JESD204B IP Core and AD9162 Hardware CheckoutReport

2016.12.06

AN-785 Subscribe Send Feedback

The JESD204B IP core is a high-speed point-to-point serial interface intellectual property (IP).

The JESD204B IP Core has been hardware-tested with a number of selected JESD204B-compliant DAC(digital-to-analog converter) devices.

This report highlights the interoperability of the JESD204B IP Core with the AD9162 converter evaluationmodule (EVM) from Analog Devices Inc. (ADI). The following sections describe the hardware checkoutmethodology and test results.

Hardware RequirementsThe hardware checkout test requires the following hardware and software tools:

• Arria 10 GX FPGA Development Kit• ADI AD9162-FMCC-EBZ• Micro-USB cable• SMA cable• Oscilloscope

© 2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logosare trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrantsperformance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to makechanges to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version ofdevice specifications before relying on any published information and before placing orders for products or services.

ISO9001:2008Registered

www.altera.com101 Innovation Drive, San Jose, CA 95134

Hardware SetupFigure 1: Arria 10 GX FPGA Development Kit Hardware Setup

An Arria 10 GX Development Kit is used with the ADI AD9162 daughter card module installed to theFMC connector B of the development board.

• The AD9162 EVM derives power from FMC pins.• The DAC sampling clock is supplied by the ADF4355 clock generator on the DAC AD9162 EVM.• The FPGA device clock is supplied by the AD9508 clock fan-out buffer on the EVM through FMC pins.

The link and frame clocks are generated from the device clock using IOPLL.• For subclass 1, AD9508 clock generator on the EVM generates SYSREF for JESD204B IP core through

FMC pins as well as the DAC AD9162.• The sync_n signal is transmitted from the DAC to FPGA through FMC.

2 Hardware SetupAN-785

2016.12.06

Altera Corporation JESD204B IP Core and AD9162 Hardware Checkout Report

Send Feedback

Figure 2: System Diagram

DAC

AD9162

RFOUTA

RFOUTA

Arria 10 GX FPGA AD9162 Evaluation BoardFMC B

rx_serial_data[7:0] (12.5 Gbps)

cs1, cs2, cs3,sclk, miso,mosi

cs3, sclk, mosi

cs2, sclk, mosi

cs1, sclk, miso, mosi

mgmt_clk100 MHz

ref_clk120 MHz

jesd204b_ed_top.sv

jesd204b_ed.sv

Design Example

JESD204B IP Core

(Duplex)L=8, M=2, F=1

Avalon-MMInterface

signals

global_rst_n

sysref to DAC

Avalon MM Slave

Translator

Qsys System

JTAG to AvalonMaster Bridge

PIO

SignalTap II

L0 – L7

SPIMaster

SPISlave

ADF4355BCPZ

AD9508BCPZ

CLK & SYNC

sync_n

sysref

CLK

ref_clk

SPISlave

SPISlave

device_clk 312.5 MHzFPGA Ref Clock

In this setup, where LMF=821, the data rate of transceiver lanes is 12.5 Gbps. Two clock generators areavailable on the EVM – ADF4355 and AD9508. The ADF4355 clock generator uses 120MHz crystaloscillator as reference clock to generate the DAC sampling clock and reference clock for AD9508 clockgenerator. The AD9508 supplies FPGA device clock and SYSREF for FPGA through FMC pins. In additionto this SYSREF for DAC is also generated. The DAC AD9162 provides SYNC_N signal through FMC pins.The DAC operates in single JESD link in all configurations.

The clock generators and DAC are programmed by FPGA through SPI interface. The DAC provides a 4-wire SPI interface, while the clock generators on the EVM provide a 3-wire SPI interface for programming.The SPI word size is 24 bits for DAC and AD9508 while the word size is 32 bits for ADF4355 clockgenerator. A user logic is written on FPGA to take care of these differences and allow programming of all 3SPI slaves.

Hardware Checkout MethodologyThe following section describes the test objectives, procedure, and the passing criteria. The test covers thefollowing areas:

• Transmitter data link layer• Transmitter transport layer• Scrambling• Deterministic latency (Subclass 1)

AN-7852016.12.06 Hardware Checkout Methodology 3

JESD204B IP Core and AD9162 Hardware Checkout Report Altera Corporation

Send Feedback

Transmitter Data Link LayerThis test area covers the test cases for code group synchronization (CGS) and initial lane alignmentsequence.

On link start up, the receiver issues a synchronization request and the transmitter transmits /K/ (K28.5)characters. The SignalTap II Logic Analyzer tool monitors the transmitter data link layer operation.

Code Group Synchronization (CGS)

Table 1: CGS Test Cases

L in the following table indicates the number of lanes.Test Case Objective Description Passing Criteria

CGS.1 Check that /K/characters aretransmitted whensync_n isasserted.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

• jesd204_tx_pcs_data[(L*32)-1:0]• jesd204_tx_pcs_kchar_data[(L*4)-

1:0]

The following signals in <ip_variant_name>.v are tapped:

• sync_n• jesd204_tx_int

The txlink_clk is used as the samplingclock for the SignalTap II.

Each lane is represented by 32-bitdata bus in jesd204_tx_pcs_datasignal. The 32-bit data bus is dividedinto 4 octets.

Check the Code Group Synchroniza‐tion Status status in the AD9162Register.

• /K/ character or K28.5 (0xBC)is transmitted at each octet ofthe jesd204_tx_pcs_data buswhen the receiver asserts thesync_n signal.

• The jesd204_tx_pcs_kchar_data signal is asserted when-ever control characters like /K/characters are transmitted.

• The jesd204_tx_int is deas-serted if there is no error.

• The “Code Group Synchroni‐zation Status” for all lanesshould be asserted in DACRegister 0x470.

4 Transmitter Data Link LayerAN-785

2016.12.06

Altera Corporation JESD204B IP Core and AD9162 Hardware Checkout Report

Send Feedback

Test Case Objective Description Passing Criteria

CGS.2 Check that /K/characters aretransmitted aftersync_n isdeasserted butbefore the start ofmultiframe.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

• jesd204_tx_pcs_data[(L*32)-1:0]• jesd204_tx_pcs_kchar_data[(L*4)-

1:0]

The following signals in <ip_variant_name>.v are tapped:

• sync_n• tx_sysref• jesd204_tx_int

The txlink_clk is used as the samplingclock for the SignalTap II.

Each lane is represented by 32-bitdata bus in the jesd204_tx_pcs_datasignal. The 32-bit data bus is dividedinto 4 octets.

Check the following error in theAD9162 reg-ister:

• 8b/10b Not-in-Table Error• 8b/10b Disparity Error

• The /K/ character transmissioncontinues for at least 1 frameplus 9 octets.

• The sync_n and jesd204_tx_intsignals are deasserted.

• The “8b/10b Not-in-TableError” and “8b/10b DisparityError” in AD9162 registers0x46E and 0x46D respectivelyshould not be asserted.

Initial Frame and Lane Synchronization

Table 2: Initial Frame and Lane Synchronization Test Cases

L in the following table indicates the number of lanes.

AN-7852016.12.06 Initial Frame and Lane Synchronization 5

JESD204B IP Core and AD9162 Hardware Checkout Report Altera Corporation

Send Feedback

Test Case Objective Description Passing Criteria

ILA.1 Check that the /R/ and /A/characters aretransmitted at thebeginning andend of eachmultiframe.

Verify that fourmultiframes aretransmitted inILAS phase andreceiver detectsthe initial lanealignmentsequencecorrectly.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

• jesd204_tx_pcs_data[(L*32)-1:0]• jesd204_tx_pcs_kchar_data[(L*4)-

1:0]

The following signals in <ip_variant_name>.v are tapped:

• sync_n• jesd204_tx_int

The txlink_clk is used as the samplingclock for the SignalTap II.

Each lane is represented by 32-bitdata bus in jesd204_tx_pcs_data. The32-bit data bus for is divided into 4octets.

Check the following status in theAD9162 regis-ters:

• Frame Synchronization• Initial Lane Synchronization

• The /R/ character or K28.0(0x1C) is transmitted at thejesd204_tx_pcs_data bus tomark the beginning ofmultiframe.

• The /A/ character or K28.3(0x7C) is transmitted at thejesd204_tx_pcs_data bus tomark the end of eachmultiframe.

• The sync_n and jesd204_tx_intsignals are deasserted.

• The jesd204_tx_pcs_kchar_data signal is asserted when-ever control characters like /K/, /R/, /Q/ or /A/ characters aretransmitted.

• The “Frame and Initial LaneSynchronization” status for alllanes should be asserted in theAD9162 registers 0x471 and0x473 respec-tively.

ILA.2 Check theJESD204Bconfigurationparameters aretransmitted in thesecondmultiframe.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

• jesd204_tx_pcs_data[(L*32)-1:0]

The following signal in <ip_variant_name>.v is tapped:

• jesd204_tx_int

The txlink_clk is used as the samplingclock for the SignalTap II.

The system console accesses thefollowing JESD CSR registers:

• ilas_data1• ilas_data2

The content of 14 configuration octetsin second multiframe is stored in theabove 32-bit registers.

Check the following status and errorin the AD9162 register:

• Good Checksum• Configuration Mismatch Error

• The /R/ character is fol-lowedby /Q/ character or K28.4(0x9C) in the jesd204_tx_pcs_data at the beginning of secondmultiframe.

• The jesd204_tx_int isdeasserted if there is no error.

• The JESD204B parameters readfrom ilas_data1, ilas_data2registers are the same as theparameters set in theJESD204B IP Core Qsysparameter editor.

• The “Link ConfigurationMismatch Error” in theAD9162 register 0x4BB shouldnot be asserted and the “GoodChecksum” status for theAD9162 register 0x472 shouldbe asserted.

6 Initial Frame and Lane SynchronizationAN-785

2016.12.06

Altera Corporation JESD204B IP Core and AD9162 Hardware Checkout Report

Send Feedback

Test Case Objective Description Passing Criteria

ILA.3 Check theconstant patternof transmitteduser data after theend of 4thmultiframes.

Verify that thereceiver success‐fully enters userdata phase.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

• jesd204_tx_pcs_data[(L*32)-1:0]

The following signals in <ip_variant_name>.v are tapped:

• jesd204_tx_int

The txlink_clk is used as the samplingclock for the SignalTap II.

The system console accesses the JESDCSR register - tx_err.

Check the following errors in theAD9162 register:

• Lane FIFO Full• Lane FIFO Empty

• When scrambler is turned off,the first user data istransmitted after the last /A/character, which marks the endof the 4th mul-tiframetransmitted.(1)

• Bits 2 and 3 of the JESD tx_errregister are not set to “1”.

• The “Lane FIFO Full” and“Lane FIFO Empty” in theAD9162 registers 0x30C and0x30D should not be asserted.

• The jesd204_tx_int isdeasserted if there is no error.

Transceiver Transport LayerTo verify the data integrity of the payload data stream through the TX JESD204B IP core and transportlayer,the DAC’s JESD core is configured to check short transport layer test pattern that is transmitted fromFPGA’s test pattern generator. The DAC JESD core checks the transport layer test patterns based on F = 1,2, 4 or 8 configuration. The short test pattern has a duration of one frame period and is repeated continu-ously for the duration of the test.

To verify that data from the FPGA digital domain is successfully sent to the DAC analog domain, theFPGA is configured to generate a sinewave. Connect an oscilloscope to observe the waveform at the DACanalog channels.

This figure shows the conceptual test setup for data integrity checking.

(1) When scrambler is turned on, the data pattern cannot be recognized after the 4th multiframe in ILASphase.

AN-7852016.12.06 Transceiver Transport Layer 7

JESD204B IP Core and AD9162 Hardware Checkout Report Altera Corporation

Send Feedback

Figure 3: Data Integrity Check Using Short Transport Layer Pattern Checker

The SignalTap II Logic Analyzer tool monitors the operation of the TX transport layer.

PatternGenerator

FPGA

DAC

TXJESD204B IP Core

PHY and Link Layer

RXPHY and Link Layer

TXTransport Layer

RXTransport Layer

PatternChecker

Table 3: Transport Layer Test Cases

Test Case Objective Description Passing Criteria

TL.1 Check the transport layermapping using STPL testpattern.

The following signals in altera_jesd204_transport_tx_top.sv are tapped:

• jesd204_tx_data_valid• jesd204_tx_data_ready

The following signals in jesd204b_ed.svare tapped:

• jesd204_tx_int

The txframe_clk is used as the SignalTapII sampling clock.

Check the following status in the DAC:

• STPL teststatus

• The jesd204_tx_data_ready andjesd204_tx_data_valid signals areasserted.

• The STPL error forall DACs is checkedin DAC register0x32F and jesd204_tx_int signal shouldbe deasserted.

TL.2 Verify the data transferfrom digital to analogdomain

Enable sinewave generator in the FPGAand observe the DAC analog channeloutput on the oscilloscope.

• A monotonesinewaveis observedon the oscilloscope

ScramblingWith descrambler enabled, the transport layer test pattern checker at the DAC JESD core checks the dataintegrity of scrambler in the FPGA.

The SignalTap II Logic Analyzer tool monitors the operation of the TX transport layer.

8 ScramblingAN-785

2016.12.06

Altera Corporation JESD204B IP Core and AD9162 Hardware Checkout Report

Send Feedback

Table 4: Scrambler Test Cases

Test Case Objective Description Passing Criteria

SCR.1 Check the functionality ofthe scrambler using shorttransport layer test patternas specified in theparameter configuration.

Enable descrambler at the DAC JESDcore and scrambler at the TX JESD204BIP core.

The signals that are tapped in this testcase are similar to test case TL.1

Check the following status in the DAC:

• STPL test status

• Thejesd204_tx_data_ready and jesd204_tx_data_validsignals are asserted.

• The STPL error forall DACs is checkedin DAC register0x32F and jesd204_tx_int signal shouldbe deasserted.

SCR.2 Verify the data transferfrom digital to analogdomain

Enable descrambler at the DAC JESDcore and scrambler at the TX JESD204BIP core.

Enable sine wave generator in the FPGAand observe the DAC analog channeloutput on the oscilloscope.

A monotone sine waveis observed on theoscilloscope.

Deterministic Latency (Subclass 1)Figure below shows a block diagram of the deterministic latency test setup. The AD9508 clock fan-outbuffer provides periodic SYSREF pulses for both the AD9162 and JESD204B IP Core. The period ofSYSREF pulses is configured to 2 Local Multi Frame Clocks (LMFC). The SYSREF pulse restarts the LMFcounter and realigns it to the LMFC boundary.

Figure 4: Deterministic Latency Test Setup Block Diagram

Arria 10 GX FPGA Development Kit DAC AD9162FMC

MSB

t0 t1

16 bit digital sample 8000h

Total Latency

Single PulseGenerator

TX TransportLayer

Oscilloscope

Ch 1 Ch 2

Tx JESD204BIP Core PHY &

Link Layer

JESD204BIP Core

DigitalBlocks

DAC

0V

The FPGA generates a 16-bit digital sample with a value of 8000 hexadecimal number at the transportlayer. The most significant bit of this digital sample has a logic 1 and this bit is pin out at FPGA. This bit isprobed at oscilloscope channel 1. The DAC analog channel is probed at oscilloscope channel 2. With two's

AN-7852016.12.06 Deterministic Latency (Subclass 1) 9

JESD204B IP Core and AD9162 Hardware Checkout Report Altera Corporation

Send Feedback

complement value of 8000h, a pulse with the amplitude of negative full range is expected at DAC analogchannel output. The time difference between the pulses at channel 1 (t0) and channel 2 (t1) is measured.This is the total latency of the JESD204B link, the DAC digital blocks, and analog channel.

Table 5: Deterministic Latency Test Cases

Test Case Objective Description Passing Criteria

DL.1 Measure the total latency. Measure the time differencebetween the rising edge of pulses atoscilloscope channel 1 and 2.

The latency shouldbe consistent.

DL.2 Re-measure the total latency afterDAC power cycle and FPGAreconfiguration.

Measure the time differencebetween the rising edge of pulses atoscilloscope channel 1 and 2.

The latency shouldbe consistent.

JESD204B IP Core and DAC ConfigurationsTheJESD204B IP Core parameters (L, M and F) in this hardware checkout are natively supported by theAD9162 device's configuration registers. The transceiver data rate, sampling clock frequency, and otherJESD204B parameters comply with the AD9162 operating conditions.

The hardware checkout testing implements the JESD204B IP Core with the following parameter configura‐tion.

Table 6: Parameter Configuration

Global setting for all configuration:

• N = 16• N' = 16• CS = 0• CF = 0• Subclass = 1• Lane Rate (Gbps) = 12.5• FPGA Device Clock (MHz) = 312.5 (2)

• FPGA Management Clock (MHz) = 100• FPGA Frame Clock (MHz) = 312.5(3)

• FPGA Link Clock (MHz) = 312.5(4)

• Character Replacement = Enabled• PCS Option = Soft PCS

(2) The device clock is used to clock the transceiver and IO PLL.(3) The frame clock is derived from the device clock using an IO PLL.(4) The link clock is derived from the device clock using an IO PLL.

10 JESD204B IP Core and DAC ConfigurationsAN-785

2016.12.06

Altera Corporation JESD204B IP Core and AD9162 Hardware Checkout Report

Send Feedback

LMF HD S DAC SamplingClock (GHz)

DAC Interpolation Data Pattern(5)

124 0 1 5 16 1. Sine2. Single pulse3. Constant

• M0S0:0xF1E2• M1S0:0xD3C4

222 0 1 5 8 1. Sine2. Single pulse3. Constant

• M0S0:0xF1E2• M1S0:0xD3C4

324 0 3 3.75 4 1. Sine2. Single pulse

421 1 1 5 4 1. Sine2. Single pulse3. Constant

• M0S0:0xF1E2• M1S0:0xD3C4

622 0 3 3.75 2 1. Sine2. Single pulse

811 1 4 5 1 1. Sine2. Single pulse3. Constant

• M0S0:0xF1E2• M0S1:0xD3C4• M0S2:0xB5A6• M0S3:0x9780

(5) Sine wave pattern is used in TL.2 and SCR.2 test cases to verify that pattern generated in the FPGA transportlayer is transmitted by DAC analog channel. Single pulse pattern is used in deterministic latency measure‐ment test cases DL.1 and DL.2 only. Constant pattern is used to check the STPL test. DAC does not supportSTPL test for modes with 3 and 6 lanes.

AN-7852016.12.06 JESD204B IP Core and DAC Configurations 11

JESD204B IP Core and AD9162 Hardware Checkout Report Altera Corporation

Send Feedback

LMF HD S DAC SamplingClock (GHz)

DAC Interpolation Data Pattern(5)

821 1 2 5 2 1. Sine2. Single pulse3. Constant

• M0S0:0xF1E2• M0S1:0xD3C4• M1S0:0xB5A6• M1S1:0x9780

Test ResultsThe following table contains the possible results and their definition.

Table 7: Results Definition

Result Definition

PASS TheDevice Under Test (DUT) was observed to exhibit conformant behavior.PASS with comments TheDUT was observed to exhibit conformant behavior. However, an additional

explanation of the situation is included, such as due to time limitations only aportion of the testing was performed.

FAIL The DUT was observed to exhibit non-conformant behavior.Warning TheDUT was observed to exhibit behavior that is not recommended.Refer to comments From the observations, a valid pass or fail could not be determined. An

additional explanation of the situation is included.

The following table shows the results for test cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, and SCR.1with different values of L, M, F, K, subclass, data rate, sampling clock, link clock and SYSREF frequencies.

Table 8: Results Definition

Link clock (MHz) = 312.5Test L M F SCR K Lane rate

(Gbps)Sampling

Clock(GHz)

SYSREF pulsefrequency

(MHz)

Result

1 1 2 4 0 32 12.5 5 9.765 Pass2 1 2 4 1 32 12.5 5 9.765 Pass

(5) Sine wave pattern is used in TL.2 and SCR.2 test cases to verify that pattern generated in the FPGA transportlayer is transmitted by DAC analog channel. Single pulse pattern is used in deterministic latency measure‐ment test cases DL.1 and DL.2 only. Constant pattern is used to check the STPL test. DAC does not supportSTPL test for modes with 3 and 6 lanes.

12 Test ResultsAN-785

2016.12.06

Altera Corporation JESD204B IP Core and AD9162 Hardware Checkout Report

Send Feedback

Test L M F SCR K Lane rate(Gbps)

SamplingClock(GHz)

SYSREF pulsefrequency

(MHz)

Result

3 2 2 2 0 32 12.5 5 19.5312 Pass4 2 2 2 1 32 12.5 5 19.5312 Pass5 3 2 4 0 32 12.5 3.75 9.765 Pass6 3 2 4 1 32 12.5 3.75 9.765 Pass7 4 2 1 0 32 12.5 5 39.0625 Pass8 4 2 1 1 32 12.5 5 39.0625 Pass9 6 2 2 0 32 12.5 3.75 19.5312 Pass

10 6 2 2 1 32 12.5 3.75 19.5312 Pass11 8 1 1 0 32 12.5 5 39.0625 Pass12 8 1 1 1 32 12.5 5 39.0625 Pass13 8 2 1 0 32 12.5 5 39.0625 Pass14 8 2 1 1 32 12.5 5 39.0625 Pass

The following table shows the results for test cases DL.1 and DL.2 with different values of L, M, F, K,subclass, lane rate, sampling clock, link clock and SYSREF pulse frequencies. Also DAC registersLMFCDel (LMFC offset) and LMFCVar (RBD offset) configured with values to achieve deterministiclatencies are tabulated.

Table 9: Results for Deterministic Latency Test

• Subclass = 1• K = 32• Lane rate (Gbps) = 12.5• Link Clock (MHz) = 312.5

S.no L M F Samplin gClock(GHz)

LMFCDel

LMFCVar

SYSREF pulsefrequency

(MHz)

Total Latency Result

1 1 2 4 5.0 0x1D 0x4 9.765 Pass (367.4-367.8 ns)2 2 2 2 5.0 0x8 0xA 19.5312 Pass (236.4-237.0 ns)3 3 2 4 3.75 0x1D 0x4 9.765 Pass (195.6-196.4 ns)4 4 2 1 5.0 0 0x1F 39.0625 Pass (180.8-181.4 ns)5 6 2 2 3.75 0xD 0x4 19.5312 Pass (146.2-147.2 ns)6 8 1 1 5.0 0x6 0x4 39.0625 Pass (119.6-120.6 ns)7 8 2 1 5.0 0x6 0x6 39.0625 Pass (139.6-140.4 ns)

AN-7852016.12.06 Test Results 13

JESD204B IP Core and AD9162 Hardware Checkout Report Altera Corporation

Send Feedback

Figure 5: Sine Wave at DAC Analog Channel OutputFigure shows the sine wave output from DAC analog channel.

14 Test ResultsAN-785

2016.12.06

Altera Corporation JESD204B IP Core and AD9162 Hardware Checkout Report

Send Feedback

Figure 6: Deterministic Latency Measurement for LMF = 324 ConfigurationFigure shows the time difference between pulses in deterministic latency measurement for LMF = 324Configuration

Test Result CommentsIn each test case, the TX JESD204B IP core successfully initializes from CGS phase, ILA phase, and untiluser data phase. The behavior of the TX JESD204B IP core meets the passing criteria.

No data integrity issue is observed from the short transport layer (STPL) test pattern checkers at DACJESD core for all modes except with 3 and 6 lanes. In these modes, the DAC does not support the STPLtest. Sine wave at transmitted frequency is observed at analog channel when sine wave generators in FPGAare enabled for all supported JESD modes.

In the deterministic latency measurement, consistent total latency is observed across the JESD204B linkand DAC analog channels.

Document Revision History

Date Version Changes

December 2016 2016.12.06 Initial release.

AN-7852016.12.06 Test Result Comments 15

JESD204B IP Core and AD9162 Hardware Checkout Report Altera Corporation

Send Feedback