Upload
alan-tran
View
28
Download
0
Embed Size (px)
Citation preview
AMS Workshop
by Cadence VCAD design services SA
CERN 16/11 – 20/11, 2009
Welcome
16/11/09 [email protected] 2
Welcome to the Analog & Mixed Signal Training Workshop.
Presenting Methodology Workflows customized to the CMOS8RF (130nm) Mixed Signal Design Kit V1.6.
Focusing on Mixed Signal designs with big Analog and small Digital blocks.
CMOS8RF Mixed Signal design kit
16/11/09 [email protected]
IBM Standard
cell libraries
IBM PDK
Mixed Signal Design
Kit
CAE Tools
Key Features: IBM PDK V1.6 IBM Standard cell and IO pad libraries
Physical Layout views available. Separate substrate contacts
for mixed signal low noise applications. Access to standard cells libraries is legally
covered by already established IBM CDAs
New versions of CAE Tools Open Access database support.
Interoperability of Virtuoso and SOC-Encounter platforms.
Compatible with the “Europractice” distributions. Virtuoso IC 6.1.3, Analog front-end design SOC Encounter 7.1 Mixed signal back-end design IUS 8.1 support for simulations. Calibre support for Sign-Off Physical Verification
Support for LINUX Platform (qualified on RHEL4) Two independent design kits:
CMOS8RF-LM (6-2 BEOL)
CMOS8RF-DM (3-2-3 BEOL)
3
CMOS8RF Mixed Signal Workflows
16/11/09 [email protected]
Design Workflows
Digital Library
PDK Analog & Mixed Signal (AMS) Workflows.
Formalize the design work by employing standardized and validated Design Workflows.
Formalize the design work across design teams in common projects.
Provide a repository with reference design examples.
Development work subcontracted to Cadence, VCAD design services.
Close collaboration of CERN - VCAD - IBM VCAD brought in their invaluable expertise on the CAE tools IBM provided the physical IP blocks and important technical assistance CERN assisted the development and validated the design kit functionality.
4
Design Kit Distribution
The Design kit V1.6 is available to all collaborating institutes that have signed a CDA with IBM.
No access fees required.
Pay-per-use scheme. Prototyping must be done exclusively through CERN. A 7% fee will be applied on the prototyping costs. This should cover part of the design kit maintenance costs in the long
term.
16/11/09 [email protected] 5
The CERN ASIC support website
16/11/09 [email protected]
http://cern.ch/asic-support
Download Design Kits and access technical documents (restricted access)
Information about MPW runs and foundry access services.
Communicate news and User support feedback forms and access request forms.
This website replaces our ‘afs’ based download facility.
6
Objectives
Workshop Targets: Present the IBM CMOS8RF (130nm) Mixed Signal Kit. Present Workflows for Analog, Digital and Mixed Signal designs. Introduce the new Platform of Cadence CAE Tools.
This is NOT: A course on analog or digital designing. An advanced course targeted to a specific Cadence Tool.
16/11/09 [email protected] 7
AMS Workshop Contents Day 1 (Lead by Ahmed Noeman)
- Introduction to AMS kit Workshop - Functional Verification : Digital Simulation Flow - Functional Verification : AMS Simulation from command-line - Functional Verification : AMS Simulation from DFII
Day 2 (Lead by Ahmed Noeman) - Analog IP Characterization : ADEXL - Overview of IC6.13 (ADEXL and VSE) - Analog Block Creation: Constraints
Day 3 (Lead by Vincent Cao Van Phu) - Hierarchical Floorplaning (Virtuoso based) - CDB IP Import to OA database for IC61 Methodology
Day 4 (Lead by Vincent Cao Van Phu) - Digital Block Implementation - Block IP Characterization Back End - Digital IP Characterization Front-End
Day 5 (Lead by Vincent Cao Van Phu) - Constraint Driven Analog Block Creation Back-End - DRC (Calibre + Assura workflows) - LVS (Callibre + Assura workflows) - Extraction - Round table discussion and workshop evaluation (30min).
16/11/09 [email protected] 8
Analog &
Mixed Signal
Digital
Physical Verification
Daily Schedule
9:00 - 10:00 (15 min coffee break)
10:15 - 12:00 (lunch break)
14:00 - 15:45 (15 min coffee break)
16:00 – 17:30
16/11/09 [email protected] 9
16/11/09 [email protected] 10