amba_tbsc

AMBA TGuideProduct VersMay 2005ransactors User and Reference

ion 5.4

2004 Cadence DPrinted in the Unite

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AMBA Transactors User and Reference Guide

May 2005

Preface . . . How to Use PrerequisitePlatform Sup

1TransactioIntroduction . Transaction-Bas

Non-TransacTransaction-

Why move to TrOther Sourc

2Getting StaInstallation and

InstallationAMBA Configur

Running theAMBA Transact

ConstructionConstructionConstructionVerilog SystVHDL Syste

3IntroductioIntroduction .

Conten

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1This Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

n-Based Verification Overview . . . . . . . . . . . . . . . . . . . . . . . 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ed Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6tion-Based Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Based Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7ansaction Based Verification? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7es of Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

rted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11or Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 and Instantiation of the Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 and Instantiation of the Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 and Instantiation of the Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

em . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

ts1 Product Version 5.4

n to the AHB Transactors Family . . . . . . . . . . . . . . . . . . . 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31


May 2005

Verification of ASingle-mastSingle-slaveMulti-MasterMulti-slave DAdditional in

Transactor InterTransactor CTransactor TTransactor PTransactor TTransaction

Stimulus GenerDevice Emulato

4AHB TransAHB Master Tra

AHB MasterMaster ConfiMaster TranPull InterfacPush InterfaThe ahb_argThe ahb_argCreating andAHB MasterAHB MasterEndian FormStart Delay SBus RequesTransfer LocInsertion of Retried bursEarly terminHB Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32er Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 DUV Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38UV Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

formation on the verification configurations . . . . . . . . . . . . . . . . . . . . . . 39faces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40onfiguration Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40ransaction-Level Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40in-Level Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40ransaction View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Searches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41ator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

actor Reference Information . . . . . . . . . . . . . . . . . . . . . . . . 43nsactor Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Transactor Overall Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45guration Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

saction-level Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50ce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52_t Public Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59_t static public methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 using transaction handles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Pin-Level Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Transaction Recording . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77at of the Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84pecifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85BUSY cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88ated bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882 Product Version 5.4


May 2005

AHB 1K LineAHB Slave TranAHB Slave Tran

AHB Slave TAHB Slave DConfiguratioAHB Slave DPush InterfaAHB Slave PAHB Slave TSlave Burst

AHB Monitor TrAHB MonitoAHB MonitoAHB MonitoCompliance

AAppendix A

Index. . . . . .

Glossary . Burst Protection Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88sactor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89sactor Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92ransactor Configuration Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92evice Emulator Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

n Argument Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98evice Emulator Transaction-Level Interface . . . . . . . . . . . . . . . . . . . . . 113

ce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114ort Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120ransaction Recording . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123Pipelined Stream Parent-Child relationship . . . . . . . . . . . . . . . . . . . . . . 127ansactor ( ahb_monitor_t ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128r Configuration Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129r Pin-Level Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138r Transaction Recording . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

- References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1613 Product Version 5.4


May 2005 4 Product Version 5.4


May 2005

Preface

The purpose ofin SystemC. Thprotocol. Cadenverification of ATestBuilder-Sys

How to Use T

This document

Chapter 1, Tranbased verificatio

Chapter 2, Get

Chapter 3, Introprocedures requon the creation

Chapter 4, AHBeach of the Tranand the AHB M

Appendix A - ReTransactors tha

Prerequisites

A verification tea

C++ (Requ Verilog, VH

See the NCinformationthis document is to describe the Cadence AMBA-AHB transactors developede Transactors are used to test design that are compliant with the AMBA AHBce Transactors are behavioral models intended to support the functionalSIC and system designs. These models are written in C++ using thetemC libraries provided in the Cadence LDV package.

his Document

is organized in the following manner:

saction-Based Verification Overview, gives you an overview of transaction-n.

ting Started, provides you with an overview of each of the Transactors.

duction to the AHB Transactors Family, gives you instructions on theired to set up and run the Transactors. This chapter also provides information

of stimulus.

Transactor Reference Information, gives you reference information aboutsactors. They include the AHB Master Transactor, the AHB Slave Transactor,onitor Transactor.

ferences includes references to topics related to tools used with thet are not described in this document.

m using this document should have the following set of knowledge and skills:

ired)DL, NC-Sim or other HDL

-Verilog Simulator Help and the NC-VHDL Simulator Help for1 Product Version 5.4

on the Cadence simulators.


May 2005

SystemC (RSee the NC

Simvision W

See the Sim

TxE (TransSee the TraTransactio

Knowledge

Note: Skills indcontribute to a b

Platform Sup

The AMBA-AHB

Sun-Solaris

Linux Red-

HP-UX11.0Preface

ecommended)-SC Simulator User Guide for information on Cadence SystemC.

aveform Window (Recommended)Vision User Guide for information on the Simvision Waveform Window.

action Explorer) (Recommended)nsaction Explorer User Guide for infomation on TxE. Also see then-Based Verification User Guide for infomation on transactors.

of AMBA AHB Protocol Specifications - (Recommended)icated as Recommended are not required, but knowledge of those skills willetter understanding of the tasks.

port

Transactors have been tested and are supported on the following platforms:

8

Hat 7.12 Product Version 5.4


May 2005

Contact InFor answers to yyour sales repre

Additional informwww.cadence.co

The table below

Table 1-1

RegionNorth America

Japan

Central Europe

Northern Europ

Southern Europ

Hong KongKoreaPreface

formationour sales questions please send an e-mail to [email protected] or contactsentative.

ation can be found on the web at:m/methodology_services.

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E-mail Phone Fax4 Product Version 5.4


May 2005

Transac

This chapter givabout the benefimethodology ca

This chapter co

Introduction

Transaction

Why move

IntroductiTransaction-basdebug simulatio

Transaction-bas

A transaction isinterface. Transpacket through

A transactor is aunder verificatiotest program an

Cadence has deand the PCI famtransactor, a tesare implemente1tion-Based Verification Overview

es you an overview of transaction-based verification. The chapter tells youts of transaction-based verification and how a transaction-based verificationn help your verification effort.

ntains the following topics:

on page 5

-Based Verification on page 6

to Transaction Based Verification? on page 7

oned verification lets you develop simulation test benches and analyze andns at a higher level of abstraction than simply using an HDL.

ed verification consists of transactions and transactors.

a high-level transfer of data from one device to another over a well-definedactions can be as simple as a read or write, or as complex as passing a dataa design.

device that executes a transaction. The transactor connects to a designn (DUV) at a design interface and serves as an abstraction layer between thed the design.

veloped key transactors like the AMBA AHB transactor, the USB transactor,ily of transactors. These transactors are written in C++/SystemC. To use at engineer writes tests in C++/SystemC, calling tasks and functions, whichd in the transactor.5 Product Version 5.4


May 2005

TransactioTransaction-basmeans that a teverification effortransaction-basand transforms

Non-Transac

An example of atransfer level (Rverification setugenerator.

Figure 1-1 Non

In operation, thealso checks thestimuli/responsewrites signal-levDUV interface.

For example, aswith typical sign(such as read/toggling all of thprotocol.

Stimuli/ResGeneraTransaction-Based Verification Overview

n-Based Verificationed verification raises the level of abstraction from signals to transactions. Thisst engineer can concentrate on writing tests and improving the overallt rather than being concerned with low-level signal-based tasks. Aed verification methodology also encourages the re-use of test componentscomponents like transactors into intellectual property (IP).

tion-Based Verification

typical setup for the verification of a block- and chip-level digital registerTL) design is illustrated in Figure 1-1 on page 6. As shown in the figure, thep consists of the design under verification and a stimuli and response

-Transaction-Based Verification Architecture

DUV is provided with test stimuli from a stimuli/response generator, whichresults of the test. The interface between the testbench module (which is thegenerator) and the DUV are at the signal level. Therefore, the test engineer

el tests, which include the details of the communication of the tests with the

sume that the interface between the stimuli generator and the DUV is a busal-level elements such as a data bus, an address bus, and control signalsno_write, chip_select, and so on). A test engineer needs to write testsese signals, in the correct sequence, in order to generate the correct interface

Design Under Verification(RTL code)

ponsetor6 Product Version 5.4


May 2005

Transaction-

Figure 1-2 on ptransaction-basstimuli/response

The test engineis as follows:

write(data

The details of hprotocol specificof by the transa

Figure 1-2 Tra

Why moveWorking at the tmeasure functioand bus protoco

A transaction-baconcepts includ

Self-checki

Bus monito

Random te

Constraine

The result is a m

Stimuli/ResponGeneratorTransaction-Based Verification Overview

Based Verification

age 7 shows a transaction-based verification architecture. In theed architecture an extra layer, the transactor, is introduced between the generator and the design under verification.

er writes tests using transactions. A simple example of a possible transaction

, address)

ow the write transaction is translated into signal accurate values andsequence activating the data, address and the control signals is taken care

ctor.

nsaction-Based Verification Architecture

to Transaction Based Verification?ransaction level lets a test engineer create tests, debug the design, andnal coverage without the need for dealing with the details of low-level signalsls.

sed verification methodology supports and facilitates several verificationing:

ng tests

rs

sts

d random tests

Design Under Verification(RTL code)

se Transactor7 Product Version 5.4

ore complete, more efficient verification of the design.


May 2005

Other Source

For more informthe subsequentavailable in the Source Link. Se

For an introductsee A Tutorial and Stuart Swahttp://www.tTransaction-Based Verification Overview

s of Information

ation on transactions see the Transaction Based Verification Guide andchapters in this user guide. The Transaction Based Verification Guide isCDSDoc online documentation library from your CVE installation or frome the Whats New for instructions on accessing documents from Source Link.

ion to the transaction based verification methodology adopted by CadenceIntroduction on the New SystemC Verification Standard, by C. Norrisn, in the Technical Papers section at http://www.systemc.org and atestbuilder.net/whitepapers/sc_tut.pdf.8 Product Version 5.4


May 2005

Getting

This chapter detransactors and

Installation

AMBA Con

AMBA Tran

InstallatioThe following sotransactors:

The Ca

NC-SC

NC-Ve

C++ C

SimVis

Transa

Note: Check tha specific releas

Installation

The AMBA tranusing SoftLoad through the com2 Started

fines the procedures you use to prepare and use the AMBA family of contains the following topics:

and Licensing on page 5

figuration on Page 6

sactor Construction on page 7

n and Licensingftware should be installed on your system prior to installing and using the

dence Verification Extensions (Formerly known as TestBuilder-SC)

rilog, NC-VHDL, or the Cadence mixed-language simulator

ompiler

ion Waves (Recommended/Optional)ction Explorer (TxE) (Recommended/Optional)e Whats New for specific versions of each of the tools that are supported fore.

sactors are installed using Cadences SoftLoad utility. For instructions onsee the Cadence Installation Guide. The installation guide takes youplete installation procedure through testing the validity of your installation.9 Product Version 5.4


May 2005

Installation Dir

Installing the tratools.platfor

Where platfofollowing path istools.sun4v/tv

SoftLoad install

exampthat cadocum

inclufile.

lib

veriltransa

vhdl

scripts

AMBA CoThe library for Acontains a librarup the correct c

Source

Type thsetenv

Changtools.

Run thcomman

When ./setuGetting Started

ectory

nsactor creates the following directory:m/tvmsc/amba20

rm is sun4v for Solaris, hppa for HP-UX, lnx86 for Linux. For example the for the Solaris platform:msc/amba20

s all component files in subdirectories as follows:

lesContains an example testbench, example test case, and a run scriptn be used for incoming inspection of the installation. Refer to the READMEent at this location.

deContains header files required to link in the components shared object

Contains the required library files for the components shared object file.ogContains the Verilog wrappers for master, slave, and monitorctors.

Contains the VHDL wrappers for master, slave, and monitor transactors.

Contains the perl script for setting the configuration.

nfigurationMBA transactors is available in the lib subdirectory. This subdirectoryy compiled with GNU and NATIVE compilers on different platforms. To setonfiguration following steps are required:

the IUS5.3 environment

e following line to define the required environment variable: AMBA_TVM_TOP tools.platform/tvmsc/amba20

e directories to the following directory:platform/tvmsc/amba20

e following command:d ./setup

you run the command, the following output appears on your screen:10 Product Version 5.4

p


May 2005

perl: ======

The fosuppor

======

Enter

Instal... Do

Verify libahblibahblibahb

Running the

After you have sfollowing:

1. Change dirtools.sun4

2. Run one of

a. make

b. make

Note: Refe

3. Type the fosimvision

AMBA TraThe AMBA tranwhich you use t

Stimulus generapush_stimulus_Getting Started

tools./tvmsc/amba20/lib=======================================================

llowing selection of LDV Releases and Compilers areted in this release :=======================================================

1. IUS 5.3 gnu2. IUS 5.3 native

Selection: 2ling Library for IUS 5.3 and nativene

that the following softlinks are created in the lib subdirectory:20_32b.so -> libamba20-bw32-ius53-native.so20_64b.so -> libamba20-bw64-ius53-native.so20_128b.so -> libamba20-bw128-ius53-native.so

Example

etup the environment, you can run the example. To run the example do the

ectories to the following directory:v/tvmsc/amba20/example/run_ahb_master_slave

the following commands:

exe_push_32

exe_push_32 -f Makefile.native

r to the README file for details on the make file.

llowing command to view transaction recording:txdb

nsactor Constructionsactors are written in SystemC and are provided to you with HDL wrappers,o connect to the design under verification (DUV) and the stimulus.11 Product Version 5.4

tion for the AMBA transactor is modeled by the class:generator_t


May 2005

Members and mcontrol of the m

The class pushclass push_sti public:

//Push Intsc_port_emulator_control_port;evice Emulator Configuration Objectdevice_emulator_config_t emulator_config;

re used to keep a reference of all the transactions submitted tosterction_list_t master_transaction_handles;

e that centralizes the transactors configuration attributesuration_t transactors_config;

sh_stimulus_generator_t) :_tx_port("master_tx_port"),_control_port("master_control_port"),control_port("slave_control_port"),r_control_port("monitor_control_port"),_emulator_control_port("device_emulator_control_port"),or_config(device_emulator_control_port),_transaction_handles("master_tx_list", ahb_arg_handle_t() )

EAD(tb_main);

ction spawned in this stimulus12 Product Version 5.4

in();timulus function


May 2005

void run_m

private:void ivoid t

};

// tb_main metvoid push_stim{ cout send_control(transactors_config);

ned addr = MIN_SLAVE_ADDRESS;addr next();//randomize data byte13 Product Version 5.4

igure the device emulator with data, wait cycles and response typesor_config.write_emulator(addr,


May 2005

}//Configur//RETRY/SPemulator_c

for( int i

//crea//and master

unsignrandomstartA

//Conf// byt//Tran

master

master

tb_out

master

} //end o

//Make sur//completemaster_traGetting Started

randomDataByte->read(), response_typeBag.peekRandom(), responseDelayBag.peekRandom(), 0);

e device emulators to reset responses to OKAY after aLIT/ERROR transferonfig.set_reset_response_after_use( true );

=1; inext();ddr = randomStartAddr->read();igure a Burst with incremental data value (incremented at eache address).sfer size: 1 byte, No data self-checking, Burst length is 10 if INCR

_transaction_handles[i]->fill_data_burst( burstType, startAddr, AHB_SIZE_BYTE, false, INCR,

10, 0);

_transaction_handles[i]->set_write_transaction(readWriteBag.peekRandom() );


May 2005

tb_out


May 2005

if(slv == cout slave

The slave is boustimulus_p

Construction

A SystemC poris shown below

sc_port


May 2005

The top-level Ve

timescale 1 n

//The testbenc//for a systemifdef NCSCmodule topTest

elsemodule topTest initial $sc_endifendmodule

module top; //Definitionifdef DATA32 parameter

else ifdef DATA6 parameter

else ifdef DAT paramet

elseparamete

the command li endif // endif // Dendif // DATA

// Master S wire wire wire wire wire [31:0] wire [1:0] wire wire [2:0] Getting Started

rilog module with the transactor trio connected to the stimulus is as follows:

s/1 ps

h is empty, it is used as the top level entry pointc netlist.

bench (* integer foreign = "SystemC"; *);

bench;cosim_init;

of the Data bus width parameter

data_bus_width = 32;

4 data_bus_width = 64;

A128er data_bus_width = 128;

r data_bus_width = 128; //Default value if no DATAxx was passed inne DATA128ATA6432

pecific AHB Signals ahb_gnt_M1; ahb_gnt_M2; ahb_req_M1; ahb_lock_M1; ahb_addr_M1; ahb_trans_M1;17 Product Version 5.4

ahb_write_M1; ahb_size_M1;


May 2005

wire [2:0] wire [3:0] wire [data_ wire wire wire [31:0] wire [1:0] wire wire [2:0] wire [2:0] wire [3:0] wire [data_

// Slave Sp wire wire [15:0] wire wire [1:0] wire [data_ wire wire [15:0] wire wire [1:0] wire [data_

// Multiple wire [31:0] wire [1:0] wire wire [2:0] wire [2:0] wire [3:0] wire [data_ wire [data_ wire wire [1:0]

// System C reg

reg Getting Started

ahb_burst_M1; ahb_prot_M1;bus_width-1:0] ahb_w_data_M1; ahb_req_M2; ahb_lock_M2; ahb_addr_M2; ahb_trans_M2; ahb_write_M2; ahb_size_M2; ahb_burst_M2; ahb_prot_M2;bus_width-1:0] ahb_w_data_M2;

ecific AHB Signals ahb_sel_S1; ahb_split_S1; ahb_ready_S1; ahb_resp_S1;bus_width-1:0] ahb_r_data_S1; ahb_sel_S2; ahb_split_S2; ahb_ready_S2; ahb_resp_S2;bus_width-1:0] ahb_r_data_S2;

xed signals ahb_addr; ahb_trans; ahb_write; ahb_size; ahb_burst; ahb_prot;bus_width-1:0] ahb_w_data;bus_width-1:0] ahb_r_data; ahb_ready; ahb_resp;

lock and Reset resetn;18 Product Version 5.4

clk;


May 2005

//AHB Bus O wire [3:0] wire

topTestbenc // Instance ahb_master_

// Instance ahb_slave_t

Getting Started

utputs used in Split-enables Slaves ahb_master_id; ahb_mastlock;

h topTest(); of the AHB Master TVMt ahbMaster ( .ahb_clk(clk), .ahb_resetn(resetn), .ahb_gnt(1b1), .ahb_lock(ahb_lock_M1), .ahb_req(ahb_req_M1), .ahb_resp(ahb_resp), .ahb_ready(ahb_ready), .ahb_r_data(ahb_r_data), .ahb_w_data(ahb_w_data_M1), .ahb_prot(ahb_prot_M1), .ahb_burst(ahb_burst_M1), .ahb_size(ahb_size_M1), .ahb_write(ahb_write_M1), .ahb_trans(ahb_trans_M1), .ahb_addr(ahb_addr_M1) ); of the AHB Slave TVM ahbSlave ( .ahb_clk(clk), .ahb_resetn(resetn), .ahb_ready(ahb_ready), .ahb_sel(ahb_sel_S1), .ahb_addr(ahb_addr), .ahb_write(ahb_write), .ahb_trans(ahb_trans), .ahb_size(ahb_size), .ahb_burst(ahb_burst), .ahb_w_data(ahb_w_data), .ahb_master(ahb_master_id), .ahb_mastlock(ahb_mastlock), .ahb_prot(ahb_prot), .ahb_ready_out(ahb_ready_S1),19 Product Version 5.4

.ahb_resp(ahb_resp_S1), .ahb_r_data(ahb_r_data_S1),


May 2005

// Instance ahb_standal

.............

.............

.............

// Propagate t defparam ah ahbM ahbS ahbM // // assert R // initial beg clk = 0; resetn =

repeat (Getting Started

.ahb_split(ahb_split_S1) );

of the AHB Monitor TVMone_monitor_t ahbMonitor ( .ahb_clk(clk), .ahb_resetn(resetn), .ahb_gnt({15b0,1b1}), .ahb_lock({15b0,ahb_lock_M1}), .ahb_req({15b0,ahb_req_M1}), .ahb_resp(ahb_resp), .ahb_ready(ahb_ready), .ahb_r_data(ahb_r_data), .ahb_w_data(ahb_w_data), .ahb_prot(ahb_prot), .ahb_burst(ahb_burst), .ahb_size(ahb_size), .ahb_write(ahb_write), .ahb_trans(ahb_trans), .ahb_addr(ahb_addr), .ahb_sel({15b0,ahb_sel_S1}), .ahb_master(ahb_master_id), .ahb_mastlock(ahb_mastlock), .ahb_split(ahb_split_S1) );

he data bus widthbBus.data_bus_width = data_bus_width,aster.data_bus_width = data_bus_width,lave.data_bus_width = data_bus_width,onitor.data_bus_width = data_bus_width;

eset for 10 clocks

in20 Product Version 5.4

0;10) @(posedge clk);


May 2005

resetn =

end // init // // a 50% du // always begi #10; clk = ~cl endendmodule.

Master Verilog

The Verilog wratimescale 1 n

//Verilog Wrapmodule ahb_mas

ifdef NCSC

// Note that t

(* integer fendif;

// Note that pGetting Started

1;ial begin

ty cycle clock with period 20

n

k;

Wrapper

pper for the master transactor is as follows (excerpted):s / 100 ps

per of the Master transactor that is implemented in SystemC.ter_t (ahb_clk, ahb_resetn, ahb_gnt, ahb_lock, ahb_req, ahb_resp, ahb_ready, ahb_r_data, ahb_w_data, ahb_prot, ahb_burst, ahb_size, ahb_write, ahb_trans, ahb_addr )

he foreign attribute string value must be "SystemC".

oreign = "SystemC"; *)21 Product Version 5.4

ort names must match exactly port names as they appear in


May 2005

// sc_module //// PARAMETERS parameter

// Ports input input input output

output

input [1:0] input input [data output [dat output [3:0 output [2:0 output [2:0 output

output [1:0 output [31:ifdef SCHDL Dynamic Par reg big_e

reg [31:0] reg [1:0] reg

reg [2:0] reg [2:0] reg [3:0] reg [data_b reg

reg

initial begin ahb_addr ahb_tran ahb_writ ahb_sizeGetting Started

class in SystemC; they must also match in order, mode and type.

big_endian = 1, data_bus_width = 32, addr_hold = 1;

ahb_clk; ahb_resetn; ahb_gnt; ahb_lock; ahb_req; ahb_resp; ahb_ready;_bus_width-1:0] ahb_r_data;a_bus_width-1:0] ahb_w_data;] ahb_prot;] ahb_burst;] ahb_size; ahb_write;] ahb_trans;0] ahb_addr;

ametersndian_dp;

ahb_addr;ahb_trans;ahb_write;ahb_size;ahb_burst;ahb_prot;us_width-1:0] ahb_w_data;ahb_req;ahb_lock;

= 32hFEFFE000;s = 0;22 Product Version 5.4

e = 0; = 0;


May 2005

ahb_burs ahb_prot ahb_w_da ahb_req ahb_lock //Initia big_endi end initial $scendif // ifdeendmodule

Slave Verilog W

The Verilog wratimescale 1ns//Verilog Wrapmodule ahb_slaahb_trans, ahbahb_ready_out,ifdef NCSC (* integer fendif;

// PARAMETERS parameter bi parameter da parameter sp

parameter re

// Ports input input input input input[31:0] input input[1:0] input[2:0] input[2:0] input[data_bGetting Started

t = 0; = 0;ta = 0;= 0; = 0;lize dynamic parameters.an_dp = big_endian;

_cosim_init;f SCHDL

rapper

pper for the slave is as follows: / 100 psper of the Slave transactor that is implemented in SystemC.ve_t (ahb_clk, ahb_resetn, ahb_ready, ahb_sel, ahb_addr, ahb_write,_size, ahb_burst, ahb_w_data, ahb_master, ahb_mastlock, ahb_prot, ahb_resp, ahb_r_data, ahb_split)

oreign = "SystemC"; *)

g_endian = 1;ta_bus_width = 32;lit_capable = 1;set_response_after_use = 1;

ahb_clk; ahb_resetn; ahb_ready; ahb_sel; ahb_addr; ahb_write; ahb_trans; ahb_size;23 Product Version 5.4

ahb_burst;us_width-1:0] ahb_w_data;


May 2005

input[3:0] input input[3:0] output

output[1:0] output[data_ output[15:0]ifdef SCHDL //Dynamic P reg

reg

reg

reg [9:0] reg

reg

reg [1:0] reg [data_b reg [15:0]

initial beg ahb_r_da ahb_read ahb_resp ahb_spli split_ca big_endi enable_m data_bus reset_re

end initial $scendif // ifdeendmodule

Monitor Verilog

Verilog wrappertimescale 1 n

//Verilog WrapGetting Started

ahb_master; ahb_mastlock; ahb_prot; ahb_ready_out; ahb_resp;bus_width-1:0] ahb_r_data; ahb_split;

arameters split_capable_dp; enable_memory_dp; big_endian_dp; data_bus_width_dp; reset_response_after_use_dp; ahb_ready_out; ahb_resp;us_width-1:0] ahb_r_data; ahb_split;

inta = 0;y_out = 0; = 0;t = 0;pable_dp = split_capable;an_dp = big_endian;emory_dp = enable_memory;_width_dp = data_bus_width;sponse_after_use_dp = reset_response_after_use;

_cosim_init;f SCHDL

Wrapper

for monitor is as follows:s / 100 ps24 Product Version 5.4

per of the Monitor transactor that is implemented in SystemC.


May 2005

module ahb_sta ahb_ ahb_ ahb_ ahb_ ahb_ ahb_ ahb_ ahb_ ahb_ ahb_ ahb_ ahb_ ahb_ ahb_ ahb_ ahb_ ahb_ ahb_ ahb_ )ifdef NCSC// Note that t (* integer fendif;

// Note that p// sc_module c// PARAMETERS // width of parameter da

input input input [15:0] input [15:0] input [15:0] input [1:0] input input [data_Getting Started

ndalone_monitor_t(clk,resetn,gnt,lock,req,resp,ready,r_data,w_data,prot,burst,size,write,trans,addr,sel,master,mastlock,split

he foreign attribute string value must be "SystemC".oreign = "SystemC"; *)

ort names must match exactly port names as they appear inlass in SystemC; they must also match in order, mode and type.DEFAULT VALUESthe data busta_bus_width = 128;

ahb_clk; ahb_resetn; ahb_gnt; ahb_lock; ahb_req; ahb_resp;25 Product Version 5.4

ahb_ready;bus_width-1:0] ahb_r_data;


May 2005

input [data_ input [3:0] input [2:0] input [2:0] input input [1:0] input [31:0] input [15:0] input [3:0] input input [15:0]

ifdef SCHDL // connect t initial begi end // initi initial $sc_endif // ifdeendmodule

VHDL System

At the top level,

1. Masterah

2. Slaveahb

3. Monitora

4. ahbBusa

5. topTestben

The monitor com

The top-level VHdrives the transstimulus and is library ieee;use ieee.numeruse ieee.std_lentity top isGetting Started

bus_width-1:0] ahb_w_data; ahb_prot; ahb_burst; ahb_size; ahb_write; ahb_trans; ahb_addr; ahb_sel; ahb_master; ahb_mastlock; ahb_split;

his TVM to Testbuildernal begincosim_init;f SCHDL

there are five inter-connected components:

bMaster (or Host DUV)Slave (or Device DUV)hbMonitor

hbBus

chtopTest

ponent can exist in a standalone mode.

DL code, instantiating the three transactors and the SystemC testbench thatactors, is shown below. Note that the monitor is configured in the SystemCnot standalone.

ic_std.all;ogic_1164.all;26 Product Version 5.4


May 2005

generic (bend top;

library ieee;use ieee.numeruse ieee.std_l

architecture a

component ah generic ( data_bus big_endi addr_hol port

( ahb_clk ahb_reset ahb_gnt ahb_lock ahb_req ahb_resp ahb_ready ahb_r_dat ahb_w_dat ahb_prot ahb_burst ahb_size ahb_write ahb_trans ahb_addr end componen

component ah generic ( big_endi data_bus enable_m split_ca port

( ahb_clk Getting Started

us_width : integer );

ic_std.all;ogic_1164.all;

1 of top is

b_master_t

_width : integer := 32;an : integer := 1;d : integer := 0);

: in std_ulogic;n : in std_ulogic; : in std_ulogic; : out std_ulogic; : out std_ulogic; : in std_ulogic_vector(1 downto 0); : in std_ulogic;a : in std_ulogic_vector((data_bus_width -1) downto 0);a : out std_ulogic_vector((data_bus_width -1) downto 0); : out std_ulogic_vector(3 downto 0); : out std_ulogic_vector(2 downto 0); : out std_ulogic_vector(2 downto 0); : out std_ulogic; : out std_ulogic_vector(1 downto 0); : out std_ulogic_vector(31 downto 0));t;

b_slave_t

an : integer := 1;_width : integer := 32;emory : integer := 1;pable : integer := 1);27 Product Version 5.4

: in std_ulogic;


May 2005

ahb_reset ahb_ready ahb_sel ahb_addr ahb_write ahb_trans ahb_size ahb_burst ahb_w_dat ahb_maste ahb_mastl ahb_prot

ahb_ready ahb_resp ahb_r_dat ahb_split );

end componen......

......

ahbMaster : ah

Getting Started

n : in std_ulogic; : in std_ulogic; : in std_ulogic; : in std_ulogic_vector(31 downto 0); : in std_ulogic; : in std_ulogic_vector(1 downto 0); : in std_ulogic_vector(2 downto 0); : in std_ulogic_vector(2 downto 0);a : in std_ulogic_vector((data_bus_width -1) downto 0);r : in std_ulogic_vector(3 downto 0);ock : in std_ulogic; : in std_ulogic_vector(3 downto 0);

_out : out std_ulogic; : out std_ulogic_vector(1 downto 0);a : out std_ulogic_vector((data_bus_width -1) downto 0); : out std_ulogic_vector(15 downto 0)

t;

b_master_t generic map (data_bus_width => bus_width) port map( ahb_clk => clk, ahb_resetn => resetn, ahb_gnt => mon_gnt(0), ahb_lock => ahbLock_1, ahb_req => ahbReq_1, ahb_resp => ahbResp, ahb_ready => ahbReady, ahb_r_data => ahbRData, ahb_w_data => ahbWData_1, ahb_prot => ahbProt_1, ahb_burst => ahbBurst_1, ahb_size => ahbSize_1, ahb_write => ahbWrite_1,28 Product Version 5.4

ahb_trans => ahbTrans_1, ahb_addr => ahbAddr_1 );


May 2005

ahbSlave : ahb

ahbMonitor : a

Getting Started

_slave_t generic map (data_bus_width => bus_width) port map( ahb_sel => ahbSel1, ahb_addr => ahbAddr, ahb_ready => ahbReady, ahb_write => ahbWrite, ahb_trans => ahbTrans, ahb_size => ahbSize, ahb_burst => ahbBurst, ahb_w_data => ahbWData, ahb_resetn => resetn, ahb_clk => clk, ahb_master => ahbMasterID, ahb_mastlock => ahbMastLock, ahb_prot => ahbProt, ahb_ready_out => ahbReady_S1, ahb_resp => ahbResp_S1, ahb_r_data => ahbRData_S1, ahb_split => ahbSplit_S1);

hb_standalone_monitor_t generic map (data_bus_width => bus_width) port map( ahb_clk => clk, ahb_resetn => resetn, ahb_gnt => mon_gnt, ahb_lock => mon_lock, ahb_req => mon_req, ahb_resp => ahbResp, ahb_ready => ahbReady, ahb_r_data => ahbRData, ahb_w_data => ahbWData, ahb_prot => ahbProt, ahb_burst => ahbBurst, ahb_size => ahbSize, ahb_write => ahbWrite, ahb_trans => ahbTrans,29 Product Version 5.4

ahb_addr => ahbAddr, ahb_sel => mon_sel,


May 2005

.......

.......

topTest: topTe

end a1;

Note: The sheldirectory for theyour_amba_ins

The definitions Getting Started

ahb_master => ahbMasterID, ahb_mastlock => ahbMastLock, ahb_split => ahbSplit_S1 );

stbench;

ls for the transactors are not shown here. Please refer to the following definitions of these shells.tall_dir/vhdl

follow the shell construction described in Verilog System on page 16.30 Product Version 5.4


May 2005

IntroduFamily

The Cadence AMaster TransactAHB verification

This chapter co

Introduction

Verification

Transactor

Stimulus G

Device Em

IntroductiAn AHB Mastertransactions on

Some of the sup

A 32-bit ad

32-bit, 64-b

Big or little

All transfer

All burst typ

Locked tran3ction to the AHB Transactors

MBA SystemC Transactors support the AHB bus protocols. The AMBAors, Slave Transactors, and Monitor Transactors constitute a complete AMBA environment.

ntains the following topics:

on page 31

of AHB Peripherals on page 32

Interfaces on page 40

enerator on page 42

ulator on page 42

on Transactor is used to emulate an AHB Master bus interface, which initiatesthe bus, whereas the AHB Slave Transactors respond to those transactions.

ported features of the Cadence AHB include:

dress width

it, or 128-bit data width

endian bit ordering scheme

types and sizes (up to the data bus width)es31 Product Version 5.4

sactions and sequences of transactions


May 2005

Automatic b

Automatic b

Automatic bowns it bac

Supports m

Recording database

The AHB Monitrecording for tracompliance che

The AHB Masteprotocol, indepethe Transactors

VerificatioThis section desMulti-Master/Sla

The configuratio

Single-Maspage 33

Single-Mas

Multi-Maste

Multi-Maste

The illustrations

In any of the illuAHB Slave + D

The Stimulus GEmulator indicaAHB bus. TheseIntroduction to the AHB Transactors Family

us request and bus lock assertion and release

urst rebuild after a retry or a split

urst early termination and continuation when the master looses the bus andk again later

ulti-master configurations, master hand-over operations

of overlapping bursts, address phases, and data phases in the Simvision

or Transactor is responsible for compliance checking, as well as transactionnsfers on the AHB bus. See Compliance Checks on page 152 for a list ofcks Cadence offers.

r, Slave, and Monitor Transactors handle all the AMBA-AHB interfacendently from the design, the test sequence, or coverage goals, thus making

reusable for any AMBA bus design configuration.

n of AHB Peripheralscribes examples of configurations supported by the AMBA Transactors.ve as well as Single-Master/Slave configurations are supported.

ns of the AHB bus that are included are:

ter Single-Slave AMBA AHB bus configuration shown in Figure 3-1 on

ter Multi-Slave AMBA AHB bus configuration shown in Figure 3-2 on page 34

r Single-Slave AMBA AHB bus configuration shown in Figure 3-2 on page 34

r Multi-Slave AMBA AHB bus configuration shown in Figure 3-4 on page 36

show all of the Transactor connections

strations, any block labeled AHB Master + FIFO + Stimulus Generator orevice Emulator can also be a DUV (Design Under Verification).

enerator submits transactions to the Master transactor, and the Devicetes what response the Slave transactor should give to the transaction on the components are not part of the Transactors and are user specific.32 Product Version 5.4


May 2005

Single-Maste

The Single-Masrequire any arbisignals are eachAHB Slave can

Figure 3-1 SinIntroduction to the AHB Transactors Family

r Single-Slave

ter Single-Slave configuration, shown in Figure 3-1 on page 33, does notter or multiplexer to manage the bus (provided that the Grant and Sel tied to the correct values). Any green block around the AHB Master or the

be replaced by a DUV.

gle-Master Single-Slave AMBA AHB Bus configuration33 Product Version 5.4


May 2005

Single-Maste

The Single-Masan address decdrive the correctcan be replacedbe DUVs.

Figure 3-2 SinIntroduction to the AHB Transactors Family

r Multi-Slave

ter Multi-Slave configuration, shown in Figure 3-2 on page 34, only requiresoder to select the correct slave addressed by the Master and a multiplexer toSlave signals back to the Master. Any of these blocks around Master or Slave by a DUV. The AMBA Decoder and Multiplexer managing the bus can also

gle-Master Multi-Slave AMBA AHB Bus Configuration34 Product Version 5.4


May 2005

Multi-Master

The Multi-Mastearbiter to grant tthe correct Masbe replaced by

Figure 3-3 MuIntroduction to the AHB Transactors Family

Single-Slave

r Single-Slave configuration, shown in Figure 3-2 on page 34, needs anhe bus to only one Master at a time, and a multiplexer to drive the signals ofter to the Slave. Here again, any of the block around the Master or Slave cana DUV. Arbiter or Multiplexer blocks can be DUVs as well.

lti-Master Single-Slave AMBA AHB Bus Configuration35 Product Version 5.4


May 2005

Multi-Master

The Multi-Mastemost general cacomponents ca

Figure 3-4 MuIntroduction to the AHB Transactors Family

Multi-Slave

r Multi-Slave configuration, shown in Figure 3-4 on page 36, represents these of an AMBA Bus, with all its components. Once again, any of these

n be a DUV, as detailed before in all the specific configurations.

lti-Master Multi-Slave AMBA AHB Bus Configuration36 Product Version 5.4


May 2005

VerificatioThis chapter givverification procmulti-master/muverification proc

Figure 3-5 Ver

1. Instantiate the2. Bind the Tran3. Select the apoptions).4. Bind the StimuIntroduction to the AHB Transactors Family

n Processes an overview of the different configurations that can be used during aess. The verification of a single-master/single-slave AHB configuration and alti-slave AHB configuration will be covered. Figure 3-5 on page 37 lists theess flow.

ification Process Flow

Create a C++/SystemC testbench.

In this testbench do the following: necessary AHB Master, Slave and Monitor transactors.

sactors Configuration Interfaces to the testbench through sc_ports.propriate configurations for each Transactor (if different from default

lus Generator port to the Master and the Device Emulator port to the Slave.

Create Stimulus Generator and Device Emulator files.

Create a top level HDL testbench instantiatingthe Transactor modules and the DUV.

Run the simulation using Testbuilder SC.

Compile and link the testbench(Stimulus Generator, Transactors, DUV, and so on).

Debug the DUV using Signalscan, TransactionExplorer, and the log file generated by the

simulation until all the tests go as expected.37 Product Version 5.4

Refine the Test suite until thefunctional coverage goals are met.


May 2005

Single-maste

When verifying several AHB Slabe connected toactivity.

In the example VHDL, located iinstall_dir/t

Note: There is

In the example,verifying a singl

Single-slave

When verifying several AHB Mabe connected toactivity.

In the example VHDL, located iinstall_dir/t

Note: There is

In the example verifying a singl

Multi-Master

When verifying several AHB Slabe connected toactivity.

In top_with_mfollowing directoinstall_dir/tIntroduction to the AHB Transactors Family

r Verification

a single-master AHB configuration, the test writer must instantiate one orve Transactors, within the HDL netlist. A single AHB Monitor Transactor canall the Master and Slave Transactors on the bus to cover the whole AHB bus

files top_with_monitor.v for Verilog or top_with_monitor.vhd forn the following directory.ools./tvmsc/examples run_ahb_master_slave

only one instance of a AHB Slave Transactor in the directory.

three Transactors are instantiated, a Master, a Slave, and a Monitor. Whene-master configuration, substitute the Master Transactor with the actual DUV.

Verification

a single-slave AHB configuration, the test writer must instantiate one orster Transactors, within the HDL netlist. A single AHB Monitor Transactor canall the Master and Slave Transactors on the bus to cover the whole AHB bus

files top_with_monitor.v for Verilog or top_with_monitor.vhd forn the following directory.ools./tvmsc/examples run_ahb_master_slave

only one instance of a AHB Slave Transactor in the directory.

three Transactors are instantiated, a Master, a Slave, and a Monitor. Whene-slave configuration, substitute the Slave Transactor with the actual DUV.

DUV Verification

a multi-master AHB configuration, the test writer must instantiate one orve Transactors within the HDL netlist. A single AHB Monitor Transactor canall the Master and Slave Transactors on the bus to cover the whole AHB bus

onitor.v for Verilog or top_with_monitor.vhd for VHDL, located in thery:38 Product Version 5.4

ools./tvmsc/amba20/examples/run_ahb_multi_masters_slaves


May 2005

There are two inand one instancconfiguration, s

Multi-slave D

When verifying aAHB Master Traconnected to alactivity.

In top_with_mfollowing directoinstall_dir/t

There are two inand one instancconfiguration, s

Additional in

Information abodesign, and conStarted. Informpage 42.

In the multi-masTransactors withenvironment whTransactors canthat are left on t

In the multi-slavTransactors withenvironment whTransactors canthat are left on tIntroduction to the AHB Transactors Family

stances of AHB Master Transactors, two instances of AHB Slave Transactors,e of a AHB Monitor Transactor in the directory. When verifying a multi-masterubstitute the Master Transactors with DUVs.

UV Verification

multi-slave AHB configuration, the test writer must instantiate one or severalnsactors within the HDL netlist. A single AHB Monitor Transactor can bel the Master and Slave Transactors on the bus to cover the whole AHB bus

onitor.v for Verilog or top_with_monitor.vhd for VHDL, located in thery:ools./tvmsc/amba20/examples/run_ahb_multi_masters_slaves

stances of AHB Master Transactors, two instances of AHB Slave Transactors,e of AHB Monitor Transactor in the directory. When verifying a multi-slave

ubstitute the Slave Transactors with DUVs.

formation on the verification configurations

ut creating your testbench configuration, instantiating the transactors in thenecting the transactors to the testbench is located in Chapter 2, Gettingation about the writing stimulus tests is given in Stimulus Generator on

ter verification configuration, it is not necessary to substitute all the Master DUVs. For example, your goal can be to test DUVs as masters in anere the bus is shared with other masters. In this case only some of the Masterbe substituted with DUVs and the others left as is. All the Master Transactorshe bus will then have to be driven/configured by the testbench/stimulus.

e verification configuration, it is not necessary to substitute all the Slave DUVs. For example, your goal can be to test DUVs as slaves in anere the bus is shared with other slaves. In this case, only some of the Slavebe substituted with DUVs, and the others left as is. All the Slave Transactors

he bus will then have to be configured by the testbench/stimulus.39 Product Version 5.4


May 2005

TransactoTransactor interduring simulatioprotocol operatiinto a graphicalsetup during siminterface).

Transactor C

The Configuraticomponent opecomponent are:

Error check

Endianess

The general usadescription, refeInformation on

Transactor T

Master and Slavgenerator) throutransactor. Thesfor the Master tr

Transactor P

All Transactors connectivity bethas an HDL wrait to the DUV inson page 75, AHon page 138 forIntroduction to the AHB Transactors Family

r Interfacesfaces provide mechanisms for you to interact with Transactor objects createdn. They provide for initial setup (mode of operation), allow you to generateons (transaction-level interface) and abstract the operation being executed representation (transaction recording). They also allow you to modify theulation (configuration interface) and allow for status checking (configuration

onfiguration Interface

on Interface is a C++ interface providing a mechanism to configurerations. Some examples of the operations that can be configured for a

ing (for the Monitor)(for the Master and Slave)ge of the configuration interface is to set a mode of operation. For a fullr toMaster Configuration Interface on page 47, AHB Transactor Referencepage 43 and AHB Monitor Configuration Interface on page 129.

ransaction-Level Interface

e transactors connect to higher level components (such as a stimulusgh a Transaction-Level interface. This interface doesnt exist for the Monitore interfaces are described on Master Transaction-level Interface on page 49ansactor and on for the Slave transactor.

in-Level Interface

provide a pin-level interface. This HDL interface is used to establishween the C++ layer of a Transactor and the DUV interface. Each Transactorpper that is used to instantiate the Transactor into the HDL netlist and connecttance using HDL wires. See examples in AHB Master Pin-Level InterfaceB Slave Port Interface on page 120 and AHB Monitor Pin-Level Interface

pin-level interface descriptions.40 Product Version 5.4


May 2005

Transactor T

Every TransactoTransactions areas transaction bis a pictorial repAHB Master Trpage 123 and Athe recorded tra

Transaction

Searches are ucoverage. Whensimulation databcreate searchesthe Transaction

The transactionattribute names(operations) canThe data availato the simulation

Read c

Write c

Data tr

Burst T

Respo

Addres

Note: See the TAlso see the REAfor examples ofIntroduction to the AHB Transactors Family

ransaction View

r records transactions using TestBuilder's transaction recording facilities.recorded to an SST2 waveform database and can subsequently be viewed

oxes with duration in the Signalscan Waveform Viewer. The transaction viewresentation of the operations that can be executed on the interface. Refer toansaction Recording on page 77, AHB Slave Transaction Recording onHB Monitor Transaction Recording on page 143 for detailed descriptions ofnsactions.

Searches

sed on a simulation database to quickly determine the current functional a simulation is executed, the transactions are automatically stored into thease by the Transactor. After successful completion of a simulation, you can to determine the functional coverage of the particular simulation run using

Explorer (TxE) in Signalscan.s that are recorded contain attributes. Searches may be performed using the. Their values can be checked, temporal relationships of transactions be analyzed, and operation types can be counted.

ble for a search is dependent upon the data that the Transactor is recording database. Searches might include for example:

ycle counts

ycle counts

ansfer sizes

ype

nse Type

ses accessed

ransaction Explorer User Guide for infomation on creating TxE searches.DME file located at install_dir/tools./txe/examples

TxE searches.41 Product Version 5.4


May 2005

Stimulus GA stimulus genepredefined test inject test sequeInterface on pag

Refer to Chaptestimulus genera

Device EmA Device Emulapredefined modresponse delaysthe transactionsIntroduction to the AHB Transactors Family

eneratorrator is a C++ object that implements transaction sequences according to aplan. Stimulus generators use the Transactors transaction-level interface tonces onto the DUV interface as defined in Transactor Transaction-Levele 40.

r 2, Getting Started, for more information about how to connect yourtor with the transactor(s) instantiated in the design under verification.

ulatortor is a C++ object that implements response sequences according to ael or test plan. It can behave as a basic memory (pre configured with data and), or deliver more elaborate responses following a complex model reacting to occurring on the AHB bus.42 Product Version 5.4


May 2005

AHB Tr

This chapter proreference inform

Transaction

Pin-Level In

Visual Tran

The following Tr

AHB Maste

AHB Slave

AHB Monit

An illustration ofis provided in Fthroughout this 4ansactor Reference Information

vides the reference information about each of the AMBA Transactors. Theation includes:

-level description (classes and public methods).terface description

saction Recording description

ansactors are referenced in this chapter:

r Transactor Class on page 45

Transactor on page 89

or Transactor ( ahb_monitor_t ) on page 128an AHB design, consisting of several masters, several slaves, and a monitor,

igure 4-1 on page 44. This example is used as a reference exampledocument.43 Product Version 5.4


May 2005

Figure 4-1 ExaAHB Transactor Reference Information

mple of AHB Design44 Product Version 5.4


May 2005

AHB MastThe master traninterface. It is us

See Chapter 3, protocol feature

AHB Master

The function of module (see Fig

1. An AHB Masignal-level

2. An AHB Magenerator)methods ininterface isadded on toa general d

The pull int

The push in

3. An AHB Main Master C

Figure 4-2 on pinterfaces.AHB Transactor Reference Information

er Transactor Classsactor class: ahb_master_t is used to emulate an AHB Master bused to test designs based on the AHB interface.

Introduction to the AHB Transactors Family, for a summary of the AMBAs that the AHB Master transactor supports.

Transactor Overall Structure

an AHB Master transactor is captured in the ahb_master_t SystemCure 4-2 on page 46), which offers three SystemC interfaces:ster transactor connecting to a device under verification through a interface, as described in AHB Master Pin-Level Interface on page 75.

ster transactor connecting to a higher level component (such as a stimulusthrough a transaction-level interface. This interface is based on call backs of an a SystemC sc_interface object and is called a Pull interface. Thisdescribed in Master Transaction-level Interface on page 49. A layer can bep of a Pull interface making it a Push interface. Chapter C, Glossary givesefinition of the Pull and Push interfaces.

erface is described in Pull Interface on page 50.

terface is described in Push Interface on page 52.

ster configured dynamically through a configuration interface, as describedonfiguration Interface on page 47.

age 46, shows a class diagram of the master transactor and its three45 Product Version 5.4


May 2005

Figure 4-2 AH

Connecting a

A master transadeclares a virtuInterface on pa

The sc_port cnew transaction

When the Pull incalled by the ma

A FIFO queue ismethods. FigureAHB Transactor Reference Information

B Master Transactor Structure

Master Transactor to a Stimulus Generator

ctor is connected to a stimulus generator through a SystemC sc_port thatal interface called uvm_pull_if_t (see Master Transaction-levelge 49).

an be seen as the transaction-level port used by a master transactor to pull a from the stimulus generator when it is ready to accept one.

terface is used alone the stimulus generator is implemented as methodsster transactor. The Push interface is layered on top of the Pull interface.

placed between the stimulus generator and the master transactors callback4-3 on page 57, illustrates such configuration.46 Product Version 5.4


May 2005

Figure 4-3 Tes

Master Confi

The AHB Mastethat is not protoand so on). The

Example Class

The following co

template rol_if_tic sc_interface {

_t() : debug(0), enable(1) {}end_control(const CONTROL_T &) = 0;//protocol specific configurationnable_on() {enable = 1;} //enables the transactor (default)nable_off() {enable = 0;} //disable the transactorebug_on() { debug = 1;}//displays the debug informationebug_off() { debug = 0;}//hides the the debug info (default)et_debug() { return debug;}et_enable() { return enable;}

T template structure of this class is protocol-specific. A common structure47 Product Version 5.4

figuration_t is used to configure all the AHB Transactors. Table 4-1 on the attributes of this structure used to configure an AHB Master Transactor.


May 2005

Table 4-1 AttribMaster Transac

Note: The datashown in the fol

//Data Bus widconst int DATA

As presented inahb_w_data asc_in > and sc_out.


May 2005

The consequenfor each possibl

Example of Us

If you want to comust contain aahb_configur

Example

class push_sti public:

sc_port master_control_port;//Master configuration port

;timulus_generator_t)ontrol_port(master_control_port),..,..

HREAD(my_test);

ulus_generator_t::my_test() {e transactors before starting the stimulus.ion_t transactors_config;nfig.transaction_record = false;nfig.big_endian = true;_port->send_control(transactors_config);

action-level Interface

es of the master transaction-level interface are:

s are represented as objects of a class called ahb_arg_handle_t. These49 Product Version 5.4

created by a stimulus generator and contain all the conguration information


May 2005

that a stimudocument, master tran

A virtual puclass ahb_method is dblocking casimulation

If a stimulusability to wagrant, resethe transaca previousl

Pull Interface

As specified in tof the following

1. A SystemCtemplate class uvm_pull_if_t : virtual public sc_interface {

pull() = 0;

above code shows T being returned by value. It is expected that the templateill be a shared pointer to a transaction object.ction interface classes are template classes. The pull method returns anpe T in the above code). This class type of the returned object will change forype of transactor. For AHB Master transactors, the template type ishandle_t, which is dened as:b_arg_handle_t scv_shared_ptr;

ointer can be used exactly like a pointer (by using the -> operator to accesstion attributes and methods) but is safer because it frees the test writer fromof memory management, especially when the transaction is used by severale the scv_shared_ptr class description in the TestBuilder-SystemC manual).tion of a SystemC port in the transactor as follows:50 Product Version 5.4

master_t :


May 2005

public uvmpublic:sc_portset

/**....ConArgument C

return arg

}

5. The declarawords, instclass top_{public:ahb_stimul}AHB Transactor Reference Information

_control_if, public ahb_master_port_if {

m_pull_if_t,1> puller;

nnects an AHB master transactor to a stimulus generator through a-level interface.The port has a template type that is the name of the interfaceis case the template type is: uvm_pull_if_t. That type in turn has its ownrameter which specifies the template class handled by this generator, which_handle_t. The second argument in the ports template is the number ofched to the port. A value of 0 means any number of objects.on of a stimulus generator class which inherits the SystemC interfaces defined in item 1) This class contains the callback function (pull()),irtual function in the interface class.stimulus_generator_t : public uvm_pull_if_t

us_generator_t() {}lus_generator_t() {}b_arg_handle_t pull();

on of the interface member function, where stimulus transactions are created

g_handle_t ahb_stimulus_generator_t::pull()

g_handle_t arg_p = new ahb_arg_t;//create new transaction_address(0x100);figure the transaction using the methods defined in Transactionlass on page 54)...**/_p;

tion of the interface class, usually in the same module that declares (in otherantiates) the transactor, as follows:testbench_t : public sc_module

us_generator_t stim_gen;51 Product Version 5.4


May 2005

Push Interfac

The Push interfstimulus generatransactor calls template _pull_fifo_tim_channel,ush_if_t,ull_if_t

push(const T &arg) {n_value = fifo.empty();arg);.notify();urn_value;

ush_wait(const T &arg) {arg);.notify();event);

() { be a scv_shared_ptr or scv_smart_ptr.o queue is empty, return a dummy transaction which is null by defaultmpty()) {transaction_h;//null scv_shared_ptrummy_transaction_h;

ifo.front();();nt.notify();arg;52 Product Version 5.4


May 2005

private: sc_event pus

};

If the transactiotransactor. If theand sent to the

The following lis//non-blockingvoid push(ahb_

//blocking pusvoid push_wait

Since these funthey are bound

//UVM Push Inttemplate set_add/**..configurepage 54**/master_port->p

ahb_arg_handleAHB Transactor Reference Information

h_event, pull_event;

n queue is empty, the pull function returns a null shared pointer to the master queue is not empty, then the last transaction put into the queue is poppedmaster transactor.

ting shows what the Push interface looks like to the user of the transactor: push, returns after 0-simulation timearg_handle_t &arg);

h, returns when a transaction is pulled by the transactor(ahb_arg_handle_t &arg);

ctions are members of a class that inherits from a SystemC interface class,to a port and are called through the port pointer, which is as follows:

erface Declarationname TX_T>_if_t : virtual public sc_interface {

ush(ahb_arg_handle_t &arg)= 0;ush_wait(ahb_arg_handle_t &arg)= 0;

ush stimulus generatormulus_generator_t : public sc_module {t master_tx_port;timulus_generator_t) {est);

;

ulus_generator_t::my_test() {_t tx1_h = new ahb_arg_t;ress(0x100); a transaction as specified in Transaction Argument Class on53 Product Version 5.4

ush(tx_h);_t tx2_h = new ahb_arg_t;


May 2005

/**..configuremaster_port->p

}

Transaction Ar

The ahb_arg_uvm_pull_if_configuring tran

By way of tpull interfac

By way of thinterface (P

ahb_arg_handmethods are de

The way you crefollowing line:ahb_arg_handle

Once the transaexample above)example, from tlast transfer of tSee Creating aof the transactio

Table 4-2 on pamethods and ata detailed descr

Table 4-2 Brief

Attributes and

void wait_fAHB Transactor Reference Information

another transaction**/ush_wait(tx2_h);

gument Class

handle_t class is the return type of the pull method defined in thet interface class. The stimulus generator is responsible for creating and

sactions before submitting them to the master transactor in the follwing ways:

he return value of the pull method if the stimulus generator implements ae (Pull Interface on page 50).e argument value of the push method if the stimulus generator uses a pushush Interface on page 52).le_t is a shared pointer on a ahb_arg_t object, whose attributes andfined in this section.

ate a new transaction and store it in a shared pointer handle is shown in the

_t transaction_h = new ahb_arg_t;

ction is created, the associated transaction handle (transaction_h in the can be used to keep track of the transaction during its entire duration. forhe moment it is queued in the master transactor until the completion of thehe burst or the burst cancellation due to a bus reset or an ERROR response.nd using transaction handles on page 75, for information on the propertiesn handles.

ge 54, gives a short description of the most important transaction publictributes. Please, refer to Table 4-3 on page 57, and Table 4-4 on page 59, foription and usage explanations of all the methods and attributes.

description of the ahb_arg_t public methods and attributes

Methods Brief Description

or_start_event() Wait until the transaction54 Product Version 5.4

starts.


May 2005

void wait_f

bool wait_f

boolwait_for_lo

data_array

expected_da

beat_delay_

check_mask_

void set_adstart_addr)

voidset_write_tflag)

void set_nunull_arg =

void

set_burst_t

sc_uint

void

set_transfesize)

void

set_prot(sc_uint

Attributes andAHB Transactor Reference Information

or_finish_event() Wait until the transactionfinishes.

or_retry_event() Wait for a retry response.

ss_of_grant_event()Wait for a loss of bus grant.

Data storage array.

ta_array Expected data storage array.

array BUSY cycles array.

array Check bit masks array

dress(sc_uint;

Transaction address

ransaction(boolRead/Write

ll_transaction(boolfalse)

Null Transaction.

ype(burst)

Burst Type

r_size(sc_uintTransfer size

prot)

Protection Mode

Methods Brief Description55 Product Version 5.4


May 2005

void

set_start_d

(unsigned i

void

set_lock( b

void

set_continuflag)

void set_bu

void set_ch

set_check_mflag)

void set_n

(unsigned i

voidset_hold_reer( bool fl

voidset_hold_lofer( bool f

void releas

void releas

Attributes andAHB Transactor Reference Information

elay

nt num)

IDLE cycles inserted beforestarting the transaction.

ool )Transfer lock.

e_after_error( boolContinue after an ERROR.

rst_length() number of beats in an INCRburst.

eck_data(bool flag) Automatic data checking.

asked_data(bool Automatic data checkingwith bit masks.

um_Idle_after_retry

nt )IDLE cycles before retrying.

q_after_last_transfag = true)

Hold bus request after thelast transfer.

ck_after_last_translag = true)

Hold bus lock after the lasttransfer.

e_req() Low level action: release theHREQ pin.

e_lock() Low level action: release theHLOCK pin.



May 2005

The attributes

Table 4-3 on paThese arrays usand reference gpre-defining the

Table 4-3 ahb_

sc_uint

r_data_array(..)

Read a data transfer valuefrom data_array (refer toTable 4-4 on page 59,fordetails on the parameters ofthis method)

er_data_array(..)Write a data transfer value(refer to Table 4-4 onpage 59,for details on theparameters of this method)

urst(..) Configure a burst transaction(refer to Table 4-4 onpage 59,for details on theparameters of this method)

lise() initialize the transactionobject.

Description

array

int >

This array contains the data to be written into the slavememory space. This array is also used to store the read data.Each location is indexed by the byte address and holds abyte of data.The default byte value is 0.



May 2005

scv_sparse_

< int, sc_uexpected_da

scv_sparse_

< int, int beat_delay_

ArrayAHB Transactor Reference Information

array

int >ta_array

This array contains the data to be checked by the mastertransactor against the actual data read on the bus during aRead transaction. This checking is done automatically if theset_check_data() method has been called prior tosubmitting the transaction.

Each location in the sparse array is sized to 8 bits andindexed by the byte address exactly like the data_array.The default byte value for this array is 0.

array

>array

This array contains a specified number of BUSY cycles toinsert before any SEQuential transfer in a burst. Eachlocation of this array is indexed with the transfer (or beat) toassign a busy delay. The index starts with 1, whichcorresponds to the first beat.No BUSY cycles can be inserted before a NONSEQuentialtransfer, therefore beatDelayArray[1] will be ignored. Inany other transfer in the burst, a specified number of BUSYcycles can be inserted.Example:beat_delay_array[2] =1;//1 BUSY cycle will be inserted before the 2nd Transfer

beat_delay_array[4]=3;//3 BUSY cycles will be inserted before the 4thtransfer.

The default integer value stored in all locations is 0.

Description58 Product Version 5.4


May 2005

The ahb_arg

Table 4-4 on pa

Table 4-4 Tabl

scv_sparse_

< int, sc_u

check_mask_

Method

void set_adstart_addr)

ArrayAHB Transactor Reference Information

_t Public Methods

ge 59 describes the ahb_arg_t public methods.

e of ahb_arg_t Public Methods

array

int >

array

This array contains a bit mask used to compare the expecteddata with the actual data during a read transaction. Eachlocation of this array is indexed by a byte address and holds abyte of data.Each bit within a byte specifies if the corresponding bit ofdata must be checked against the expected data.1: Compare0: Do not care.The default byte value stored in all locations is 0xff (All thebits are compared).

Description

dress(sc_uint;

Sets the start (byte) address of the burst orthe single transfer.It is the responsability of the user to providean address that is aligned with the transfersize (byte, half-word, word, 2-words).An unaligned address will be automaticallymasked internally in the master transactorand correctly aligned. An internal ErrorException will be thrown and inform theuser if such correction occurs.A corresponding get_address()method returns the start address(sc_uint type)

Description59 Product Version 5.4


May 2005

void set_wrflag)

void

set_burst_t

sc_uint AHB Transactor Reference Information

ite_transaction(bool Sets the transaction direction: Write (flag =true) or Read (flag = false).The default value is true (Write)

ype(burst)

This sets the burst type. Here are the validvalues for this argument:0 - SINGLE

1 - INCR (Unspecified Length)(the user must specify a value usingset_burst_length(int))2 - WRAP4

3 -INCR4

4 - WRAP8

5 - INCR8

6 - WRAP16

7 - INCR16

Instead of using integer values, thefollowing predefined constants can be usedin the testbench:AHB_BURST_SINGLE

AHB_BURST_INCR

AHB_BURST_WRAP4

AHB_BURST_INCR4

AHB_BURST_WRAP8

AHB_BURST_INCR8

AHB_BURST_WRAP16

AHB_BURST_INCR16

The default burst type is SINGLE ( 0 ).A corresponding get_burst_type()method returns the Burst type(sc_uint value).60 Product Version 5.4


May 2005

void

set_transfesize)

void

set_prot(sc_uint

void

set_start_d

(unsigned iAHB Transactor Reference Information

r_size(sc_uintSets the transfer size for the burst. The validvalues for this argument:0 - BYTE (8 bits)1 - HALF-WORD (16 bits)2 - WORD (32 bits)3 - 2 WORDS (64 bits).Instead of using integer values, thefollowing predefined constants can be usedin the testbench:const unsigned int AHB_SIZE_BYTE = 0;const unsigned int AHB_SIZE_HALF = 1;const unsigned int AHB_SIZE_WORD = 2;const unsigned int AHB_SIZE_2WORD = 3;

A corresponding get_transfer_size()method returns the Burst type(sc_uint value)

prot)

Sets the value to drive on the HPROT pins ofthe transactor for the duration of the burst.The default value is 0.A corresponding get_prot() methodreturns the protection type (sc_uintvalue)

elay

nt num)

Sets a number of IDLE cycles to beinserted before the NONSEQ transfer starts(First transfer of the burst). The defaultnumber is 0. More details are given aboutthis feature is detailed in Start DelaySpecifications on page 85.a corresponding get_start_delay()method returns the start delay value (int)61 Product Version 5.4


May 2005

void

set_lock( b

void

set_continuflag)

void set_buAHB Transactor Reference Information

ool )Indicates to the transactor that thecorresponding transaction must be locked.true = locked, false = not locked, defaultvalue = false.HLOCK will be automatically asserted andreleased by the transactor.The way HLOCK is asserted and released bythe master transactor are described inTransfer Lock on page 85.A corresponding get_lock() methodreturns the Lock value (bool)

e_after_error( boolSets a flag that tells the master transactorwhether to complete the current burst or toterminate the burst when the Slave issuesan ERROR response.0 - Terminate the burst and cancel thefollowing transfers default1 - Complete the remaining transfers.A correspondingget_continue_after_error() methodreturns the value of this boolean flag.

rst_length() Specifies burst length for INCR bursts (ofunspecified length) Valid values are anyvalues from 1 and higher.This method should be used only when theburst type is INCR (undetermined length).If the set_burst_type method was usedwith any other burst type of specified lengthpassed as an argument (for example,INCR4 ), the length will be automaticallyset.A corresponding get_burst_length()method returns the value of the burstlength.62 Product Version 5.4


May 2005

void set_ch

set_check_mflag)AHB Transactor Reference Information

eck_data(bool flag) Sets a flag that when set to one (1) willcompare supplied data inexpectedDataArray against the actualdata read during a read transaction.An internal scv error exceptions(AHB_DATA_CHECK_EXCEPTION) will bethrown during the transaction if data doesnot match expectations stored in theexpectedDataArray.

The default state of this flag is false.A corresponding get_check_data()method returns the value of this flag (bool)

asked_data(bool Sets a flag that when set to one (1) willcompare supplied data inexpectedDataArray against the actualdata read during a read transaction. Duringthe comparison, each byte of data will bemasked with a corresponding byte suppliedin the check_mask_array.This masked comparison will be do

Documents

amba_tbsc