Upload
sorabh-dung
View
217
Download
0
Tags:
Embed Size (px)
DESCRIPTION
sfefsf eff
Citation preview
eInfochips Corporate Overview
IMPLEMENTATION OF AHB PROTOCOL USING VERILOGPresented By: Nirav Desai(13014061003)Guided By: Rajesh Navandare-Infochips Institute of Training Research and Academics Limited
16/12/2014TABLE OF CONTENTAdvanced High Performance BusFeatures of AHB BUSAMBA 2.0Components in AHB AHB SignalsRequest / Grant ProtocolPipelined TransactionsRTL Diagrams of all modulesSimulation Result of all modulesAdvantagesReferences6/12/20142Implementation of AHB Protocol using verilog6/12/20142Advanced High Performance BusAHB is a new generation of AMBA bus which is intended to address the requirements of high-performance synthesizable designs.It is a high-performance system bus that supports multiple bus masters and provides high-bandwidth operation.
6/12/20143Implementation of AHB Protocol using verilogFeatures of AHB BUS
AMBA AHB implements the features required for high-performance, high clock frequency systems Including: Burst transfers Split transactions Single-cycle bus master handover Single-clock edge operation Wider data bus configurations (64/128 bits).
6/12/20144Implementation of AHB Protocol using verilogAMBA 2.0
6/12/20145Implementation of AHB Protocol using verilogComponents in AHB MasterAHB master is able to initiate read and write operations by providing an address and control information. Only one bus master is allowed to actively use the bus at any one time.(max. 16)SlaveAHB slave responds to a read or write operation within a given address-space range. The bus slave signals back to the active master the success, failure or waiting of the data transfer.
6/12/20146Implementation of AHB Protocol using verilogComponents in AHB ArbiterAHB arbiter ensures that only one bus master at a time is allowed to initiate data transfers. DecoderAHB decoder is used to decode the address of each transfer and provide a select signal for the slave that is involved in the transfer. A single centralized decoder is required in all AHB implementations.
6/12/20147Implementation of AHB Protocol using verilogAHB Response SignalsResponse signalsHREADYTransfer done, ready for next transferHRESP[1:0]OKAY transfer completeERROR transfer failure(ex: write ROM)RETRY higher priority master can access busSPLIT other master can access bus6/12/20148Implementation of AHB Protocol using verilogAHB Arbitration SignalsArbitration signalsHGRANTxSelect active bus masterHMASTER[3:0]Multiplex signals that sent from master to slaveHMASTLOCKLocked sequence6/12/20149Implementation of AHB Protocol using verilogMaster Signals
6/12/201410Implementation of AHB Protocol using verilogArbiters Signals
6/12/201411Implementation of AHB Protocol using verilogSlave Signals
6/12/201412Implementation of AHB Protocol using verilogRequest / Grant Protocol
RequestCPU #1CPU #2IP Block #1IP Block #1IP Block #2IP Block #3IP Block #46/12/201413Implementation of AHB Protocol using verilogRequest / Grant Protocol
RequestGrantCPU #1CPU #2IP Block #1IP Block #1IP Block #2IP Block #3IP Block #46/12/201414Implementation of AHB Protocol using verilogRequest / Grant Protocol
RequestGrantTransactionCPU #1CPU #2IP Block #1IP Block #1IP Block #2IP Block #3IP Block #46/12/201415Implementation of AHB Protocol using verilogRequest / Grant Protocol
Before a transaction a master makes a request to the central arbiter 6/12/201416Implementation of AHB Protocol using verilogRequest / Grant Protocol
Before a transaction a master makes a request to the central arbiter Eventually the request is granted 6/12/201417Implementation of AHB Protocol using verilogRequest / Grant Protocol
Before a transaction a master makes a request to the central arbiter Eventually the request is granted Then the transaction proceeds 6/12/201418Implementation of AHB Protocol using verilogRequest / Grant Protocol
Before a transaction a master makes a request to the central arbiter Eventually the request is granted Then the transaction proceeds Performance Impact 6/12/201419Implementation of AHB Protocol using verilogPipelined TransactionsTo help improve bus efficiency the transactions on the bus can be pipelined
This is really a simple implementation of multiple outstanding transactions
The address for one transaction can be presented before the data from the previous transaction has been completed
6/12/201420Implementation of AHB Protocol using verilogPipelined Transactions
6/12/201421Implementation of AHB Protocol using verilogPipelined Transactions
Transaction A Starts6/12/201422Implementation of AHB Protocol using verilogPipelined Transactions
Transaction A StartsTransaction B Starts6/12/201423Implementation of AHB Protocol using verilogPipelined Transactions
Transaction A StartsTransaction B StartsTransaction A Completes6/12/201424Implementation of AHB Protocol using verilogConnections of AHB masters6/12/2014Implementation of AHB Protocol using verilog25
Connection of AHB slaves6/12/2014Implementation of AHB Protocol using verilog26
Arbiter RTL6/12/201427
Implementation of AHB Protocol using verilogArbiter Simulation Result
6/12/201428Implementation of AHB Protocol using verilogDecoder RTL6/12/2014Implementation of AHB Protocol using verilog29
Decoder Simulation Result6/12/2014Implementation of AHB Protocol using verilog30
MUX Slave To Master RTL6/12/2014Implementation of AHB Protocol using verilog31
MUX Slave To Master Simulation Result6/12/2014Implementation of AHB Protocol using verilog32
MUX Master to Slave RTL6/12/2014Implementation of AHB Protocol using verilog33
MUX Master to Slave Simulation Result6/12/2014Implementation of AHB Protocol using verilog34
MUX peripherals to bridge RTL6/12/2014Implementation of AHB Protocol using verilog35
MUX peripherals to bridge Simulation Result6/12/2014Implementation of AHB Protocol using verilog36
AdvantagesRelatively easy to add new blocksStill has the familiar bus structureLow hardware costBus arbitration solves many ordering problems
6/12/201437Implementation of AHB Protocol using verilog38DisadvantagesBusses that require arbitration:must route signals to the arbitration logic and backmust find a fair way to share the busslaves are not always available => backpressuredifficult to provide performance guarantees...
Still potentially a bandwidth bottleneck
Still doesnt scale well when blocks are added
Multiple outstanding transactions not handled well - no ordering information
References[1] AMBA Specification, Rev. May, 2.0, 1999. [2] High-Speed Single-Port SRAM (HS-SRAM-SP) Generator User Manual, Artisan Components Inc., Release 4.0, Aug. 2000.[3] Debussy User Guide and Tutorial, NOVAS Software Inc., Sept. 2002.[4] Compatibility of Network SRAM and ZBT SRAM, Mitsubishi LSIs Application Note (AP-S001E), Rev. C, Renesas Tech. Corp., Sept. 2002.[5] DesignWare AHB Verification IP Databook, ver. 2.0a, Synopsys Inc., July 2002.[6] VMT User Manual, Release 2.0a, Synopsys Inc., July 2002.[7] Vera User Guide, ver. 5.1, Synopsys Inc., June 2002.[8] SolidAMBA, Averant Inc., Dec. 2003.6/12/201439Implementation of AHB Protocol using verilogThank you
6/12/201440Implementation of AHB Protocol using verilog