Alpha Emission Qualification of a 361pin Flip-Chip Package utilizing361pin Flip Chip Package utilizing

System Soft Error Testing

Helmut PuchnerCypress Semiconductor

Alpha ParticlesAll terrestrial materials contain trace amounts of radioactive atoms For example, 210Po, 238U, and 232Th, at a few parts per trillion

These atoms sporadically emit Alpha particles as they disintegrate into more stable elementsdisintegrate into more stable elementsAlpha particles are Helium nuclei with a double-positive charge, and are directly

ionizing, i.e., their motion in Silicon creates an electron-hole charge track; this charge can disrupt a circuit and cause soft errors

Radioactive contaminants in packaging materials need to be controlled to lower the Alpha emission rateUsage of Ultra Low Alpha (ULA) mold compounds and materialsCertificate of Compliance (CoC) and tight supply chain controlTypical Alpha emission rates for semiconductor materials are shown in the table to Typical Alpha Emission Rates:

the right

Alpha particles can be partially screened from reaching sensitive circuitsAdditional passivation layers (10μm polyimide 50% reduction)

Material α/cm2-hr

Processed Wafers 0.0009

Cu Metal (thick) 0.0019

Al Metal (thick) 0.0014Additional passivation layers (10μm polyimide 50% reduction)A dummy metal layer can also act as an Alpha shield

Materials in Packages that are close enough to SRAM CellWire bond packages: mold compound

Al Metal (thick) 0.0014

Mold Compound 0.024 - <0.002

Underfill 0.002 – 0.0009

Pb-solders 7.200 - <0.002

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Wire bond packages: mold compoundFlip chip packages: solder bump, underfill, UBM, presolder

Alpha Particle TestingA tester with an open-top DUT setup and a calibrated 232Th foil positioned at a predefined distance (<2mm) from the chip surface is used

Test flowsStatic – Write data pattern (e.g., checkerboard) => Alpha exposure time x => Read-verify => log errorsDynamic – During exposure time x, enter into in infinite Write-Read loop and log errors as they occurBitmapping – collect hundreds of individual, isolated events for bitmap studiesSEL – high-temperature and high-flux, static testing attempts to overwhelm the memory and cause latchup

SER/SEL FIT Rate CalculationFIT rates are scaled to the flux of the dominant alpha emitter in the packaging materials (e.g., the mold compound for wire-bond

packages)The Alpha emission rate for Ultra-Low Alpha (ULA) mold compound is ΦPKG=0.001 α/cm2·hrp p ( ) p PKGSER is expressed on a per-Megabit basis, and SEL on a per-Device basis

SER:)(][

10)(#]1[9

Mbd ithrerrors

MbFIT

ΦΦ⋅

=

SEL:

)(][ PKGFOILMbdensityMb ΦΦ⋅

)(10)(#]1[

9

PKGFOIL

hrLUeventsDev

FITΦΦ⋅

=

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This Method works well for Wirebond Packages

Flip-Chip Package

Typical Flip Chip BGA Package

Subcon provided Alpha Emission Rates:Underfill: 1 alpha/khrSolder Bump: 2 alpha/khr

Additional FC Materials: UBM: ?, Pre-solder:?

Alpha Testing from front side impossible!!Alpha Testing from back side requires Alpha Emission Rates for ALL materials close to SRAM cells!!

System SER (Life Testing) in “Zero-Neutron Environment” can do the job!!System SER (Life Testing) in Zero Neutron Environment can do the job!!

Package independent Alpha particle upset requirements:

No Multi Bit Upsets from single events

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No Multi Bit Upsets from single eventsNo Multi Bit Upsets from multiple events

FC MBUs from Single EventCan single Alpha Particles trigger Multi Bit Upsets (MBUs)?Only gracing angle particles hitting in the same row can cause MBUsSRAM Array with 16-cell Bit Interleaving:

Al h ti l f ld b ill t MBU t f i l ti lAlpha particles from solder bumps will not cause a MBU event from a single particle since the backend stack will screen the shallow angle Alpha particle hits

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FC MBUs from Multiple EventsSRAM’s accumulate soft errors in data retention mode (Accumulation Effect)Birthday statistic can be used to calculate probability of MBU eventMBU probability depends on:

Architecture (# of addresses) 1.E+04Prob Single ECC Error

Intrinsic failure rate of SRAM cellData bus width – x8,x16

Example: 16Mbit SRAM1 E+00

1.E+01

1.E+02

1.E+03

ors

(MB

U)

Prob. Single ECC ErrorTheoretical ECC Error RateAlpha_Induced MBUs LET = 2.8LET = 5LET = 8.6LET = 16

1.E-03

1.E-02

1.E-01

1.E+00co

rrec

tabl

e Er

ro LET = 28.2LET = 38LET = 120

ULA LA1.E-06

1.E-05

1.E-04

1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06

# U

nc

StdULA LA

MBU failure rate of SRAM in data retention mode depends strongly on Alpha emission of the package material:ULA (<1 α/khr): MBU = 0.08 FIT/MbStd (<100 α/khr): MBU = 800 FIT/Mb

# Raw Array Errors (SBU)

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ULA packaging materials required in FC packages to suppress MBUs

EDAC Protected SRAM

Optimized EDAC (32+6bits internal data structure)Allows for Single Error Correction (SEC)Dedicated Error output (ERR) – ECC notifies user that a bit correction has been performed

Block Diagram

Fast SRAM with ECC

I tECCSRAM Arrayp

SEC will correct accumulated SBU events in SRAM arrayErrors stay in SRAM array until SRAM is re-written (scrubbed)Accumulated MBUs cannot be correctedHow long will it take to accumulate 1000 SBUs in SRAM array:

x18-23

Address

I/O MuxAddressDecoder

Sense A

ECC D d

Input Buffer

ECC Encoder

y

ERR

Data

How long will it take to accumulate 1000 SBUs in SRAM array:ULA (1 α/khr) = 11000 yrs @ NYCStd (100 α/khr) = 235 yrs @ NYC

Potential Issue only for Avionics applications CE OE WE BHE BLE

Amps Decoder

Control Logic

SRAM Array

ULA packaging materials required to suppress MBUs 1.E+01

1.E+02

1.E+03

1.E+04

s (M

BU

)

MBUs

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

Unc

orre

ctab

le E

rror

sECC

Eliminates Soft Errors

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1.E-06

1.E-05

1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06

#

# Raw Array Errors (SBU)

System SER TestingHundreds of devices are mounted in a system (up to 30Gb of SRAM) and written

and read continuously every four minutesExtraction of Alpha and Neutron SER through measurements at different altitudes

and environments

Cypress-preferred locationsHigh Neutron flux environment: Mauna Kea – Hawaii, 9.2x acceleration over NYCZero Neutron flux environment: Soudan – Minnesota, 10-5 n/cm2·hr, used for true Alpha SER

measurements (e.g., for flip chip package qualification)

Failure log example from Mauna Kea (305† events over 3 months)Rack Mount System w/ UPS

and Network

High Neutron Environment Zero-Neutron Environment

Soudan, Minnesota (-2,360ft)Mauna Kea (+14,700ft)

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System SER TesterCustom SSER Tester:

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361 FC w/ 144M QDR SRAM SSER164pc of 144M QDR SRAMs installed in Jan 2014 @ Soudan, MN mine (24.7 Gb)17 SBU events, 3 MCU events till end of June detected (continue for another 6 months)FIT Rate = 279 FIT/Mb equivalent to 1.07 α/khr

800

900

35

40Events (SBU)

Events MCU

Total Events (SBU+MCU)

500

600

700

20

25

30

ate

[FIT

/Mb]

of E

vent

s

FIT / Mbit (SBU+MCU)

200

300

400

5

10

15

SER

Ra

Num

ber

0

100

0

5

0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150

Mbit Hrs (x106)

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361pin Flip Chip meets ULA criterion

ConclusionsSystem SER is the only reliable method to validate alpha emission of flip chip packages:

Advantages:AccurateValidates whole package at once

Disadvantages:Disadvantages:Long measurement time (1yr)Expensive (Power, Support)

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