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26/11 2002
Jens Jørgen Gaardhøje, NBI, [email protected] 1
ALICE Si-FMD,T0,V0Si-FMD
Update on Status Conceptual design of FEE and BEE-DAQ chain Timetable Heat dissipation
26/11 2002
Jens Jørgen Gaardhøje, NBI, [email protected] 2
ALICE Si-FMD,T0,V0Hybrid with Viking PA chips
VA preamp+shaper: 128 ch
Connector(s) forpower, control, read-out
Other components
Other components
Hybrid cards contain: FE–Preampl. chips Bias voltages distribution Gate/strobe distribution Read-out clock distribution Detector bias connection
Si detector
26/11 2002
Jens Jørgen Gaardhøje, NBI, [email protected] 3
ALICE Si-FMD,T0,V0FMD RO strategy
FMD Segment
ON DETECTOR
Digital serial links
(15-20 m)
Digital serial links
(15-20 m)
Trigger & Slow Ctrl
Trigger & Slow Ctrl
IN CAVERN INCOUNTING
ROOM
Slow control& Trigger
Slow control& Trigger
Detector Data Link(50-60 m)
Detector Data Link(50-60 m)
FMD RCU
VA
1 ring: 10/20 segments 2 Digitizers 1 RCU per side 1 DDL per sideFull FMD: 70 segments 10 Digitizers 2 RCU’s 2 DDL’s
FMD Read-Out and Control Electronics
Analog serial link(10 MHz) 0.5 m
Analog serial link(10 MHz) 0.5 m
VA read-outcontrol
VA read-outcontrol
Loc
al
Con
trol
ler
DD
L - IN
TSlow
-Control
Interface
TTC-RX
BOARDCTRL
Datareceiver
FMD Digitizer
ALTROALTRO
ALTROALTRO
ALTROALTRO
CTRLCTRL
Read-out CTRLRead-out CTRL
CTRLCTRL
CTRLCTRL
BSN, 21 Nov 2002
26/11 2002
Jens Jørgen Gaardhøje, NBI, [email protected] 4
ALICE Si-FMD,T0,V0FMD FEE test setup
BSN, 21 Nov 2002
FMD FEE test
CTRLCTRL
PowerBiasesPowerBiases
Clock10 MHzClock10 MHz
Trig in
ALTRO tester
ALTROALTRO
CTRLCTRL
Ext clock
Ext trigger
Sidetector
VA
Labview
DAQ
26/11 2002
Jens Jørgen Gaardhøje, NBI, [email protected] 5
ALICE Si-FMD,T0,V0Si-FMD timetable (1)
A FRONT END (FE) READ OUT ELECTRONICS Completed
1 Demonstrate functionality of conceptual layout of FEE(Viking PA chip, control system, interface to ALTRO test board)
April 1 2003
2 Final choice of VA pre-ampl. chip. RO test June 1, 2003
3 Test FEE system coupled to sample Si detector. Source and electron beam tests.
June 1, 2003
4 Design, construction and test of prototype FMD digitizer card (FMDD), RO test with ’mini’ FMD-RCU
October 1, 2003
5 Full Si detector element + electronics chain RO with realistic RCU and DDL link to DAQ.
June 1 , 2004
B MECHANICS AND INTEGRATION Completed
1 Full scale model manufactured (Si1) February 1, 2003
2 Cabling and Cooling issues resolved April 1, 2003
3 Full integration sequence decided June 1, 2003
26/11 2002
Jens Jørgen Gaardhøje, NBI, [email protected] 6
ALICE Si-FMD,T0,V0Si-FMD timetable (2)
C. SILICON DETECTOR Completed by
1 Complete market survey February 1, 2003
2 Define final specs March 1, 2003
3 Place order for prototype with industry April 1, 2003
4 Delivery Si-wafer prototype June 1, 2003
5 Start production of Si-hybrid FEE card June 1, 2003
6 Delivery prototype hybrid August 1, 2003
7 Si prototype test with FEE and BEE test RO setup December 1, 2003
8 Place final order for Si with industry April1, 2004
26/11 2002
Jens Jørgen Gaardhøje, NBI, [email protected] 7
ALICE Si-FMD,T0,V0FMD Material constants (1)
Material type and thickness of one Si detector ring:
Layer Material Thickness
Heat conductivi
ty(W/m·K)
Density(kg/m3)
Specific heat
(J/kgK)
Silicon detector
Si 0.3 mm 84 2330 678
Hybrid Al2O3 0.5 mm 35 3970 880
FE electronics
air + chips10 mm
(mostly air)
SupportCarbon fibre or aluminium honeycomb
20.5 mm C or Al
+ 10 mm air
C: 24
Al: 222
C: 2200
Al: 2700
C: 691
Al: 900
26/11 2002
Jens Jørgen Gaardhøje, NBI, [email protected] 8
ALICE Si-FMD,T0,V0FMD Material constants (2)
Material type and thickness of one Si detector ring:
Layer Material ThicknessInteraction
lengthRadiation
length
Silicon detector
Si 0.3 mm 0.6 · 10-3 0.3 · 10-2
Hybrid Al2O3 0.5 mm 2.0 · 10-3 1.0 · 10-2
FE electronics
air + chips10 mm
(mostly air)
SupportCarbon fibre or aluminium honeycomb
20.5 mm C or Al
+ 10 mm air
C: 2.6 · 10-3
Al: 2.5 · 10-3
C: 0.5 · 10-2 Al: 1.1 · 10-2
Total thickness of one Si ring: C: 5.2 · 10-3 I 1.8 · 10-2 X0 Al: 5.1 · 10-3 I 2.4 · 10-2 X0
26/11 2002
Jens Jørgen Gaardhøje, NBI, [email protected] 9
ALICE Si-FMD,T0,V0Heat dissipation. Si-FMD
Heat dissipated by FE electronics of one Si detector ring:
VA1TA preamp chip (128 channels): 150 mW 80 chips = 12 W / ring
For simulation: assume uniform distribution on hybrid surface (towards support plate)
Read-out electronics and power distribution: 5 W / ring
For simulation: assume concentrated in 2 locations near outer radius
=> Total estimated heat release pr . side < 30-40 W
26/11 2002
Jens Jørgen Gaardhøje, NBI, [email protected] 10
ALICE Si-FMD,T0,V0FMD electronics
FMD channel count
Note: We are looking into increasing the number of strips, but use more integrated FE chips - red values.
Segments (wafers)
Phi sectorsRadial sectors
HybridsChips/
hybridFE chips FE channels
Si1 inner 10 20 (256) 512 10 (16) 8 (160) 80 (5,120) 10,240
Si1 outer 20 40 (128) 256 20 (8) 4 (160) 80 (5,120) 10,240
Si2 inner 10 20 (256) 512 10 (16) 8 (160) 80 (5,120) 10,240
Si2 outer 20 40 (128) 256 20 (8) 4 (160) 80 (5,120) 10,240
Si3 10 20 (256) 512 10 (16) 8 (160) 80 (5,120) 10,240
Total system 70 140 70 (720) 360 (25,600) 51,200
