AFPGA Assignments - Complete

AFPGA Assignments

IQBAL KHAN 1

1 – Write a module for a 8 to 1 mux. Mux8.v module Mux8(i0,i1,i2,i3,i4,i5,i6,i7,con,out);

input [2:0]con; //Control Pins

input i0,i1,i2,i3,i4,i5,i6,i7; //Input Pins

output out; //Output Pin

assign out = (con == 3'b000) ? i0 :

(con == 3'b001) ? i1 :

(con == 3'b010) ? i2 :

(con == 3'b011) ? i3 :

(con == 3'b100) ? i4 :

(con == 3'b101) ? i5 :

(con == 3'b110) ? i6 :

i7;

endmodule

Mux8_TB.v initial begin

// Initialize Inputs

i0 = 0;

i1 = 0;

i2 = 0;

i3 = 0;

i4 = 0;

i5 = 0;

i6 = 0;

i7 = 0;

con = 0;

#100 i0 = 1;i1 = 0;i2 = 0;i3 = 0;i4 = 0;i5 = 0;i6 = 0;i7 = 0;con = 000;

#100 i0 = 0;i1 = 1;i2 = 0;i3 = 0;i4 = 0;i5 = 0;i6 = 0;i7 = 0;con = 001;

AFPGA Assignments

IQBAL KHAN 2

#100 i0 = 0;i1 = 0;i2 = 1;i3 = 0;i4 = 0;i5 = 0;i6 = 0;i7 = 0;con = 010;

#100 i0 = 0;i1 = 0;i2 = 0;i3 = 1;i4 = 0;i5 = 0;i6 = 0;i7 = 0;con = 011;

#100 i0 = 0;i1 = 0;i2 = 0;i3 = 0;i4 = 1;i5 = 0;i6 = 0;i7 = 0;con = 100;

#100 i0 = 0;i1 = 0;i2 = 0;i3 = 0;i4 = 0;i5 = 1;i6 = 0;i7 = 0;con = 101;

#100 i0 = 0;i1 = 0;i2 = 0;i3 = 0;i4 = 0;i5 = 0;i6 = 1;i7 = 0;con = 110;

#100 i0 = 0;i1 = 0;i2 = 0;i3 = 0;i4 = 0;i5 = 0;i6 = 0;i7 = 1;con = 111;

// Wait 100 ns for global reset to finish

#100;

2 – Use if-else construct to compare two 8-bit inputs a and b. There

are three one bit outputs g(reater), l(ess), e(qual) Compare_1.v module Compare_1( input[7:0]A,B, output reg G,

output reg I,

output reg E );

always @ *

begin

if (A == B)

E = 1;

else

E = 0;

if (A > B)

AFPGA Assignments

IQBAL KHAN 3

G = 1;

else

G = 0;

if (A < B)

I = 1;

else

I = 0;

end

endmodule

Compare_1TB.v initial begin


A = 00000000;

B = 11111111;


#100; A = 11111111; B = 00000000;

#100; A = 00000000; B = 00000000;

#100; A = 11111111; B = 11111111;

// Add stimulus here

AFPGA Assignments

IQBAL KHAN 4

3 – Structure Struct.v module Ful_Adr (A,B,CI,S,CO);

input A,B,CI;

output S,CO;

wire N1,N2,N3;

half_adder HA1 (A,B,N1,N2),

HA2 (N1,CI,S,N3);

or P1 (CO,N3,N2);

endmodule

module half_adder(X,Y,S,C);

input X,Y;

output S,C;

xor (S,X,Y);

and (C,X,Y);

endmodule

Struct_TB.v initial begin


A = 0;

B = 0;

CI = 0;


#100 A = 0; B = 0; CI = 1;


#100 A = 0; B = 1; CI = 0;

#100 A = 0; B = 1; CI = 1;

#100 A = 1; B = 0; CI = 0;

#100 A = 1; B = 0; CI = 1;

#100 A = 1; B = 1; CI = 0;

AFPGA Assignments

IQBAL KHAN 5

#100 A = 1; B = 1; CI = 1;

end

4 – Use case construct to create an 8-bit counter with a two bit

control input c, 8-bit data input din, 8-bit data output dout. All

operations are synchronous w.r.t +ve edge clock clk. Counter.v Module Counter(clk, rst, c, din, dout);

input clk, rst, c ;

input [15:0] din;

output [15:0] dout;

reg [15:0] dout;

always @(posedge clk)

casez ({rst, c})

//below given control table is as per reference of 74xx867

2'b00 : dout = 15'b0;

2'b10 : dout = din;

2'b11 : dout = dout + 1;

2'b01 : dout = dout - 1;

default : dout = 15'bx;

endcase

endmodule

AFPGA Assignments

IQBAL KHAN 6

Counter_TB.v initial begin


clk = 0;

rst = 0;

c = 0;

din = 0;


#100; din[0] = 1; din[2] = 1;

#100; clk = 1; rst=1; c=0; // Load from din to dout

#100; clk = 0;

#100; clk = 1; rst=1; c=1; // Increment 1 Time

#100; clk = 0;

#100; clk = 1; rst=1; c=1; // Increment 1 Time

#100; clk = 0;

#100; clk = 1; rst=0; c=1; // Decrement 1 Time


end

endmodule

AFPGA Assignments

IQBAL KHAN 7

5 – Use while loop to design a circuit which divides a 16-bit input din

by 3. The 15-bit output result holds the result of the division and 2

bit output Reminder. (Error) While.v `timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////

////////

// Company:

// Engineer:

//

// Create Date: 01:40:50 04/17/2015

// Design Name:

// Module Name: while

//////////////////////////////////////////////////////////////////////////

////////

module zerocount (din, result, reminder, clk, count);

input clk;

input [15:0] din;

output [15:0] result;

output [1:0] reminder;

output [4:0] count;

reg [1:0] reminder;

reg [4:0] count;

reg [15:0] result;

reg [15:0] din_reg;

//assign result [15:0] = 0;

always @(posedge clk) begin

reminder = 0; count = 0; din_reg[15:0] = din [15:0];//result

[14:0] = 0;

AFPGA Assignments

IQBAL KHAN 8

while (count < 3) begin

count = count+1;

if (din_reg[0]== 1) begin

reminder = reminder + 1;

end // if

din_reg = din_reg >> 1;

result = din_reg;

end // while

end // always

endmodule

While_TB.v `timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////

//////

// Company:

// Engineer:

//

// Create Date: 03:28:44 04/17/2015

// Design Name: zerocount

// Module Name: C:/Users/Iqbal Uddin Khan/ISE - Projects/While/While_TB.v

// Project Name: While

// Revision 0.01 - File Created

//////////////////////////////////////////////////////////////////////////

//////

module While_TB;

// Inputs

reg [15:0] din;

reg clk;

AFPGA Assignments

IQBAL KHAN 9

// Outputs

wire [15:0] result;

wire [1:0] reminder;

wire [4:0] count;

// Instantiate the Unit Under Test (UUT)

zerocount uut (

.din(din),

.result(result),

.reminder(reminder),

.clk(clk),

.count(count)

);

initial begin


din = 0;

clk = 0;


#100; din = 36; clk = 1;

#100; clk = 0;

#100; clk = 1;

#100; clk = 0;


end

endmodule

AFPGA Assignments

IQBAL KHAN 10

6 – Use a for loop to detect number of times ‘010’ pattern is found in

a 32-bit input din. The patterns can overlap each other, ex01010

counts as two patterns. The 4-bit output is named count (Error) Com_chk.v `timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////

////////

// Company: AFPGA Assignments

// Engineer: Iqbal Uddin Khan

//

// Create Date: 18:53:13 04/12/2015

// Design Name:

// Module Name: Comb_chk

// Project Name:

// Target Devices:

// Tool versions:

// Description:

//

// Dependencies:

//

// Revision:


// Additional Comments:

//

//////////////////////////////////////////////////////////////////////////

////////

module Comb_chk(din, count, clk, para_chk);

input clk;

input [31:0] din;

output [3:0] count;

output [2:0] para_chk;

AFPGA Assignments

IQBAL KHAN 11

reg [31:0] a;

reg [3:0] count, b, c;

reg [2:0] d, para_chk;

//assign d[2:0] = 0;

always @ (posedge clk)

//count = 0;

for (a=0; a<32; a = a+1)

begin

b <= a+1;

c <= a+2;

d [2:0] = {din[a], din[b], din[c]};

if (d == 2)

//if (d == 3'b010)

count = (count +1);

para_chk[2:0] = d[2:0];

//end

end

endmodule

Comb_chk_TB.v `timescale 1ns / 1ps

// Company:

// Engineer:

//

// Create Date: 08:13:32 04/19/2015

// Design Name: Comb_chk

// Module Name: C:/Users/Iqbal Uddin Khan/ISE -

Projects/combination_check/Comb_chk_TB.v

// Project Name: combination_check

// Target Device:

AFPGA Assignments

IQBAL KHAN 12

// Tool versions:

// Description:

//

// Verilog Test Fixture created by ISE for module: Comb_chk

//

// Dependencies:

//

// Revision:



//

module Comb_chk_TB;

// Inputs

reg [31:0] din;

reg clk;

// Outputs

wire [3:0] count;

wire [2:0] para_chk;


Comb_chk uut (

.din(din),

.count(count),

.clk(clk),

.para_chk(para_chk)

);

initial begin

AFPGA Assignments

IQBAL KHAN 13


din = 0;

clk = 0;


#100; din = 715827882; clk = 1;

#100; din = 715827882; clk = 0;

#100; din = 715827882; clk = 1;

#100; din = 715827882; clk = 0;

#100; din = 715827882; clk = 1;

#100; din = 715827882; clk = 0;

#100; din = 715827882; clk = 1;

#100; din = 715827882; clk = 0;

#100; din = 715827882; clk = 1;


end

endmodule

AFPGA Assignments

IQBAL KHAN 14

7 – DUAL PORT RAM (Using Code) Memory.v `timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////

// Company:

// Engineer:

// Create Date: 21:38:30 05/16/2015

// Design Name:

// Module Name: memory

// Project Name:

// Target Devices:

// Tool versions:

// Description:

// Dependencies:

// Revision:



//////////////////////////////////////////////////////////////////////////

module memory ( clk, reset, enable, read, wr_addr, rd_addr, data_in,

data_out);

integer n;

input clk, reset, enable, read;

input [7:0] data_in;

input [3:0] wr_addr, rd_addr;

output reg [7:0] data_out;

reg [7:0] mem [15:0]; // declaring width (8) and depth (16)

always @ (posedge clk)

begin

if (reset)

begin

for (n=0; n<16; n=n+1)

begin

mem[n]<=0;

end

end

else

begin

if (enable)

mem[wr_addr]<=data_in;

if (read)

data_out<=mem[rd_addr];

end

end

endmodule

AFPGA Assignments

IQBAL KHAN 15

Memory_TB.v `timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////

// Company:

// Engineer:

//

// Create Date: 22:24:43 05/16/2015

// Design Name: memory

// Module Name: C:/Users/Iqbal Uddin Khan/ISE - Projects/Memory/memory_TB.v

// Project Name: Memory

// Target Device:

// Tool versions:

// Description:

// Verilog Test Fixture created by ISE for module: memory

AFPGA Assignments

IQBAL KHAN 16

// Dependencies:

// Revision:



//////////////////////////////////////////////////////////////////////////

module memory_TB();

integer i;

reg clk, reset, enable, read;

reg [7:0] data_in;

reg [3:0] wr_addr, rd_addr;

wire [7:0] data_out;

parameter cycle=20;

memory DUT (clk, reset, enable, read, wr_addr, rd_addr, data_in, data_out );

task initialize ();

begin

enable = 0;

read = 0;

data_in = 0;

end

endtask

initial

begin

clk = 1'b0;

forever

#(cycle/2) clk=~clk;

end

task rst_dut();

begin

reset = 1'b1;

@ (posedge clk);

reset = 1'b0;

end

endtask

task stimulus (input [3:0] n, input [7:0]j);

begin

wr_addr = n;

data_in = j;

@ (negedge clk);

rd_addr = i;

end

endtask

AFPGA Assignments

IQBAL KHAN 17

task write();

begin

enable = 1'b1;

end

endtask

task reading();

begin

read = 1'b1;

end

endtask

initial

begin

rst_dut;

write;

reading;

@ (negedge clk);

for (i=0; 1<16; i=i+1)

begin

stimulus (i,($random));

end

#100 $finish;

end

endmodule

8 – Dual Port RAM with DCM at 2X (Using IP Core) Configuring DCM from IP Core

1. Click Project New Source Select IP (Core Generator) Name the Core Next

2. In pop up window FPGA Features and Design Clocking Spartan 3E, Spartan 3A Single DCM-

SP

3. Finish Next Check Verilog Next Check 2X Un Check RST and Locked Set Input Clock

Frequency NEXT

Configuring Dual Port RAM from IP Core 1. Click Project New Source Select IP (Core Generator) Name the Core Next

AFPGA Assignments

IQBAL KHAN 18

2. In pop up window Memories and Storage Elements RAMs and ROMs Block Memory

Generator NEXT Finish

3. Next In Memory Type Select SIMPLE DUAL PORT RAM Next

4. Select Write Width 08 (depends on your need) Next

5. Check Load Init File (For Initial Values if required) Brows Path of Init File or (.COE File)

6. Next Next Generate

INIT file (.COE) 1. Open Text Editor

2. Copy Following Contents

3. Save as <Name>.coe

; Sample initialization file for a

; 8-bit wide by 16 deep RAM

memory_initialization_radix = 16;

memory_initialization_vector =

12, 34, 56, 78, AB, CD, EF, 12, 34, 56, 78, 90, AA, A5, 5A, BA;

DCM_1.tfi (Instantiation Template) // Instantiate the module

DCM_1 instance_name (

.CLKIN_IN(CLKIN_IN),

.CLK0_OUT(CLK0_OUT),

.CLK2X_OUT(CLK2X_OUT) );

RAM_1.veo (Instantiation Template) //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG

RAM_1 your_instance_name (

.clka(clka), // input clka

.wea(wea), // input [0 : 0] wea

.addra(addra), // input [3 : 0] addra

.dina(dina), // input [7 : 0] dina

.clkb(clkb), // input clkb

.addrb(addrb), // input [3 : 0] addrb

.doutb(doutb) // output [7 : 0] doutb

);

// INST_TAG_END ------ End INSTANTIATION Template ---------

DCM_RAM_1.v `timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////

// Company:

// Engineer:

//

AFPGA Assignments

IQBAL KHAN 19

// Create Date: 23:34:04 05/30/2015

// Design Name:

// Module Name: DCM_RAM_1

// Project Name:

// Target Devices:

// Tool versions:

// Description:

//

// Dependencies:

//

// Revision:



//

//////////////////////////////////////////////////////////////////////////

module DCM_RAM_1(

input CLKIN_IN,

input [0 : 0] wea,

input [3 : 0] addra,

input [7 : 0] dina,

input [3 : 0] addrb,

output [7 : 0] doutb

);

// Calling DCM

DCM_1 CALL_DCM (


.CLK0_OUT(clka),

.CLK2X_OUT(clkb)

);

// Calling RAM -> your_instance_name

RAM_1 CALL_RAM (

.clka(clka), // input clka

.wea(wea), // input [0 : 0] wea

.addra(addra), // input [3 : 0] addra

.dina(dina), // input [7 : 0] dina

.clkb(clkb), // input clkb

.addrb(addrb), // input [3 : 0] addrb

.doutb(doutb) // output [7 : 0] doutb

);

endmodule

AFPGA Assignments

IQBAL KHAN 20

DCM_RAM_TB.v `timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////

// Company:

// Engineer:

//

// Create Date: 23:38:35 05/30/2015

// Design Name: DCM_RAM_1

// Module Name: /home/iqbal/ISE/RAM/DCM_RAM_1/DCM_RAM_TB.v

// Project Name: DCM_RAM_1

// Target Device:

// Tool versions:

// Description:

//

// Verilog Test Fixture created by ISE for module: DCM_RAM_1

//

// Dependencies:

//

// Revision:



//

//////////////////////////////////////////////////////////////////////////

module DCM_RAM_TB;

// Inputs

reg CLKIN_IN;

reg [0:0] wea;

reg [3:0] addra;

reg [7:0] dina;

reg [3:0] addrb;

// Outputs

wire [7:0] doutb;


DCM_RAM_1 uut (


.wea(wea),

.addra(addra),

.dina(dina),

.addrb(addrb),

.doutb(doutb)

);

initial begin

AFPGA Assignments

IQBAL KHAN 21


CLKIN_IN = 0;

wea = 0;

addra = 0;

dina = 0;

addrb = 0;

/*

// Reading only

#100; CLKIN_IN = 1; // CLK a1

for data sync

#100; CLKIN_IN = 0;

#100; CLKIN_IN = 1; // CLK a2

for data sync

#100; CLKIN_IN = 0;

#100; CLKIN_IN = 1; // CLK a3

for data sync

#100; CLKIN_IN = 0;

#100; CLKIN_IN = 1; // CLK 1

#100; CLKIN_IN = 0;

#100; CLKIN_IN = 1; // CLK 2

#100; CLKIN_IN = 0;

#100; CLKIN_IN = 1; // CLK 3

#100; CLKIN_IN = 0;

#100; CLKIN_IN = 1; // CLK 4

#100; CLKIN_IN = 0;

#100; CLKIN_IN = 1; addrb = 1; // CLK 5

wea = 1; addra = 8; dina = 33;

#100; CLKIN_IN = 0;


addra = 9; dina = 35;

#100; CLKIN_IN = 0;



#100; CLKIN_IN = 0;



#100; CLKIN_IN = 0;



#100; CLKIN_IN = 0;



#100; CLKIN_IN = 0;



AFPGA Assignments

IQBAL KHAN 22

#100; CLKIN_IN = 0; wea = 0;


#100; CLKIN_IN = 0;


#100; CLKIN_IN = 0;


#100; CLKIN_IN = 0;


#100; CLKIN_IN = 0;


#100; CLKIN_IN = 0;


#100; CLKIN_IN = 0;


#100; CLKIN_IN = 0;


*/

end

endmodule

AFPGA Assignments

IQBAL KHAN 23

LINUX Screen Shot

AFPGA Assignments

IQBAL KHAN 24

Windows Screen Shot

AFPGA Assignments

IQBAL KHAN 25

Windows Screenshot – II (With Internal DCM Signal)

Documents

AFPGA Assignments - Complete