Advanced technologies for optimized sub-quarter-micrometer SOI CMOS devices

1092 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 5, MAY 1998

Advanced Technologies for OptimizedSub-Quarter-Micrometer SOI CMOS Devices

Tommy C. Hsiao,Member, IEEE, Ping Liu, Member, IEEE, and Jason C. S. Woo,Senior Member, IEEE

Abstract—Two manufacturable technologies of fully-depleted(FD) thin-film silicon-on-insulator (SOI) MOSFET’s for low-power applications are proposed in this paper. To maintainhigh current drive while aggressively thinning down the SOIfilm, silicide is to be formed on Ge-damaged silicon layers.Ge preamorphization facilitates silicide formation at low tem-perature (�450 �C) and effectively controls the silicide depthwithout void formation. It also reduces the floating body effect. Inaddition, a reliable gate work-function engineering is introducedfor good threshold voltage management. A p+++ SiGe/Si stack gatealleviates the threshold voltage instability of SOI due to filmthickness nonuniformity and broadens the design window forchannel doping. These advanced technologies, compatible withexisting bulk CMOS technology, are integrated into SOI CMOSprocess. Excellent electrical device results are presented.

Index Terms—CMOS, silicon-on-insulator technology.

I. INTRODUCTION

FULLY-DEPLETED (FD) silicon-on-insulator (SOI) tech-nology has many attractive features as well as appli-

cations. With the revolutionary developments in SOI sub-strate materials, it has been considered as an alternative forhigh-performance low-power electronics [1]–[3]. However,in addition to wafer cost and quality issues, thin-film SOIfaces device and technology challenges. First, the series resis-tances associated with the source/drain regions limit the deviceperformance by dramatically reducing the output current,especially when the SOI films are thin [4]. Second, the floatingbody effect causes early source-to-drain breakdown [5] andcomplicates design considerations when a reduced voltagesupply is called upon. Third, the nonuniformity of the SOIfilm thickness across the wafer makes threshold voltage man-agement critical [6]. In this work, manufacturable technologiesaimed at resolving these hurdles and increasing process-ing latitude are presented. Source/drain engineering using anovel salicide process and gate work-function engineeringwith an advanced electrode material will be introduced. Geimplantation and preamorphization is used to improve thecurrent drive and breakdown voltage, and a ppolycrystalline

Manuscript received June 2, 1997; revised October 23, 1997. The reviewof this paper was arranged by Editor J. G. Fossum. This work was supportedby Defense Advanced Research Projects Agency (DARPA).

T. C. Hsiao was with the Department of Electrical Engineering, Universityof California, Los Angeles, CA 90095-1594 USA. He is now with AdvancedMicro Devices Inc., Sunnyvale, CA 94088-3453 USA.

P. Liu was with the Department of Electrical Engineering, University ofCalifornia, Los Angeles, CA 90095-1594 USA. He is now with IntegratedDevice Technology, Inc., Santa Clara, CA 95054 USA.

J. C. S. Woo is with the Department of Electrical Engineering, Universityof California, Los Angeles, CA 90095-1594 USA.

Publisher Item Identifier S 0018-9383(98)02973-6.

Si Ge gate sets the desired threshold voltage with mod-erate channel dopings. Incorporating these technologies, SOIshort-channel devices exhibit substantially improved electricalresults. Process integration for an optimal sub-0.25-m FDthin-film SOI CMOS technology can therefore be achieved,targeted for low-voltage, high-speed applications.

II. NOVEL TECHNOLOGIES

In this section, two innovative process modules will bepresented to enhance the competitiveness and reproducibilityof SOI CMOS technology. These include a new approach toimplement salicide on thin-film SOI and an alternative gateelectrode material for adjusting the threshold voltage flexibly.

A. Silicide Formation on Preamorphized Silicon

The salicide process has been applied to SOI substratesbefore [7]. However, silicide depth control for ultrathin SOIfilms is critical. When the source/drain regions are fully orclose to fully silicided, micro-voids can form due to the limitedamount of silicon available for the silicidation process. On theother hand, ultrathin silicide (20 nm) is prone to thermalagglomeration and islanding [8], resulting in poor electricalcontact. To address this issue, we have proposed a novelsalicide technology by forming silicide on damaged layerswith a low thermal cycle [9], [10]. This is accomplishedthrough the amorphization of the gate and source/drain re-gions by a low-dose Ge implantation. Ge preamorphizationis applied to greatly reduce the silicide formation energyand effectively control the silicide depth by forming a sharpamorphous/crystalline interface. It was also chosen for thefollowing reasons.

1) Ge requires a smaller dose to amorphize the films,compared to Si, and SiGe is known to have lower contactresistance with metal.

2) Ge is a neutral species suitable for both P and N-MOSFET’s.

3) SiGe has a larger lattice constant than Si, and the SiGeregions will be in tensile stress, potentially reducing theinterstitial injection from the channel that causes voidformation.

4) SiGe allows for bandgap engineering [11] to alleviatefloating body effects for SOI.

To prove the effectiveness of the proposed salicide process,Ge implantation was applied to SOI wafers with varyingbackground dopings. A very low sheet resistance with a lowthermal budget process is produced for both nand p

0018–9383/98$10.00 1998 IEEE

HSIAO et al.: ADVANCED TECHNOLOGIES FOR OPTIMIZED SUB-QUARTER-MICROMETER SOI CMOS DEVICES 1093

Fig. 1. Low thermal cycle silicide formation by Ge preamorphization. TheGe dose is 1015 cm�2 and S.E. stands for selective etch.

diffusion layers, as shown in Fig. 1. X-ray diffraction patternssupport the enhanced phase transformation of TiSifrom C49to low resistive C54 at low temperature, suggesting that Tionly reacts with the amorphized Si films at 450C. Thedamaged films thus broaden the silicide process window. Thetransmission electron microscopy (TEM) micrograph in [10]further confirms that the silicide depth is controlled by thedepth of the amorphous layer, not by the thickness of Ti.Very thin silicide films ( 20 nm) with excellent interfacemorphology can be obtained, and Ge preamorphization makesthe source/drain resistance less susceptible to the variationof deposited metal thickness. Thus, the demand for silicideuniformity can be achieved.

Preamorphization has previously been used on bulk CMOSdevices with a high-temperature RTA process [12]. In thiswork, to minimize dopant segregation and void formation, alower silicide formation thermal cycle is adopted so that thesilicide is formed within the amorphous layer. Fig. 2 shows thesilicide depth versus annealing condition. For each first annealtemperature, there is a critical time for the Ti/-Si reaction,below which the silicide depth decreases due to insufficientenergy for silicidation to take place. When the thermal cycleis chosen so that the critical time is reached, prolonging thefirst RTA will not change either the final sheet resistance or thedepth of TiSi . The critical time is shorter for higher first RTAtemperature. However, to ensure that Ti only reacts with theamorphous layer, the first RTA temperature has to be chosencarefully. In Fig. 2, partial regrowth of the amorphized layersaccounts for the different silicide depth with different RTAtemperatures. If the first RTA temperature is too high, Ti willalso react with the crystalline silicon which totally nullifies theadvantage of preamorphization. The detailed kinetics studieswill be presented in [13].

Fig. 3 shows the TiSi sheet resistance versus n-polysilicon line width. One challenge for titanium silicideis the ability to form low sheet resistance on thin gate lengths[14]. To study the thin polysilicon linewidth dependence ofTiSi 2 sheet resistance, 290 nm n-polysilicon films wereprepared by an As ion implantation and subsequently furnaceannealed for 30 min at 950C. With Ge preamorphization,the sheet resistance of 0.2-m wide Si lines is 5.8 /sq.

Fig. 2. TiSi2 silicide depth versus first anneal temperature and time. Secondanneal was 800�C for 1 min.

Fig. 3. TiSi2 sheet resistance versus n+ polysilicon line width.

This indicates that this technology extends titanium silicide tobe applicable to the sub-0.25-m regime. A similar approachcan be applied to cobalt silicide. Enhanced phase transitionwith the aid of preamorphization is observed when plain Coor Co/Ti laminate is used as the source material.

B. Gate Work-Function Engineering

To set a threshold voltage of about 0.4 V, thicker SOI films( 75 nm) will be partially depleted. On the other hand, a chan-nel doping concentration of cm or higher is requiredfor thinner films ( 50 nm). This high level of channel dopingdegrades mobility due to increased Coulombic scattering andaggravates the subthreshold slope. Additionally, the thresholdvoltage is sensitive to SOI film thickness variation. A 50-nmfilm with 5-nm nonuniformity across the wafer can result inthreshold voltage instability of 0.1 V. Using n polysilicongates for p-channel devices results in a threshold voltage lowerthan 1 V. This places strict restriction on the design spaceof n polysilicon gates. P polysilicon gates will have similarpredicaments in targeting the desired threshold voltage withgood uniformity.


Fig. 4. Simulated threshold voltage of n-channel SOI MOSFET’s withvarying film thicknesses and channel dopings, using p+ poly-Si0:5Ge0:5as the gate electrode.L = 2 �m, Tox = 7 nm, Tbox = 350 nm, andQf = 5 � 1010 cm�2.

P polycrystalline Si Ge is compatible with conven-tional silicon processing and offers a variable work-function,tuned by changing the Ge mole fraction [15]. Using a p-poly-Si Ge /Si stack as the gate electrode, CMOS devicesfabricated on SOI have demonstrated increased flexibility inthe choice of film thickness with near symmetric NMOS andPMOS channel dopings [6]. However, the degraded gate oxidequality made the CMOS threshold voltages 0.15 V less than thetarget values [6], [15]. In addition, process control of the SiGefilm deposition has never been addressed. This section presentsa reliable gate work-function engineering, setting appropriatethreshold voltages of SOI CMOS for low-power applications.

Si Ge has a smaller bandgap than Si, and the differencemainly comes from the valence band. While is about0.02 eV regardless of the Ge composition, canbe approximated as 0.74[16]. From this formulation, thework function of p poly-Si Ge would be 0.37 V lowerthan that of p polysilicon, achieving a threshold voltage of0.58 V for moderately doped long n-channel devices as shownin Fig. 4. By tuning Ge composition, the desired thresholdvoltage value can be set, and channel dopings for both NMOSand PMOS devices can be optimized.

While a threshold voltage of 0.6 V is suitable for a 3.3-V0.6- m technology, next generation low-power applicationsnecessitate a 2.5-V or 1.8-V 0.15-m technology, accordingto the CMOS scaling guideline [17]. A higher Ge compositioncan be used to adjust the work function and lower the thresholdvoltage of SOI CMOS to about 0.35 V ( 0.2 ) forsub-0.25- m channel lengths. This is accomplished by setting

to be close to the midgap of silicon, /2, resultingin a Ge composition of 70%. This is equivalent to assumea gate work function of 4.732 V, which is within 0.01 Vof the value estimated in [18]. Fig. 5 shows the simulatedthreshold voltage versus channel length for CMOS devices on50-nm SOI films. A symmetric channel doping at moderatelevels is chosen for both PMOS and NMOS. The thresholdvoltages are 0.37 V for NMOS and 0.35 V for PMOSat 0.14- m channel lengths, nearly symmetric. To examinethe reproducibility and manufacturability of the poly-SiGe

Fig. 5. Simulated threshold voltage of SOI CMOS using p+ poly-Si0:3Ge0:7 as the gate electrode withTSOI = 50 nm, Tox = 7 nm,Tbox = 350 nm, andQf = 5� 1010 cm�2. Channel doping concentrationis 1 � 1016 cm�3 for both NMOS and PMOS.

Fig. 6. Capacitance versus gate voltage plot for a SiGe 139 nm/Si 155 nmstack gate on thin gate oxide (71A). Dopant anneal was done at 500�Cfor 90 min.

technology, MOS capacitors were fabricated with a SiGe/Sistack gate. Fig. 6 shows the SiGe compositional uniformityacross a wafer with threshold voltage variations less than20 mV. A recipe optimization has been carried out so thatfilm uniformity is preserved from wafer to wafer and frombatch to batch, regardless of the SiGe film thickness or Gecomposition.

III. D EVICE FABRICATION AND PERFORMANCE

Fully-depleted SOI CMOS devices were fabricated basedon a conventional bulk CMOS process. The process flow isoutlined in Table I. For gate electrode material, both dualpolysilicon gates and p SiGe/Si stack gates were used.When the latter is used, separate implants for the gate andsource/drain are necessary for N-MOSFET’s. Table II sum-marizes the salicide modules used for device performancecomparison. For the 100-nm SOI films, only conventionalhigh thermal cycles were used to make partially or fullysilicided source/drain regions. Its potential problem will be


TABLE IPROCESSFLOW FOR FD SOI CMOS

TABLE IITITANIUM THICKNESS AND RTA TEMPERATURESUSED IN

CONVENTIONAL SILICIDE PROCESS ANDGe PREAMORPHIZATION

PROCESS FORVARYING SOI FILM THICKNESSES

demonstrated. For other SOI film thicknesses, devices wentthrough either low- or high-temperature annealing cycles,depending on if Ge preamorphization was applied. For thesewafers, the titanium thicknesses were selected so that 70%to 75% of the SOI films (source/drain regions) would besilicided if conventional RTA processing was used. The silicidedepths for the Ge preamorphization process, on the other hand,are controlled by the amorphous layers. Ge implant energiesused for 50-, 90-, and 150-nm SOI films were 20, 45, and80 KeV, respectively. The Ge dose was cm . Theinterface-controlled salicide process by Ge preamorphizationwas outlined in [9].

Fig. 7 shows typical output characteristics for a FD SOINMOS short-channel device with n polysilicon gate andfully silicided source/drain. The Ti deposited was 45 nm,more than enough to fully react with the 100-nm SOI filmsin the source/drain regions. Schottky diode behavior is ob-served at the interface of the silicided and nonsilicided regionwhich diminishes the advantages of silicidation by seriouslyincreasing the turn-on voltage and degrading the switch speedwhen applied to VLSI circuitry. The partially silicided de-vices also show degraded output characteristics with statisticaloccurrence of Schottky diode behavior, observed in 22 outof 76 short-channel devices. These observations indicate that

Fig. 7. Drain current versus drain voltage of a FD SOI NMOS short-channeldevice. The source/drain regions were fully silicided.W = 10 �m,Le� = 0:3 �m, Tox = 7 nm, TSOI = 100 nm, and the deposited Tithickness is 45 nm.

Fig. 8. Threshold voltage and subthreshold slope versus effective channellength for SOI NMOS devices with n+ polysilicon and p+ Si0:5Ge0:5/Sistack gates.W = 10 �m, Tox = 7 nm, andTSOI = 90 nm.

conventional silicide processing dramatically changes the elec-trical performance of SOI devices. For thin-film SOI, scalingthe silicide thickness in proportion to the available silicon filmabove the buried oxide cannot guarantee success in loweringthe source/drain series resistances. When dopant segregationtakes place, the high contact resistance between the silicidedand nonsilicided interface becomes a dominant term in thetotal resistance.

Fig. 8 shows the threshold voltage roll-off and subthresh-old slope of three n-channel devices. Threshold voltage wasmeasured at a low drain-to-source bias ( V) andextrapolated from the peak transconductance. The experimen-tal results are very close to simulation results. Using npolysilicon as gate electrode for SOI NMOS results in athreshold voltage below zero for lightly doped substrates,unsuitable for ULSI applications. High channel doping shiftsthe threshold voltage up to about 0.2 V for long-channeldevices. While this low threshold voltage is applicable to 1.0-V0.1- m technology, the subthreshold slopes (filled diamonds)degrade exponentially as the effective channel lengths shrink.It is clear in Fig. 8 that a midgap material like pSiGe


Fig. 9. Subthreshold characteristics for SOI short-channel CMOS devices us-ing p+ poly-Si0:3Ge0:7/Si as the gate material.Tox = 7 nm,TSOI = 90 nm,andWe� = 8:3 �m for both devices.

can set a more appropriate threshold voltage with near idealsubthreshold slope, a better alternative for SOI CMOS sub-0.25- m devices.

To set a desired threshold voltage with excellent uniformityand alleviate source/drain parasitic resistances, the optimizedthin-film SOI CMOS process is to use pSi Ge asgate material and a low thermal cycle silicidation processwith Ge preamorphization. Fig. 9 shows the subthresholdcharacteristics of SOI short-channel CMOS devices biased at

V and 2 V. A SiGe 80-nm/Si 220-nm stack gatewas used, doped by boron implantation at 12 KeV with adose of cm . For the 0.31-m NMOS transistor,a threshold voltage of 0.4 V can be achieved with moderatechannel doping ( cm ). Near ideal subthreshold slope(63 mV/decade) is observed for low drain bias and degrades to81 mV/decade for high drain voltage. The steep subthresholdslope results in a low off-state leakage with equal to

A/ m at V and V. For the0.35 m PMOS transistor, the threshold voltage is0.21 V,and the subthreshold slope is 71 mV/decade at V.The off-state leakage current is A/ m. It is clear inFig. 9 that the Ge implantation silicide process does not causean increase of junction leakage current at high drain biases.

The threshold voltage versus effective channel length isshown in Fig. 10. Both NMOS and PMOS demonstrate goodshort-channel behavior. Threshold voltages for long-channelNMOS and PMOS devices are 0.5 and0.25 V, respec-tively. The Ge composition is estimated to be between 65%and 70%, using X-ray diffraction analysis [19], which givesthreshold voltages of about 0.4 V for channel dopingsof cm . The positive threshold voltage shift inFig. 10 can be ascribed to boron penetration [20]. Using RTAprocessing instead of a furnace anneal for dopant activa-tion will alleviate this problem while adjusting the thresh-old voltages closer to the targeted values. The degradedgate oxide quality observed in [6] was corrected in ourprocess. time-dependent-dielectric-breakdown (TDDB) studiesshowed comparable ramp-voltage-stressed characteristics be-

Fig. 10. Threshold voltage versus effective channel length for SOI CMOSusing p+ poly-Si0:3Ge0:7/Si as the gate material. Channel doping levels are1 � 10

16 cm�3 for both N- and P-MOSFET.

Fig. 11. Output characteristics of SOI CMOS using Ge preamorphizationsilicide processing. Gate biases arejVGS � VTHj = 0, 0:5, 1, 1:5, 2, and2:5 V. We� = 8:3 �m, Tox = 7 nm, TSOI = 90 nm, and channel dopingis 1 � 10

16 cm�3 for both.

tween MOS capacitors (7-nm gate oxide) with ppolysiliconand p poly-SiGe/Si gates. For most channel lengths, thesubthreshold slopes of both P- and N-MOSFET’s are less than70 mV/decade. In addition to achieving threshold voltages inthe range of 0.2–0.4 V, a SiGe/Si stack gate exhibits goodthreshold voltage stability across the wafer. For example, theaverage threshold voltages of long-channel P-MOSFET’s weremeasured to be V, while the average SOI filmthickness is nm.

Measurements using Van der Pauw structures [21] indicatethat the sheet resistance of the Ge-implanted silicide layeris about 3.3 /square. The contact resistance betweenthe silicided and nonsilicided regions is extracted to be

-cm (silicide depth is about 50 nm for 90-nmSOI films). Fig. 11 shows the output characteristics of theCMOS devices. Compared to devices using conventionaltwo-step RTA silicide processing, NMOS devices exhibita 30% improvement in series resistances, whereas PMOSdevices have comparable values due to a lightly dopedsource/drain ( cm ) for the SiGe/Si gate devices. Both


Fig. 12. Measured breakdown voltage (latch) versus effective channel lengthfor SOI NMOS devices with and without Ge implantation.W = 10 �m,Tox = 7 nm, andTSOI = 90 nm.

threshold voltage control and device output characteristics canbe further improved by optimizing the thermal cycles so thatparasitic resistances and boron penetration are minimized.

IV. DISCUSSION

In addition to reducing source/drain resistance, Ge implan-tation also improves the breakdown characteristics and reducesfloating body effects. Fig. 12 shows the measured breakdownvoltage versus effective channel length for SOI devices with

equal to 90 nm. The breakdown voltage is defined as thedrain bias where A/ m with

V [22]. Devices with Ge implantation increase thebreakdown voltage by 0.3 V. The less significant improvementin breakdown voltage, compared to the pioneering work of SOIbandgap engineering [11], is mainly due to the lower Ge doseand thermal cycles used in this process [Fig. 13(a)]. In [11][Fig. 13(b)], Ge implantation was used in a very different wayfrom the proposed technique here. It was adopted to form acrystallineSiGe layer in the source/drainprior to silicidation,if any. This requires a high dose of Ge ( cm ) toreach a maximum Ge concentration close to 10% of silicon[23]. Since the holes are accumulated near the buried oxide,if a metal-semiconductor barrier can be formed and pusheddown to the buried oxide-channel interface, the suppression offloating body effects will be even more significant.

Slightly adjusted from the novel silicide process intro-duced Section II, a large angle Ge implant with higher dose(10 cm ) is used in lieu of a 7 implant (10 cm )to amorphize the silicon films, thereby reducing source/drainseries resistances and suppressing floating body effects si-multaneously [Fig. 13(c)]. This tilt implant makes a wideramorphous layer that reaches the SOI device body close tothe buried oxide interface. After the low thermal cycle salicideprocess, a metal (silicided source)-semiconductor (floatingbody) barrier exists. Together with the SiGe pocket, theminority carrier (holes in the source) recombination velocityincreases and hole injection can be further enhanced. Fig. 14shows the output characteristics of two identical SOI NMOS0.25- m devices with Ge implant angles of 7and 45, re-spectively. Large angle implantation improves the breakdown

Fig. 13. (a) Preamorphization salicide process flow as proposed inSection II, (b) crystalline SiGe source/drain formedbeforesilicidation [11],and (c) large angle tilt Ge implant to amorphize the source/drain regions andform a SiGe pocket.

Fig. 14. Output characteristics of two 0.25-�m SOI NMOS devices with andwithout Ge large angle implant.W = 10 �m,Tox = 7 nm,TSOI = 140 nm,andNA = 1 � 1016 cm�3 for both devices.

voltage by an additional 0.6 V, owing to the presence of SiGethat reduces the emitter injection efficiency of the parasiticbipolar transistor embedded in the SOI structure.

V. CONCLUSION

This work has addressed some central issues for FD SOICMOS device process integration, aimed for low-power ULSIapplications. A novel salicide technology was proposed toform silicide on damaged diffusion layers. Ge preamorphiza-tion with subsequent low thermal cycles reduces the morpho-logical instability of silicide on doped polysilicon films andcontrols the silicide depth, forming silicide with good ohmiccontact to the adjacent nonsilicided regions. The SiGe layerunderneath the silicide helps improve breakdown characteris-tics. Increasing the Ge implantation angle and dose, a SiGepocket and a metal-semiconductor barrier can be created tofurther enhance the hole flow into the source and improvefloating body effect. A variable gate work-function schemewas also proposed, using a ppolycrystalline SiGe/Si stackgate. The Ge composition is varied to achieve the desired


threshold voltage while giving latitude in channel doping.Using this work-function engineering, a threshold voltage of0.2–0.6 V can be easily obtained for short-channel devicesfabricated on ultra-thin-film SOI. These two deliverable tech-nologies are developed so that process integration for optimalsub-0.25- m SOI CMOS devices can be accomplished. Withfurther technology advancement, SOI indeed is an alternativeto conventional bulk silicon technology, especially for low-power electronics.

ACKNOWLEDGMENT

The authors would like to thank C. Hwang for help withthin polysilicon line preparation, and A. Wang and Prof.K. Saraswat of the Center for Integrated Systems, StanfordUniversity, Stanford, CA, for the fruitful discussion of SiGedeposition.

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Tommy C. Hsiao (S’92–M’98) received the B.S. degree in electrical engi-neering from National Taiwan University, Taipei, in 1987, and the M.S. andPh.D. degrees in electrical engineering from the University of California, LosAngeles, in 1993 and 1997, respectively.

Currently, he is a Senior Process Integration Engineer at Advanced MicroDevices Inc., Sunnyvale, CA, where he is involved in the research and devel-opment of state-of-the-art flash memory process technology. From November1994 to March 1997, he conducted his research at Stanford NanofabricationFacility (SNF), Stanford, CA, focusing on process development and integra-tion issues associated with SOI CMOS devices in submicrometer regimes.His research interests are in the modeling and characterization of SOI CMOSdevices.

Ping Liu (M’95) was born in China on July 6,1965. He received the B.S., M.S., and Ph.D. degreesin electrical engineering from Fudan University,Shanghai, China, in 1986, 1989, and 1992, respec-tively.

Currently, he is working on CMOS process in-tegration at Integrated Device Technology, Inc.,Santa Clara, CA. From 1992 to 1994, he was withthe Shanghai Institute of Metallurgy, the ChineseAcademy of Sciences, working in the area of ionimplantation and SOI technology. From March 1994

to September 1994, he was a Visiting Scholar at the University of Surrey,Surrey, U.K., where he worked on salicide and SOI technologies. FromNovember 1994 to October 1997, he was a Research Associate at theUniversity of California, Los Angeles, where he was involved in shallowjunction technology, salicide technology, and process integration for thethin-film SOI CMOS devices.

Jason C. S. Woo(S’83–M’87–SM’97) received the B.A.Sc. (Hons.) degree inengineering science from the University of Toronto, Toronto, Ont., Canada, in1981, and the M.S. and Ph.D. degrees in electrical engineering from StanfordUniversity, Standord, CA, in 1982 and 1987, respectively.

In 1987, he joined the Department of Electrical Engineering, the Universityof California, Los Angeles, where he is currently a Professor. His researchinterests are in the physics and technology of novel device and devicemodeling, and has authored or coauthored more than 90 papers in technicaljournals and refereed conference proceedings in these areas.

Dr. Woo served on the IEEE IEDM Program Committee from 1989 to 1990and from 1994 to 1996, and was the Publicity Vice Chairman in 1992 andthe Publicity Chairman in 1993. He has been the Workshop Chairman anda Technical Committee Member of the VLSI Technology Symposium since1992. He has served on the committee for the IEEE SOI Conference since1995. He received a Faculty Development Award from IBM in 1987 through1989.

Documents

Advanced technologies for optimized sub-quarter-micrometer SOI CMOS devices