IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 3, MARCH 2002 467

Advanced Model and Analysis of Series Resistancefor CMOS Scaling Into Nanometer Regime—Part II:

Quantitative AnalysisSeong-Dong Kim, Member, IEEE, Cheol-Min Park, Member, IEEE, and Jason C. S. Woo, Senior Member, IEEE

Abstract—Source/drain (S/D) series resistance components anddevice/process parameters contributing to series resistance are ex-tensively analyzed using advanced model for future CMOS designand technology scaling into the nanometer regime. The total se-ries resistance of a device is found to be very sensitive to the varia-tions of the sidewall thickness, the doping concentration in the deepjunction region, and the Schottky barrier height of silicide contact.A prediction of series resistance trends with technology genera-tion indicates that silicide-diffusion contact resistance and overlapresistance will be major components in total series resistance ofnanometer-scale CMOS transistors scaled according to the ITRSroadmap. The key factors for challenging scaling barriers relatedto parasitic resistance are quantitatively examined as a function oftechnology scaling and it is shown that the series resistance can besubstantially reduced through controlling both abruptness of S/Djunction profile and silicide Schottky barrier engineering.

Index Terms—CMOS, high- dielectric, modeling, polysilicongate depletion effect, scaling, series resistance, ultra shallow junc-tion.

I. INTRODUCTION

T HE ultra-shallow source/drain (S/D) junction is an in-dispensable requirement to suppress short channel effect

(SCE) in CMOS technology in the nanometer channel lengthregime and the design of S/D structure with ultra-shallowjunction is susceptible to a high series resistance problemwhich degrades the ultimate intrinsic device performance [1],[2]. To overcome this scaling difficulty and identify the sourceof the high resistance problem, the extensive analyses for seriesresistance components and the device/process parameters ofscaled CMOS contributing on series resistance are highlyrequired. As reported in the previous paper [3], our advancedmodeling takes important features of S/D structure of extremelyshort channel devices into account such as nonnegligible po-tential relationship in MOS accumulation region, lateral andvertical doping gradient effect of source/drain extension (SDE)junction and critical parameters of silicide diffusion contactsystem in addition to current behavior in ultrashallower SDEjunction. The parasitic series resistance has been modeled bydividing into four components: SDE-to gate overlap resistance

; S/D extension resistance ; deep S/D resistance ;and silicide-diffusion contact resistance . Each resistance

Manuscript received October 10, 2001; revised November 19, 2001. The re-view of this paper was arranged by Editor K. Shenai.

The authors are with the Department of Electrical Engineering, University ofCalifornia, Los Angeles, CA 90095 USA (e-mail: woo@ee.ucla.edu).

Publisher Item Identifier S 0018-9383(02)02114-7.

Fig. 1. Schematic representation of source/drain structure and parasitic seriesresistance components developed in advanced model.

component consists of the parallel or series combinations ofsubresistance components according to the carrier conductionpath and junction structure profiles as illustrated in Fig. 1.This modeling approach provides very useful tool for physicalexamination of S/D series resistance components in detail aswell as accurate estimation of them.

In this paper, the advanced model is applied to investigatemajor resistance component and essential parameters impact ondevice optimization and scaling. We establish three CMOS tran-sistors with different gate length in the nanometer scale based onprojection of ITRS roadmap [4] to assess behavior of resistancecomponents and parameters quantitatively as technology pro-gresses and discuss about the key factors for challenging scalingbarriers related to parasitic resistance.

II. I MPACT OF SOURCE/DRAIN PARAMETERS

The series resistances of CMOSFETs of which gate lengthsare 100, 70, and 50 nm are calculated by use of the advancedmodel where the device structure and total resistance valueswere calibrated with the device simulations [3]. The devicestructure parameters of each technology are chosen accordingto the projections of ITRS road map [4] and listed in Table I.ITRS road map assumed the successful challenge of thescaling issues associated with the doping technology and thedevice dimension for the next generation devices, so that the

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468 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 3, MARCH 2002

TABLE IINPUT DEVICE STRUCTUREPARAMETERS CHOSENACCORDING TO THE

PROJECTIONS OFITRS ROAD MAP FORTHREE CMOS TECHNOLOGIES IN

WHICH THE GATE LENGTHS ARE100, 70,AND 50 nm

TABLE IISELECTED OUTPUT PARAMETERS CALCULATED BY ADVANCED MODEL AT

EACH OPERATING GATE VOLTAGE FORTHREE NMOS DEVICES WITH

DIFFERENTTECHNOLOGIES

parameters used in this work are based on the extremely heavilydoped, ultrashallow SDE junction and properly scaled lateraland vertical S/D dimensions. The selected output parameterscalculated by model at each operating voltage for three NMOStechnologies are also listed in Table II.

Fig. 2(a) shows source series resistances and their compo-nents of 100 nm-gate-length NMOSFET as a function of supplygate voltage estimated by advanced model. All the resistancecomponents except show almost the same contribution tototal series resistance in 100 nm gate length technology. As seenin experimentally and simulation study [5], [6], the model pre-dicts that the decrease of series resistance withincurred byoverlap resistance reduction due to enhanced carrier accumu-lation. The behavior of overlap resistance components are de-picted in Fig. 2(b). As increases, accumulation carrier den-sity increases in nearly exponential manner, so that and

sharply decrease. On the contrary, the parallel combinationof and is not changed much with , because thecurrent spreading into the bulk exert much influence on sub-re-sistance component over whole ranges. This results indicate

Fig. 2. (a) Series resistances and their components of 100 nm-gate-lengthNMOSFET as a function of gate voltage estimated by advanced model. (b)Calculated resistance components of the overlap region.

that plays an important role in determining the voltage-dependent overlap resistance characteristics.

The polysilicon gate depletion effect (PDE) is anotherlimitation for nanoscale short channel devices since it increasesequivalent thicknesses of aggressively scaled oxide layersbelow 2 nm and degrades device current performance. Theseries resistance is also affected by PDE as calculated byadvanced model in Fig. 3. The overlap resistance increases withdecreasing poly-doping concentration and is more degraded inlower SDE doping concentration due to the pronounced PDE[7].

Because of large direct-tunneling current of extremely thingate oxide, a high dielectric constant material is being attemptedto be employed in gate stack system or sidewall spacer [8], [9].The effect of high- sidewall material on series resistance isalso demonstrated in Fig. 4. In Fig. 4, it can be found that theuse of very high- dielectric sidewall significantly induces the

KIM et al.: ADVANCED MODEL AND ANALYSIS OF SERIES RESISTANCE FOR CMOS SCALING 469

Fig. 3. Poly-depletion effect on series resistance for different poly-doping andSDE doping concentration obtained by advanced model.

Fig. 4. Effect of high-� sidewall material on the series resistance. The useof high-� dielectric sidewall reduces the extension resistance by inducing thecarrier accumulation in surface extension region due to the increased fringingfield.

carrier accumulation in surface extension region due to the in-creased fringing field, resulting in reduction in and hence

as reported in [9], while this may invoke the increase ofgate-to-S/D capacitance problem.

Fig. 5 shows the sensitivity of total series resistance toprocess/device parameters calculated by the model when theprocess/device parameters are varied up to15 . The totalseries resistance is very sensitive to even small variations of theSchottky barrier height, the sidewall length, and dopingconcentration in the deep junction region .

III. A NALYSIS ON CMOS SCALING

In order to find and overcome the series resistance obstaclein future CMOS scaling, it is necessary to understand the rela-tive contributions of each resistance component to the total se-ries resistance. Fig. 6(a) and (b) show the relative contributionsof each resistance component to the total series resistance as afunction of technology scaling calculated by the model for con-ventional planar type NMOS and PMOS, respectively. The de-

Fig. 5. Sensitivity analysis of series resistance to the process/deviceparameters. The sidewall thickness(L ), the doping concentration in thedeep junction region(N ), and Schottky barrier height(� ) of silicidematerial are the most sensitive process/device parameters to series resistance.

vice dimensions and doping concentrations of each technologyare assumed to be scaled down according to ITRS roadmap aslisted in Table I, and the same scaled device parameters areemployed for both NMOS and PMOS except physical param-eters related to silicide Schottky contact and carrier mobility.The Schottky barrier height of midgap-level silicide contact ma-terial is assumed for all technologies and are fixed at 0.6 eVand 0.51 eV for NMOS and PMOS, respectively. It should benoted from Fig. 6 that the silicide-diffusion contact resistance

and the overlap resistance are expected to be domi-nant resistance components for future technology scaling. Thesum of their contributions on total series resistance is about 70%at 50 nm gate length. The important trends are that the contribu-tion of the silicide-diffusion contact resistance increases as thetechnology shrinks, while the overlap resistance is almost at thesame level for all technologies. In particular, the overlap resis-tance component is more severe in the case of PMOS due to therelatively poor accumulation layer mobility. Fig. 6 suggests thatmuch significant effort for S/D engineering should be concen-trated on the SDE-to-gate overlap and the contact region.

In order to optimize S/D structure to obtain the best possibleelectrical performance as device is scale down, the extensive andquantitative analysis on the key optimization parameters of eachseries resistance component is essential. The device parametersseriously contribute to series resistance are examined by ana-lyzing three important resistance components,, , and

as a function of technology as follows.The first component is the SDE-to-gate overlap resistance.

Fig. 7 shows component analysis of scaling as a func-tion of technology gate length. Among the resistance compo-nents, is the most troublesome component in scaling of

. To find out serious device parameters impact on, theoverlap resistance and its component variations are calculatedand plotted as a function of lateral abruptness of SDE profilefor different SDE doping in Fig. 8. The inset of Fig. 8 illus-trates the lateral doping profile variation as a function of theoverlap distance when the lateral abruptness is kept constant of

470 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 3, MARCH 2002

Fig. 6. Relative contributions of resistance components to the total seriesresistance as a function of technology scaling calculated by advanced model.The device parameters of each technology are scaled down according to ITRSroadmap. (a) NMOS and (b) PMOS.

Fig. 7. Overlap resistance(R ) and its component variation as a function ofgate length. Accumulation resistance(R ) is most troublesome componentto reduce.

10 nm/dec. As the lateral abruptness decreases, the resistancecomponents of the overlap region decrease depending on lateralabruptness of SDE profile, but show a little differences with themaximum doping concentration of SDE. This result suggeststhat scaling can be mainly determined by the lateral junc-tion profile slope rather than its maximum doping concentrationwhich is primarily limited by dopant solid-solubility and the de-vice SCE due to difficulty of junction depth control.

Fig. 8. Overlap resistance(R ) and its component variation as a function oflateral SDE abruptness. The inset illustrates the lateral doping profile variationas a function of the overlap distance when the lateral abruptness is kept constantof 10 nm/dec.

Fig. 9. Effect of vertical abruptness of SDE junction profile on seriesresistance for the same junction depth(X ). The inset illustrates thevariation of doping profile depending on the surface doping orX location.

The importance of the abruptness of SDE junction profile isalso governed in reduction as can be seen in Fig. 9. Theinset of Fig. 9 illustrates variation of doping profiles depend onthe surface doping or location. The increase of verticalabruptness with increasing has a significant effect on

reduction as compared to that of surface extension doping.The extension resistance can be reduced down to around 80%,if the box-shaped vertical junction profile is achieved. But thelarge increase of surface doping concentration of SDE regionmay be detrimental to short channel performance.

The silicide-diffusion contact resistance is the most seriouscomponent to reduce as discussed in Fig. 6. The controlling ofspecific contact resistivity will be essential for reductionas given by model formula [3] . In this model, the specific con-tact resistivity can be obtained from the input parameters basedon the assumptions of final Gaussian doping concentration ofthe deep junction region and the silicide materials with the bar-rier height of the midgap such as TiSiand CoSi. The effectivecontact lengths determined by the edge of the sidewall and theisolation in the longitudinal direction are found to be smallerthan calculated transfer lengths for all technologies. The nu-merical simulation have shown that the one-dimensional (1-D)

KIM et al.: ADVANCED MODEL AND ANALYSIS OF SERIES RESISTANCE FOR CMOS SCALING 471

Fig. 10. (a) Resistance variation as a function of deep junction dopingconcentration. (b) Resistance variation as a function of Schottky barrier height.The percentage ofR contribution can be reduced remarkably by Schottkybarrier height lowering technique using alternative low barrier height metal(e.g., ErSi for NMOS) instead of midgap (0.57–0.65 eV) silicide metal.

transmission line model (1-D-TLM) characterizes varia-tion quite well when the contact size is smaller than the transferlength [10]. The calculated specific contact resistivity of the sil-icon/silicide interface is on the order of 10 cm and neg-ligible for larger channel length devices, whereas, in the caseof nanoscale devices, it makes a relatively large contribution tototal series resistance even with heavily doped deep junction asshown in Fig. 10(a). To reduce contribution in next gener-ation technology, it is necessarily required that maximizing theactive dopant concentration at the silicide/Si interface or mini-mizing Schottky barrier height to obtain an acceptable specificcontact resistivity as evaluated in Fig. 10. In Fig. 10(b), it is ob-served that the percentage of contribution can be reducedremarkably to the value below that of and even witha small reduction of Schottky barrier height, while the maxi-mizing doping concentration has a fundamental limitation of

Fig. 11. Resistance contributions of each resistance component to the totalseries resistance in sub-50 nm NMOS according to S/D engineering variation.R value can be reduced to 35% of that of roadmap structure if box-shapedS/D junction and low Schottky barrier height material will be successfullychallenged.

solid solubility. Although technologically problematic yet, theSchottky barrier height lowering technique by using alternativemetal having lower barrier height of 0.2–0.25 eV, e.g., ErSifor NMOS and PtSi for PMOS [11] or using lower bandgaplayer like Si Ge films [12] will be a possible strategy forsuccessful CMOS scaling.

Fig. 11 shows the expected trend of the series resistancereduction by S/D engineering on the basis of 50 nm devicewith conventional planar type NMOS structure predicted byadvanced model, when the progressive engineering of boththe S/D junction abruptness and Schottky barrier height aresuccessfully achieved. More than 50% reduction in seriesresistance will be expected and especially, the resistance com-ponents related to ultra-shallow S/D junction will be reduceddramatically by box-shaped SDE and deep junction profile.

IV. CONCLUSION

The advanced physical model is employed to analyze theeffect of S/D device parameters on series resistance contri-bution and predicts series resistance reduction trend withCMOS technology generation below 100 nm gate length.The model well characterizes nanoscale CMOS structure andresistance characteristics including polysilicon depletion effectand high- sidewall spacer effect. It is shown that the sidewallthickness, the doping concentration in the deep junction region,and the Schottky barrier height of silicide material are themost sensitive process/device parameters to series resistancevariation. The series resistance trend with respect to technologyscaling predicts the sum of silicide-diffusion contact andoverlap resistance contributions on total series resistance willbe about 70% at 50 nm gate length and the percentage of thesilicide-diffusion contact resistance contribution increases asthe technology shrinks. The modeling analysis suggests thatadvanced S/D engineering focusing on highly abrupt SDEjunction profile and lower Schottky barrier silicide contactshould be challenged for successful CMOS technology scaling.

472 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 3, MARCH 2002

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Seong-Dong Kim(S’94–M’97) was born in Chonan, Korea, in 1967. He re-ceived the B.S., M.S., and Ph.D. in electrical engineering from Seoul NationalUniversity, Seoul, Korea, in 1990, 1992, and 1996, respectively. His graduateresearch was focused on the power semiconductor devices and ICs.

From 1996 to 1999, he was with the System IC Research and DevelopmentCenter, Hyundai Electronics Industries, Seoul, Korea, where he engaged in theresearch and development of submicron CMOS technologies, CMOS imagesensors, and high voltage CMOS-DMOS ICs. In December 1999, he joined theDepartment of Electrical Engineering, University of California, Los Angeles,as a Research Engineer, where he has been conducting research on the physics,technology, and modeling of nanometer-scale CMOS devices. His research in-terests include the design, fabrication, and modeling of CMOS VLSI technolo-gies, SOI devices, and power semiconductor devices.

Cheol-Min Park (S’96–M’01) was born in Seoul, Korea, in 1971. He receivedthe B.S. and M.S. degrees in electrical engineering from Seoul National Univer-sity, Seoul, in 1994 and 1996, respectively, where he is currently pursuing thePh.D. degree in the School of Electrical and Computer Engineering.

His current research interests are in electrical and structural properties ofpoly-Si thin-film transistors.

Jason C. S. Woo(S’83–M’87–SM’97) received the B.A.Sc. (Hons.) degree inengineering science from the University of Toronto, Toronto, ON, Canada, in1981, and the M.S. and Ph.D. degrees in electrical engineering from StanfordUniversity, Stanford, CA, in 1982 and 1987, respectively.

In 1987, he joined the Department of Electrical Engineering, the University ofCalifornia, Los Angeles, where he is currently a Professor. His research interestsare in the physics and technology of novel device and device modeling, andhe has authored more than 100 papers in technical journals and the refereedconference proceedings in these areas.

Dr. Woo served on the IEEE IEDM Program Committee from 1989 to 1990and from 1994 to 1996, and was Publicity Vice Chairman in 1992 and the Pub-licity Chairman in 1993. He has been the Workshop Chairman and a TechnicalCommittee Member of the VLSI Technology Symposium since 1992. He hasserved on the committee for the IEEE SOI Conference since 1995. He receiveda Faculty Development Award from IBM from 1987 to 1989.