XEEE TRANSACTIONS OK ELECTROK DEVICES, NOVEMBER 1972 1215

are sequentially determined for N = 3 , 4, (L- 1). IEEE, vel. 57, pp; 1250-1259, 1969. recovery diode for pulse and harmonic generation circuits,” Proc.

Finally, with substitution of right-end value y(L) in [3] K. Schunemann, Theory of frequency multiplication including (25) , unknown vectors y ( N ) , N = ( L - l ) , (L-2) , . . . , transition loss,” I E E E Tvans. Electron Devices, vol. ED-18, pp. 2 can be determined.

210-214, Mar.l11971. [4] A. De Mari, An accurate numerical one,-dimensional solution

of the p-n junction under arbitrary transient conditions,” Solid- State Electron., vol. 11, pp. 1021-1053, 1968.

[ 5 ] D. L. Scharfetter and H. K. Gummel, “Large-signal analysis of a The author to thank K. ~ ~ j i ~ ~ ~ ~ for his sup- silicon Read diode oscillator, I E E E T r a n s . Electron Devices, vol.

ED-16, pp. 64--77, Jan. 1969. port of this work. [6] W . Shockley and LV. T. Re?$, Jr., “Statistics of the recombina-

tione of holes and electrons, Phys. Rev., vol. 87, no. 5 , pp. 835-

ACKNOWLEDGMENT

REFERENCES 842, Sept. 1952.

[I] J . L. Moll, S. ,f(rakauer, and R. Shen, “ P - N junction charge- Partial Differential Equations. New York: Wiley, 1960.

[2] J . L. Moll and S. A. Hamilton, Physical modeling of the step l i d Differential Equntionr. New York: Elsevier, 1969.

171 G. E. Forsythe and \i’. R. Wasow, Finite-Difference Methods for

storage diodes, Proc, IRE, vol. 20, pp. 43-53, Jan. 1962. [8] D. U. von Rosenberg, Methods for the Numerical Solution of Par-

Correspondence

Admittance of a Forward-Biased P-N+ Junction Diode

B. V. GOKHALE

Absfract-Numerical solutions of the basic semiconductor trans- port equations are used to analyze the ac behavior of a forward- biased diode.

Two different definitions of the capacitance C of a p-n junction diode are found in the literature: 1) C = d Q / d V , where Q is the total charge of any one kind of carrier and V the applied voltage; and 2)

frequency. De Mar i [ l ] raised the question of whether the two defini- C= ( I /@). Im Y, where Y is the complex admittance and w the radian

tions are equivalent and suggested ac calculations to resolve the situa- tion. The results of such calculations are described in this cor- respondence.

Note that the two definitions cannot be equivalent under all conditions. The continuity equation for a carrier (electron or hole) relates the rate of increase of stored charge to the rate of loss due to recombination and to the s u m of currents of the particular carrier type entering both the terminals. However, the admittance is concerned with the current of both the carrier ty@es entering one terminal. A simple relation between the admittance and the rate of increase of stored charge exists only when each terminal carries just one type of carrier current, a situation possible for a reverse-biased diode.

A recent paper by O’Hearn and Chang [2] accepts complete equivalence of the two definitions; the demonstration of the equiva- lence is incorrect because their equation (13) contradicts the equation of continuity. Therefore, the calculations of O’Hearn and Chang are based on definition 1 j as stated previously.

The structure of the n+-p diode used in the present calculations is shown in Fig. 1. The basic semiconductor transport equations and the technique of numerical solution have been fully described in an earlier report by the present author [3]. Solutions were obtained at a number of dc forward-bias points. A t each bias point, ac solutions at a number of different frequencies were obtained.

The incremental capacitances calculated according to the two definitions are shown in Fig. 2. Curve 1 shows the dc calculation of dQ/d V , while curve 2 shows the low-frequency Zinait of the ac calcula- tion according to definition 2) . Note that the discrepancy between the two definitions of capacitance exists even in the limit of zero

The author is with the Components Division, I B M East Fishkill Facility, Manuscript received August 16, 1971; rpvised M a y 29, 1Y72.

Mopfwfll Junction, PI‘, 1’. 12533.

frequency. The imaginary part of Y becomes negative for bias volt- ages above 0.590 V; this indicates inductive susceptance [4]. The transition from capacitive to inductive susceptance occurs at the onset of heavy injection as judged by the change of slope of the dc log J versus V and log Q versus V characteristics.

The capacitance calculated according to definition 2) is frequency dependent. A modification of definition 2) as discussed in the follow- ing simplifies the picture. T o a close approximation the frequency dependence of Y can be fitted to the formula

involving the three positive real parameters g o , g l , and WY, which are independent of the frequency but depend upon the bias voltage. In the complex Y plane, the admittance values a t different frequencies fa.11 on a semicircle of radius 1 go -g, I /2, with the center on the axis of reals at (go+g1j/2. The semicircle intersects the axis of reals at the points Y =go and Y =g,. The parameter go is identical with the dc incremental conductance. WY represents the radian frequency at which the susceptance has the largest numerical value.

Equation (1) is applicable in the inductive as well as in the ca- pacitive range of bias voltages. In the capacitive regime, the expres- sion (go-glj is negative and thesemicircle liesin the upper half-plane. In the inductive regime, (go--gl) is positive and the semicircle lies in the lower half-plane. I t is well known that the admittance function of (1) is represented by the equivalent circuiit of Fig. 3(a) or (b) de- pending on whether (go-glj is negative or positive.

Fig. 4 shows a typical plot in the Y plane. Numerical values of the parameters go, g,, and WY may be easily determined from the plot. Individual carrier admittances Y,, and Y, cam be defined in terms of the electron and hole currents at the ohmic contact on the high-re- sistivity side of the junction. Their semicircular loci are also shown in Fig. 4. Y p is capacitive while Y, is inductive. This is found to be true at all bias voltages. A t low voltages Yp dominates and Y is ca- pacitive. A t high voltages, Y, dominates and Y i s inductive. At high frequencies, the loci of Y, Y,,, Y, depart considerably from a semi- circle. The equivalent circuits of Fig. 3 are essentially low-frequency circuits. At freq,uencies in the gigahertz range, Y does not equal the vector sum of Y, and Y p because displacement current becomes sig- nificantly large.

Fig. 5 shows the bias dependence of the parameters go and gt. and Fig. 6 that of W Y . Also shown i n Fig. 6 is the dc incremental param- eters wL defined by

TEEE TRANSACTIONS ON ELECTRON DEVICES. NOVEMBER 1972

x = o I X j = 0.4 ,& X = 3.04,~

I I I

&I = 1280.0 ."p = 477.0 cm2/-s

+V

p n = 105.0 1 p p = 57.0 cm*/V -s

Lp = 3 . 8 ~ I Ln = 18.2&

I I I I I I

Fig. 1. T I C diode model.

CAPACITANCE

1 APPLIED VOLTAGE

I I 1 I I .

0 0.1 0.2 0.3 0.4 '1.8 0.6 0.7 0.8 0.9

Fig. 1. Capacitance calculated according to the two definitions.

COKRESPOSDENCE

g 1

P

.I; 0

(b) Fig. 3. Diode equivalent circuits.

ADMITTANCE MHO/cmZ

I "

0 100. 200. 300. 400. 600. 600. 700. 800. 900. REAL

Fig. 4. Complex admittance plot. V =0.600 V;/r =136 MHz.

1218 IEEE TRANSACTIONS ON ELECTROS DEVICES, NOVEMBER 1972

0.2 0.3 0 4 0.18 0 6 0 7 0.8 0.9

Fig. 5 . Equivalent circllir. parameters go, gl as functions of the c i: hias voltage.

id

1010 -

109 -

10s -

107 I VOLT

I

0 0 1 0.2 03 0.4 0.5 0.6 0.7 0.8 0.9 L

Fig. 6. ~ r ? and w y as 'unctions of the dc hias voltage.

CORRBSPOSDENCE 1219

~c = go/ (dQ/dV) = d J / d Q . (2) wC is the reciprocal of the well-known transit time. The dashed line in Fig. 6 shows the radian frequency above which (1) does not accurately fit the computed values of Y (above 1 percent error).

The transient response of the circuits of Fig. 3 to an infinitesimal applied voltage step z’ is well known. In each case, there is an initial current jump of magnitude vgl and the final steady-state value is ogo. In the capacitive circuits, the jump is followed by an exponential decay, while in the inductive circuit, there i s an exponential rise. In either case, the time constant is l , / ~ p .

Since the equivalent circuit is inapplicable at arbitrarily high frequencies, the shape of the initial current jump cannot be predicted, but the exponential response and the value of the time constant l /wy may be accepted when the validity of the circuit extends to radian frequencies well above W Y . I t i s clear that in the high-injection range of bias voltages the usual stored charge transit time 1 /ac does not give the rise and fall times correctly.

The inductive nature of the electron current and the capacitive nature of the hole current are consistent with the physical picture of the effect of a voltage step-a sudden rise in the electron density near the junction followed by a gradual adjustment of the injected electron profile. As the electrons flow towards the p-contact, the electron current there increases while the hole current decreases be- cause fewer holes are required to establish neutrality [5].

REFEREKCES [l] A. deMari, “An accurate numerical steady state one-dimensional solution of the

p-n junction,” Solid-State Electron., vol. 11, pp. 33-58, 1968. [2 ] W. F. O’Hearn and Y . F. Chang, ‘(An analysis of the frequency d;pendence of

Electron., vol. 13, pp. 473-483, 1970. the capacitance of abrupt p-n junction semiconductor devices, Solid-State

131 B. V. Gokhale. “Numerical solutions for a one-dimensional silicon n-p-n transis-

[4] I. Ladany, “An analysis of inert(a1 inductanbe in a junchon device,” I R E tor,” IEEE Trans. Electron. Devices vol. ED-17 pp. 594-602 Aug. 1970.

Electron Devices, vol. ED-7, pp. 303-310, Oct. 1960. Granted the usual assump-

deMari’s question several years before it was asked! tions and approximations of an analytical approach, this paper answered

51 J. ,Lindmayer and C . Y . Wrigley, Fundamentals of Semicoqzduclor Deuices. Prlnceton. N. J.: Van Nostrand, 1965, p. 54.

Ion Implantation Combined with Silicon-Gate Technology

C. C. MAI, M. HSWE, AND R. B. PALMER

Abstract-Ion implantation has been combined with silicon-gate technology for the fabrication of MOS integrated circuits that possess the principal advantages afforded by each technique. This process is essentially a standard silicon-gate process to which a single masking step and an ion-implantation step have been added in order to provide the depletion-mode devices.

INTRODUCTION Ion implantation has been combined with silicon-gate technology

for the fabrication of MOS transistors that possess the principal ad- vantages afforded by each technique. These advantages [1]-[4] include the following.

1) L.ow threshold voltage operation that results in compatibility with bipolar integrated circuits.

2) Self-aligned gate structures that reduce capacitance and thus improve speed.

3) Am additional interconnecting conductor (the polycrystalline silicon) that can result in greater functional density.

4) The ability to fabricate both enhancement-mode and deple- tion-mode devices on the same chip, which can result in numerous improvements [5], [ 6 ] , including improved speed-power product and increased functional density.

PROCESS The standard silicon-gate process has been described previously

i11 the literature [2] , [3]. In the following section, we report the addi- tional steps necessary to fabricate enhancement- and depletion-mode silicon-gate devices on the same chip for p-channel devices.

Manuscript receiv$d April 7, 1972; revised May 31, 1972. The authors are with the Mostek Corporation, Worcester, Mass. 01606.

TABLE I -

Silicon substrate 4-8 Q.cm (111) VT a t 1 PA X initial X gate VTP a t 1 p A X glass VT.M 1’

2.3 V 15 000 i 500 A 12’00 k 50 A 2 7 v 40 V 8000 A

- , I

X j (boron) PPOlY Psilieon diffused area

Step I : The process is unchanged through the gate oxidation step. At the completion of this step, a 1200-A thermal oxide covers the active regions.

Step 2 : The wafers are then covered with photoresist and a pat- tern is developed that clears the resist from the active areas of the devices to be made depletion type. Note that no etching is required in this masking step.

Step 3: IiB+ ions are implanted through the gate oxide, which are unprotected by resist. The energy of tbe ions (44 keV) is insuffi- cient to penetrate the photoresist (10 000 A thick), but readily pene- trates the unprotected 1200-A gate oxides. The implantations were carried out at room temperature and at pressures of less than 1 x 10-6 torr. The doses were varied from 0 to 1.2 X 1012 ions/cm2.

Step 4: Photoresist is removed and the wafers are annealed for 10 min in dry nitrogen at 95OOC. This anneal is sufficient t o allow essen- tially complete utilization of the implanted species, and effectively, i t eliminates the radia:ion damage associated with the implantation.

Steps 2,3, and 4 are the only deviations necessary from the stand- ard silicon-gate process.

Test patterns were fabricated in the manner described in the pre- ceding. Various implant doses were used to produce the desired threshold shifts. The data reported in this paper were all taken from a silicon-gate FET having a width of 3 mil and length of 3 mil. Typical parameters of the unimplanted FET are shown in Table I.

EFFECT OF IMPLAKTATIOX ON DEVICE CHARACTERISTICS I t was found that the shift in threshold voltage was proportional

to the implanted dose, and that depletion-mode devices were pro- duced by ion doses in excess of 4 x 1 0 ” ions/cm2. Fig. 1 shows the behavior of two parameters as a function of ion dose. The first curve (left ordinate scale) presents the variation AVT of the threshold volt- age (measured at a drain current of 1 M A ) with increasing ion dose. Thus, at an approximate ion dose of 2 X 10” ions/cm2, the threshold voltage VT was shifted by 0.95 V toward zero (Le., lowered in mag- nitude). At approximately 4X 10” ions/cm2, AVr had exceeded 1.9V, a shift sufficient to cause the units fabricated in this experiment t o become depletion mode (i.e., t o be “on” with zero gate voltage). ThEecond cu rve (right ordinate scale) records the increase in ~ / I D , Y s observed as a function of increasing ion (dose. The parameter 4%~ is used because i t is proportional to the pinchoff voltage, but may be more conveniently measured with a curve tracer than the la tx[ lDs=K’(TV/L) V p 2 for zero gate bias). I t may be seen that l / I ~ s s is also proportional to the ion dose.

Fig. 2 shows the square root of the drain-to-source current 4% as a function of the gate-to-source voltage V G for the silicon-gate transistors with different implanted doses. I t was found that as the dose goes up, the lines move to higher current level, but the slope remains unchanged. I t may be concluded that the ion implantation under this condition and dose range has little effect on the trans- conductance of the devices.

EFFECTIVE DOPING CONCENTRATIOX ON AN IM:?LANTED CHANiEL The effective doping concentrat.ion on the channel after ion im-

plantation can be derived theoretically from pinchoff voltage, and is plotted in Fig. 3. A n n-type silicon substrate having an initial im- purity concentration of 2 x 10’6 ions/cm3 becomles converted in the channel to p-type at an implanted boron dose of about 1.9X10I1 ions/cm2 a t 44 keV.

SUMMARY AND CONCLUSION We have described a straightforward process by which hIOS de-

vices may be fabricated that possess the desirable features of both silicon-gate and ion-implantation technologies. ’The process allows