ADC Power Scaling

8/2/2019 ADC Power Scaling

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ADC Power Scaling: Design Issues

Amit Tripathi

Faculty of Deptt. Of EN

NIET,Gr. Noida


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Motivation for Power scaling

Increased portability

Demands low power design


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Power scaling with samplingfrequency

ADCs that have a power which reduceswith sampling rate can significantly reducemanufacturer and customer costs.

A single power scaleable ADC can beused by a manufacturer to target multipleapplications with different performance

requirements saving development costs,and reducing time to market.


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(2 )( )ENOB

s

PowerFOM f


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Digital Power

Rp

Rp

Ccycle DDE QV

EP Ef

T

2

VDDP CV f

Digital circuits only require power to

charge/discharge the load capacitance to the

final logic level. For a full cycle from zero to

one then back zero; Q = CVDD

is transferred

f r o m V D D t o g r o u n d i n F i g . 1

Fig.1


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Analog Power

Panalog= IVFor analog power scaling we have tomade voltage and/or current as functions

of the sampling frequei.e P(fs)=i(fs)V(fs)

supply voltage scaling leads to move saturated device into triode region

reduced signal swing

significantly reduces ADC SNR

..Hence voltage scaling can only provide a minimal power-speed

dependency


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Analog powercontinue.

Bais current scaling

->opamp unity gain frequency is given by

CloadRoutgm

Fig.2: Simplified small signal opamp model

mta

load

g

C 1

2at ox Dload

WC IC L

Reduction of bias current with samplingFrequency reduces the bandwidth of opampThis may keep FOM constant.

According to square law equationAs transistor Drain current reducesVGS->Vt

2 DGS t

IV VWk

L

0limDI GS tV V

As VGS

tends to Vtchannel region below the gate oxide become less inverted

And this drive the transistor in weak inversion region


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Weak inversion operation oftransistor

Weak inversion operation is commonly used inanalog circuits that require very low powerconsumption

gm/ID ratio is a maximum A significant disadvantage of operation in the

weak inversion region however is the lack ofcontinuous, easy to manipulate models of

transistor operation in weak inversion.


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Weak inversion model

A popular model (EKV),which describes transistoroperation in both strong and weak inversion regions. Inthe EKV transistor model, drain source current is givenas the difference between a forward current, and a

reverse current.

IDS=IF-IR

Where the forward current depends on gate and sourcevoltages, and the reverse current depends on gate and

drain voltages. For an NMOS transistor the currentcomponents can be expressed as

( )( )

22

( )1

G TO S D

T

V V V

U

F R S

WI I log e

L


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Weak inversion modelcontinue

If the forward current is much larger thanthe reverse current

----Transistor is saturated

If IF is comparable to IR----Transistor is in the ohmic or triode region


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Weak inversion issues - mismatch

Transistor operation in weak inversion leads to increasedcurrent mismatch

Stage

2

Stage

1

W/L W/LW/L

Stagen

W/L

0.925uA 1.075uA 0.98uA

1uA

Stage

2

Stage

1

W/L W/LW/L

Stage

n

W/L

1uA 1.16uA 1.06uA

1.08uA

Bais power increased to

meet desired bandwidth3 =15%

ID

Fig.3 Illustration of impact of mismatched current sources


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Current scaling-Bias pointsensitivity

2 ( )GS S

GS

dIk V V

dV

g t s

T

V V V

nU

GS

dI

edV

In strong inversion In weak inversion

if a transistor is acting as a current source to an opamp is in weakinversion,a small variation of gate-source voltage on the transistordue to (e.g.) noise coupling from a nearby digital circuit, thermal

fluctuations of a resistor acting as a reference current source, orthreshold mismatch, will cause the unity gain frequency of the opamp,hence accuracy of the ADC to fluctuate significantly


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Current scaling-IR Drop

2m ox DW

A g R R C IL

Fig. 4: differential pair with RC load Fig. 5: differential pair with active load

For RC load

For active load2 21D ox

m ds

D D

W W

Cox I CL LA g rI I


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current mirror transistors have a high sensitivity to bias

node fluctuations, thus it is possible that even a small IRdrop of a few mV between mirror transistor supplyvoltages (due to e.g. physical separation on a larger chip)could cause significant current mismatch hence

potentially reduced performance

M2

Vg1

Vg2Vg2

Vg1M1

M4

M3

Veff3=Vg1-VSS-Vt


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Conclusion

This Paper discussed the dependency of power withsampling rate for analog and digital systems. Currentscaling was shown as common technique to reduceanalog power with sampling rate.

It was shown that current scaling drives MOStransistors deep into the weak inversion region forextended reductions in sampling rate

Where due to less accurate models, circuitdesign/fabrication could take several iterations to meetdesired performance.

Increased mismatch, bias point sensitivity, and IR dropswere also shown as limiting factors to the extent to whichcurrent scaling can be used to reduce analog power


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ADC Power Scaling