Achievements and Results Annual Report 2004 › content › dam › isit › de › ... · Itzehoe (SMI). The outlines of a contract have been drafted that will enable SMI and ISIT

Achievements and ResultsAnnual Report 2004

Surface micromachined polysiliconstructure for inertial sensing.

Preface............................................ 7

Profile of the Institute

Brief Portrait..................................... 12

Main Fields of Activity....................... 14

Equipment....................................... 22

Offers for Research and Service

Spectrum of Services ........................23

Customers....................................... 24

Innovation Catalogue....................... 26

Representative Figures .................. 28

The Fraunhofer-Gesellschaft at a Glance ..................................... 30

Representative Results of Work

IC-TechnologyPower Balling, Assembly for Power Devices.................................. 32

Wafer Level Chip Size PackagingProduction at Itzehoe........................34

MEMS Fabrication by Using CMP.......36

Microsystems Technology and IC-DesignProjection Mask-Less Lithography:MEMS-Technology for a ProgrammableAperture Plate System.......................42

Microscanners for Mobile LaserProjection Displays............................ 46

Development of a New Sputter Processfor the Deposition of PiezoelectricLayers for MEMS-Actuators...............48

MIMOSA: Microsystems Platform for Mobile Services and Applications.. 52

Surface Micromachining ProcessPlatform for the Development of Inertial Measurement Units (IMU) in Automotive Application....... 54

Training Course for MEMS Design..... 56

Biotechnical MicrosystemsPathogen Detection on Electrochemical Microarrays.............. 58

Module IntegrationHigh Vacuum Wafer BondingTechnology........................................ 60

Studies on Underfilling Componentswith Area Array Solder Terminals in Surface Mount Technology............ 64

Lead-Free Soldering for RoHS Compliance– Challenge, Task and Chance............. 68

Integrated Power SystemsInstallation and Ramping-up of a Lithium-Polymer RechargeableBattery Production Line.....................72

Important Names, Data, Events

Lecturing Assignments at Universities................................... 76

Memberships in Coordinationboards andCommittees...................................... 76

Distinctions....................................... 76

Cooperation with Institutes and Universities................. 77

Trade Fairs and Exhibitions................ 77

Miscellaneous Events........................ 77

Scientific Publications

Journal Papers and Contributions to Conferences........... 78

Talks and Poster Presentations........... 78

Diploma Theses................................ 80

General View on Projects ............. 81

Patents............................................ 82

Contact and Further Information...................................... 83

Imprint............................................. 83

Achievements and ResultsAnnual Report 2004

Electrical biochips commonly deve-loped by Siemens, Infineon andFraunhofer ISIT.With those chips bacteria, viruses,toxins or antibiotica can be detectedrapidly and easily.

calls for an exceptional degree of stability in the engineering parameters, not only with respect to electrical properties but also in mechanical terms, and thus represents a huge technological challenge. In this context wewould like to thank the BMBF (nanoelectronicsdepartment) for their technical and financial support.

A further important milestone in the realizationof the ISIT’s concept for developing closer linksbetween R&D and manufacturing was reached in2004 in cooperation with SILICON ManufacturingItzehoe (SMI). The outlines of a contract havebeen drafted that will enable SMI and ISIT to collaborate in the field of microsystems engineering in much the same way as Vishay and ISIT now work together in the field of power electronics. In other words, ISIT willconcentrate on the development of new

2004 was a year of noteworthy decisions for the further development of Itzehoe as a high-tech research and manufacturing address.

By far the most important of these was thedecision by Vishay/Siliconix to build their firstproduction line for power components on 8” (200-mm) wafers in Itzehoe, after having considered a number of other sites outsideGermany. This decision confirms the high qualityof the infrastructure in Itzehoe and the excellent skills and motivation of the workforceat Vishay Semiconductor Itzehoe and the staff of Fraunhofer ISIT.

These facility modernization plans were able togo ahead because Vishay and ISIT, in consultationwith the BMBF, were quickly able to agree onterms for the renewal of their cooperation agree-ment. A contract has been negotiated for a period of ten years, following on from the present cooperation agreement which is due to expire in 2007. This safeguards the futureof the Itzehoe site, with the known example of cooperation between a research laboratorysite and manufacturers, for many years to come.

Over the next three years, Vishay and ISIT intend to invest around D 100 million in order toupgrade their manufacturing plant to deal with the larger-diameter wafers, and to increaseproduction capacity. The workforce will grow by around 100 employees. Vishay will carry wellover half of the necessary investment, and alsoprovide the most new jobs. It is appropriate at this point to express our very grateful thanksto the Schleswig-Holstein Ministry of Economy,and most particularly to Professor Rohwer andDr. Ross, who have given us their support inmany ways. With these new facilities, Itzehoe iswell on the way to becoming the center ofVishay /Siliconix’s R&D activities in the field of newpower components.

The transition to the new wafer size makesItzehoe a world pioneer in the development andmanufacturing of power electronics and microsystems components. – There are nowhereelse any significant activities using 8” wafers inthese particular areas of microengineering. The production of microsystems on 8” wafers

Fraunhofer ISIT Achievements and Results – Annual Report 2004 7

Preface

Dr. Peter Merz was honoured with the MAZ Award 2004 for the development of a new process for themanufacturing of microoptical lenses.

packaging, has grown out of the teething stageand is now operating as a stable, high-yield production line, as demonstrated by the risingproduction volume. Chip-size packaging is anadvanced technology that allows high-scale-integrated microelectronic circuits and microsystemcomponents to be assembled and connected inextremely small packages, not much bigger thanthe silicon chip itself. Here too, the transition to 8” wafers represents an important milestone.

The expertise built up at the institute over the last 10 years, especially through its policy of creating close links between R&D and manufacturing industry, has started to arouse the interest of a wider public and is earning a certain acclaim. The most outstanding honorwas the award of the German President’s Future Prize for Technology and Innovation to

technologies and components while SMI focuseson the appropriate production engineering and quality assurance. Owing to the fact thatISIT’s clean room for back-end microsystemsengineering is stretched to the limits of its capacity – in preparation to the transition to 8”wafers and provide space for a large number of projects for external customers – SMI and ISIT intend to construct and operatetheir own joint clean room module on SMI’s premises, equipped with the necessary 8” equipment. Itzehoe will then possess an optimi-zed infrastructure for microsystems engineering,enabling customers to be offered end-to-end service from development to every scale of production.

The first major collaborative project between SMI and ISIT, the production line for chip-size

Preface

8 Fraunhofer ISIT Achievements and Results – Annual Report 2004

ISIT Organigram

MANAGEMENT

Managing DirectorProf. Dr. Heuberger

Member of Institute ManagementDr. Windbracke

1

IC-Technology

FriedrichDr. Zwicker

SecretaryGreiff, Rosemann,

Wiegandt

Design / SimulationEichholz

2

MicrosystemTechnology

Dr. WagnerDr. Reimer

Administration

Finder

IT

Tönnies

TASKS

Planning of R&D areas in cooperation withUniversities: Dr. BerntMarketing: Dr. Dudde

Public Relations: WackerBuilding and Installation: Dr. Krullmann

Quality Management: Dr. Petzold

4

Packaging,Module

Integration

Pape

3

BiotechnicalSystems

Dr. Hintsche

5

IntegratedPower Systems

Dr. Gulde

On November 11, 2004,Dr. Walter Gumbrecht,Dr. Rainer Hintsche and Dr. Roland Thewes(from left to right)have been honouredby BundespräsidentHorst Köhler in Berlinwith the “DeutscherZukunftspreis”,Germany’s prestigiousFuture Award for Innovation andTechnology.

Dr. Rainer Hintschewith Prof. Hans-JörgBullinger, President ofthe Fraunhofer-Gesellschaft in Berlin.

Dr. Rainer Hintsche of ISIT and his colleagues Dr. Walter Gumbrecht of Siemens and Dr. Roland Thewes of Infineon Technologies. This prize, worth D 250,000, is one of the most prestigious awards for scientists in theGerman-speaking community. The three researchers received the award for their work on electric biochip technology. Dr. Hintsche and his team at ISIT have spent almost 10 yearsdeveloping the fundamental scientific basis forapplications of electric biochip technology. Out of this work, and in collaboration with ateam of industrial partners headed by WalterGumbrecht and Roland Thewes, has emerged a platform that will enable electric biochip technology to be implemented on an industrialscale. The key to the project’s success has been its interdisciplinary approach, which brings together electrochemistry and biochemistry on the one hand with the universe of microstructuresand silicon-chip technology on the other. Thenew technology has now fully entered the phaseof transfer to manufacturing and deployment in a production environment.

ISIT has succeeded in launching a number ofjoint projects with future users to develop application-specific solutions using biochips intest and analysis systems, covering a whole range of molecules from DNA/RNA to proteinsand haptens. The fields of application are diverse, and include monitoring for biologicaltoxins, safety engineering, food processing, biotechnology and medical devices.


One particular success was the development of a detection system for biowarfare agents,which represents one of the main focuses of thenew working field of “homeland security”. ISIT has agreed on a strategic partnership withthe engineering and defense supply companyDiehl. An initial version of the new test systemhas undergone successful trials at variousGerman army establishments.

Further members of ISIT staff who have beenhonored this year include Dr. Peter Merz, who together with his colleagues Jochen Quenzerand Arne Schulz-Walsemann received the MAZAward for their development of a new processfor manufacturing micro-optical lenses. The MAZ Award is a regionally based innovation prizeawarded by MAZ level One, a financial servicesprovider for young startup ventures, in consortwith two north-German competence networks,Hanse-NanoTec and Hanse-Photonik e. V. Thisprize recompenses research papers that demonstrate the greatest potential for the creation of new business opportunities in the fields of nanotechnology and optical technologies in northern Germany.

The process developed by Peter Merz and his colleagues – called glass flow process – enablesthe manufacturing of microlenses at low cost and high volume in almost any required size.There is a huge demand for such lenses. They are used in telecommunications, for example, to feed optical signals into the fibers of optical cables. But miniaturized lensesare also required in security systems such as fingerprint sensors – for credit card authenticationor car immobilization devices, etc.

ISIT meanwhile possesses the largest capacity and greatest expertise in microsystems development in Germany. This is clearly illustrated by the two projects that won awardsin 2004, but also in a multitude of other scientificadvances that have emerged from the institute.In the context of its industrial contract researchwork in recent years, ISIT has built up a stablecustomer base of more than 350 companies,including around 50 located in Schleswig-Holstein. In 2004, the foundations have been laidfor further expansion of the local research infrastructure that will assure its viability well into the future.

Preface


Open Day at the High-Tech location Itzehoe: Approximately 700 visitors were getting information about the actual main focus of work and research at the Fraunhofer ISIT, Vishay, the TF ofthe CAU-Kiel, SMI, Solid Energy, Condias and the IZET.

Planned commercial application of the electricalbiochip technology. The chipcard, developedby Siemens, contains a biochip, that can for example be used for the rapid testing ofblood samples.

of activity and engaged in lively discussions with the members of staff present. The visitorswere visibly impressed by the enthusiasm and dedication of the people they met.

These achievements are the result of the persevering efforts and hard work of the entirestaff of ISIT. I would therefore like to thank allemployees for their excellent performance andtheir willingness to take up all these challenges.They are responsible for the Institute’s success.


Close cooperation between research orga-nizations and manufacturing companies is one ofthe unique selling points supporting Itzehoe’sclaim to excellence as a favored destination forinvestments in the high-technology sector. This was also a good reason for organizing apublic open day in connection with the “Year of Technology” initiative launched by the BMBF. The purpose of this event was to give visitors a comprehensive picture of thenew ways in which research and industry can work together, and to explain why micro-electronics and microsystems engineering are of such continued importance to our futurelives. The day was a great success. In a variedseries of events, including video presentationsand guided tours of research facilities and company sites, the members of the Itzehoe high-tech community, including ISIT, Vishay, SMI, the faculty of engineering at the University of Kiel, Sollith Batteries, Condiasand the Itzehoe innovation center IZET, demonstrated their work. Some 700 visitors –school classes, students, friends and family of employees, and members of the generalpublic – came to find out more about the latest developments in the participants’ areas

Anton Heuberger

Together with Vishay Semiconductor ItzehoeGmbH, the institute operates a professionalsemiconductor production line which is up-to-date in all required quality certifications.The line is used not only for producingmicroelectronic components (PowerMOS) andmicrosystems, but also for R&D projects aimed atdeveloping new components and technologicalprocesses. An ISO-9001-certified qualitymanagement system serves as the basis for thedevelopment, qualification and production ofmicro-engineered components.

Other groups at ISIT carry out work on assemblyand packaging techniques for microsystems andsensors, analyze the quality and reliability ofelectronic components, and develop advancedpower-supply components for electronic systems.

The institute employs a staff of around 150.

Fraunhofer ISITResearch and Production at one Location

The Fraunhofer-Institut für Siliziumtechnologie(ISIT) develops and manufactures components inmicroelectronics and microsystems technology,from the design phase – including systemsimulation – to prototyping and fabrication ofsamples, up to series production. Thoughcomponents such as valves and deflection mirrors manufactured by Fraunhofer ISIT oftenmeasure just a fraction of a millimeter in size,their range of applicability is anything but small:the devices are implemented in areas as diverseas medicine, environmental and traffic engineering, communication systems, automotiveindustry, and mechanical engineering. Workingunder contract, ISIT develops these types ofcomponents in accordance with customerrequirements, also creating the application-specific integrated circuits (ASICs) needed for the operation of sensors and actuators. Includedin this service is the integration into the overallmicrosystem using miniaturized assembly andinterconnection technology.

Brief Portrait


Wafer with electrical biochips.

Main Fields of Activity

Microsystems Technology (MEMS) and IC Design

The work performed at the institute focuses predominantly on microsystems technology, anarea which ISIT pioneered in Germany. For over20 years ISIT scientists have been working on thedevelopment of micromechanical sensors andactuators, micro-optic and fluidic components,and components for radio-frequency applications (RF-MEMS). Their work in this area also includes integrating these componentswith microelectronics to create novel systems. A multitude of components and systems haveoriginated at ISIT.

The current emphasis in the area of sensor technology is on inertial sensor technology(motion, inclination, acceleration, angular rate,IMU) and pressure, temperature and flow sensors (particularly gas flow), all with integrated electro-nics (ASICs). The development of customizedintegration concepts, ranging from simple, cost-effective assembly in a common package to complete monolithic integration, representsthe core of ISIT’s offerings in this area. Oneintegration technique that customers may findparticularly valuable is the ability to mount a

microsystem on the surface of a fully processedASIC wafer using a low-temperature processsuch as electroplating.

Among the key fluidic components created atISIT are pneumatic valves, bi-stable fluid valves,sensor-controlled automatic microdosing devices,and micropumps, all of which can also beemployed in Lab-on-Chip systems.

ISIT also develops optical microsystems, primarilyfor optical communication and instrumentation.Examples include micromirrors for laser displays,laser scanners and digital light modulators, andpassive optical elements such as refractive anddiffractive lenses, prisms, or aperture systems.

Radio-frequency microsystems developed at ISIT, designed primarily for use in wireless communication devices, include microrelays,high-frequency switches and tunable capacitors.

Systems which utilize actuators need to be ableto generate the forces necessary for the device tointeract with its environment. In order to meet



Detail of a programmableaperture platesystem for mask less projectionlithography.

Different microoptical lenses by injection moldingin polycarbonate.


the special requirements of microscopically smallsystems, ISIT implements electrostatic, thermaland – more recently – piezoelectric power.

The ISIT approach enables the institute to offerits customers all of these components as prototypes and also to manufacture them inseries according to the customer’s specific needs,utilizing the institute’s in-house semiconductorproduction line wherever possible. The servicesprovided also include application-specific micro-system packaging at the wafer level, usingadvanced wafer bonding methods.

Should a customer’s requirements fall outside thescope of the institute’s technological capabilities,ISIT can utilize a European network to gainaccess to other manufacturers and processes, likeproduction lines at Bosch, SensoNor, HL Planar,ST and Tronic’s. ISIT organizes the production asa foundry service for interested customers. Andwith the settlement of SMI GmbH in Itzehoe, theinstitute has gained a key partner for producingmicrosystems and related components as a foundry service under customer contract.

One of the prerequisites for developing originalmicrosystems and microelectronic components isa highly capable circuit design group. The staff atISIT are specialists in the design of analog/digitalcircuits, which enable the electronic analysis ofsignals from silicon sensors. The circuit designersat ISIT also devise micromechanical and microoptic elements and test their functionality inadvance using FEM simulation. To carry out theseassignments, the team has modified commercialdesign tools to meet the specialized challengesof microsystems technology.

Microsystems TechnolgyDr. Bernd Wagner+49 (0) 4821 / 17 - [email protected]

Dr. Klaus Reimer+49 (0) 4821 / 17 - [email protected]

IC DesignJörg Eichholz+49 (0) 4821 / 17 - [email protected]

Foundry ServiceDr. Ralf Dudde+49 (0) 4821 / 17 - [email protected]

Wolfgang Pilz+49 (0) 4821 / 17 - [email protected]

Concept for a tirepressure sensor.

Microsensor structure forinertial measurements.

Principle of a two axesmicromirror chip (left).

Mobile laser projectionsdisplays are possibleapplications for MEMS-scanners (right).


IC Technology and Power Electronics

The power electronics and integrated circuitsgroup develops and manufactures active integrated circuits as well as discrete passivecomponents. Among the active components the main concern lies on power devices such as smart power chips, IGBTs, bi-directional components, PowerMOS circuits and diodes.Thereby ISIT primarily uses Vishay’s customized,individual production sequences. Additional support for work in this area is provided by anarray of modified tools for simulation, design and testing. ISIT also benefits from years of experience in the design and construction ofCMOS circuits.

The passive components developed and fabricatedat ISIT are primarily chip capacitors, precisionresistors and inductors. Materials developmentand the integration of new materials and alloysinto existing manufacturing processes play animportant role in the development process.

ISIT develops individual processes, process modules and complete process flows for diverseapplications. The institute also offers customer-

specific silicon components processing in small tomedium-sized batches on the basis of a qualifiedsemiconductor process technology.

To support the development of new semiconductorproduction techniques, production equipment of particular interest is selected for testing and optimization by the ISIT staff. This practice provides the institute with specialized expertise inchallenges related to etching, deposition, litho-graphy, and planarization methods. Planarizationusing chemical-mechanical polishing (CMP) inparticular is a key technology for manufacturingadvanced integrated circuits and microsystems.

The intensive work done by ISIT in this area issupported by a corresponding infrastructure: The institute’s CMP application lab is equippedwith CMP cluster tools, single- and double-sidedpolishers and post-CMP cleaning equipment forwafers with 100 to 300 mm in diameter. TheCMP group at ISIT works in close relationship toPeter Wolters Surface Technologies GmbH sincemany years, as well as other semiconductor fabrication equipment manufacturers, producers


Power balling for IGBTs. High current implanterin the ISIT cleanroom.


Peter Wolters HT-Cube, a highthroughput CMP cluster for 300 mmwafers, small pictures details:

a) handling robot,b) wafer transfer,c) polishing table.

Wafer with different balledpower devices.

IC Technology and Power ElectronicsDetlef Friedrich+49 (0) 4821 / 17 - [email protected]

CMPDr. Gerfried Zwicker+49 (0) 4821 / 17 - [email protected]

of consumables, CMP users and chip and wafermanufacturers.

The CMP group’s work encompasses the following areas:• Testing of CMP systems and CMP cleaning

equipment • Development of CMP processes for

- Dielectrics (SiO2, TEOS, BPSG, low-k, etc.) - Metals (W, Cu, Ni, etc.) - Silicon (wafers, poly-Si)

• Testing of slurries and pads for CMP• Post-CMP cleaning• CMP-related metrology• Implementation of customer-specific polishing

processes for ICs and microsystems

a)

b) c)


Biotechnical Microsystems

ISIT is worldwide leading in electrical biochiptechnology, and is holding around 20 patents inthe area. The electrical biochips offer intrinsicadvantages vs. optical biochips because of directminiaturization and transmission of responses ofbiochemical reactions into computing networks.Employing new ultramicroelectrodes and integrated reference and auxiliary electrodes theconstruction enables powerful sensor microarrays and the use of ultra-sensitive, ultra-selectivemeasurement techniques, such as “redox recycling.” In combination with microfluidic

components and integrated electronics, theseelectrical micro arrays represent the fastest andmost cost-effective basis for mobile analysissystems, which can be used to identify and quantify DNA, RNA, proteins and haptens.

Those electrical micro arrays, which are packagedinto proprietary “eBio-Chip-Sticks” are useful to detect a variety of analytes simultaneously. ISIT works closely with the Itzehoe based companyeBiochip Systems GmbH (www.ebiochip.com) ,an ISIT spin-off, to facilitate the marketing ofthese new technologies. Both together developeda variety of smart and portable instruments, froma low end device for education and demonstrationto the high end fully automated micro array analyzer. Demonstrating very competititve appli-cations as the identification and quantification ofprotein and pathogenic biowarfare agents or theantibiotics in raw milk the platform of electricalbiochip technology is successfully used in severallabs in Europe and in EU granted projects.

Dr. Rainer Hintsche+ 49 (0) 4821 / 17 - [email protected]

A new generation of a fully automatic eBiochip measuring systemfor the detection of biological agents.

Layouts for the “Lab on a Chip“. Electrical Silicon biochip.

Packaging Technology for Microelectronics and Microsystems

The assembly and interconnection technologygroup offers to customers a broad range of services,including precision assembly of microstructuredcomponents and development and qualificationof customer-specific packaging. Work in this areaincludes hermeticity and material compatibilitytests for assemblies that have to work in aggressive environmental conditions, e.g., analysis of microsystem packages intended for in vivo use in medical technology.

Another focal area is miniaturization of chip andsensor assemblies and packages, which includesdirect assembly of bare silicon chips. The institutepossesses capabilities in all of the essential tech-nical stages for chip-on-board (COB) technology,from designing the circuit boards to qualifiedCOB assemblies. The bare ICs and microsensorsare mounted using the Chip & Wire or Flip-Chiptechniques.

The group also develops processes for assemblingand packaging chips and sensors/actuators whilestill on the wafer. Due to the increasing globaltrend among chip manufacturers to implementthis special packaging process, Wafer LevelPackaging (WLP) – now considered the assemblytechnique of the future – has become a centralfocus of the group’s work. WLP technology canalso be applied for packaging sensors undervacuum, such as angular rate or acceleration sensors. ISIT has successfully integrated thin filmgetter layers for high-Q microresonators withimproved vacuum lifetime.

The institute is active in this area not only as atechnology developer, but also as a manufacturerof assemblies for its customers using the available Chip-Size-Packaging production line.

The group also develops ultra-thin electronicassemblies, which involves stacked mounting flexible silicon chips as thin as 50 µm on flexiblesubstrates.

These techniques will ultimately lead to furtherminiaturization in existing systems, such as lap-tops, hand held PCs or mobile phones, but willalso enable the development of new productslike intelligent flexible product labels or smartclothes.

Karin Pape+ 49 (0) 4821 / 17 - [email protected]

Wolfgang Reinert+49 (0) 4821 / 17 - [email protected]

Application of solderspheres for wafer levelCSP manufacturing in the SMI / ISIT production line.

Cap wafer with individual getters for high vacuum sensor encapsulation on wafer level.

Detail of a testchip with 5000 galvanic Au contacts for evaluation of high precisionflip chip bonder.

Standard testchip for otimizationof flip chip solder processes.



Quality and Reliability of Electronic Assemblies

Quality evaluation – in particular for the solde-ring work done in pre-production, pilot and mainseries lots – represents a continuous challengefor ISIT, for example whenever new technologiessuch as lead-free soldering are introduced, whenincreased error rates are discovered, or if theinstitute desires to achieve competitive advanta-ges through continual product improvement. Toreveal potential weak points, ISIT employs bothdestructive and non-destructive analysis methods,such as x-ray irradiation. Working from a requirements matrix, ISIT scientists also evaluatelong-term behavior of lead-free and lead-containing assemblies alike. They then formulateprognoses on the basis of model calculations,environmental and time-lapse load tests, and failure analysis.

In anticipation of a conversion to lead-free electronics manufacturing, Fraunhofer ISIT isundertaking design, material selection andprocess modification projects. To effect a furtheroptimization of manufacturing processes, theinstitute applies process models and producessamples on industry-compatible equipment. Thegroup also addresses issues related to thermalmanagement and reliability for customer-specificpower modules.

In addition to these technological activities, thegroup regularly holds training sessions, includingmulti-day classes, at the institute or at companysite.

Karin Pape+ 49 (0) 4821 / 17 - [email protected]

Dr. Thomas Ahrens+ 49 (0) 4821 / 17 - [email protected]

Intermetallic phase particle inside a solder jointafter deep etching of tin.

Evaluation of the integrity of different copper layers. Copper has been etched:Micro via in the build-up layer of a printedcircuit board (top).Printed through hole with tin lead solder ina section view horizontal through an innercopper layer (bottom).


The base material for ISIT’s Lithium batteryproduction process is a foil material. This allowsbatteries to be made in a much greater variety of shapes and sizes, thus significantly diversifyingthe range of possible applications.

ISIT offers the following services in this area: deve-lopment, fabrication and small series productionof customer-specific battery formats (ranging insize from microsystems to laptops) in a broad rangeof available ampere-hour ratings, with variousforms of housings and materials (e.g. plastic orTitanium). Following the preparation of samples,ISIT supports the customer in the transition toseries production. The institute also provides application-specific material selection of variouscompounds for cathodes (e.g. Lithium Cobaltite,Lithium Iron Phosphate) and anodes (Graphite,Lithium Titanate, etc.) to ensure optimal conformityto the application requirements (e.g., power density,cycle stability, capacity, product life cycle, self-dis-charge rate.) ISIT has built an initial production linefor an industrial-scale production process.

Integrated Power Systems

The growing use of a wide array of mobileelectronic devices is generating an increaseddemand for rechargeable batteries that arelighter, yet provide increased power density.Along with an exceptional power capacity, consumers expect long battery lifetime, increasedsafety and a higher degree of environmentalcompatibility. A new lithium rechargeable batterydesign developed by ISIT over the last few years – for which the institute has submitted a patent application – is capable of meetingthese demands. This new concept, which features solid-state electrolytes, affords the samehigh power density typical of Lithium-ion rechargeables, but because the materials used in the new battery are inert, it does not need the complicated hermetic packaging technologyrequired with conventional Lithium-ion batteries,which contain liquid electrolytes. The battery needs only a metallized plastic foilpackaging to make it air- and moisture-tight,resulting in a lower overall weight for the finished product.

Dr. Peter Gulde+ 49 (0) 4821 / 17 - [email protected]

RechargeableLithium poly-

mer batteryfor hearing

aids.Bottom:

battery body.

Lithium polymer battery production

line – control of electrolyte

dispenser unit.

Lithium polymer battery production line – electrical

test station.



Facilities and Equipment

In terms of both space and technical capabilities,the facilities at Fraunhofer ISIT provide an idealenvironment for research & development work aswell as production. In addition to its 150-mm sili-con technology line and 2500 m2 of clean-roomspace, the institute has a further 450 m2 ofclean-room area (class 100) for specific microsy-stems engineering processes, including: wet-etching processes, high-rate plasma etching,

deposition of non-IC-compatible materials, litho-graphy with thick resist layers, gray-scale litho-graphy, electroplating, microshaping and waferbonding. Further 200 m2 clean-room (class 10-100) is equipped for chemical-mechanical polis-hing (CMP) and post-CMP cleaning. ISIT alsooffers a diverse selection of labs (1500 m2) thatare utilized by working groups for the develop-ment of chemical, biological and thermal proces-ses, electrical and mechanical component cha-racterization, and for assembly and interconnec-tion technology. A spin-off arising from the workin assembly and interconnection technology – aCSP (Chip-Size Packaging) production line withan annual capacity of 100,000 wafers – was builtin the ISIT clean rooms in collaboration with SMIGmbH (Silicon Manufacturing Itzehoe). The line isjointly operated by ISIT and SMI. The ISIT facilityalso operates a pilot production line for Lithium-polymer rechargeable batteries with power capa-cities of up to several ampere-hours.

ISIT cleanroom: lithography area (left), diffusion furnace area (bottom).


Spectrum of Services

The institute makes its range of services availableto companies representing a wide variety ofbranches, including medical technology, communication systems, automotive industry,and industrial electronics, just to name a few.After industrial customers specify necessaryrequirements of the components and systems,ISIT engineers work closely with them to design,simulate and produce the components, systemsand manufacturing processes. In this context, ISITfollows the technology platforms concept, whichentails defining standard process flows that canbe used to manufacture a large group ofcomponents simply by varying certain designparameters. Applying this modular technologyconcept is the optimal way to ensure that ISITcontinues to offer competitive prices to itscustomers.

ISIT services have attractive implications for small-and medium-sized enterprises, which cantake advantage of the institute’s facilities andexpertise in realizing technological innovationsup to products.


ISIT-process demonstration for wafer level CSP manufacturing at the SMT 2004, Nürnberg

Wafer loading into a Semitool spray clean tool.


CustomersISIT cooperates with companies of different sectors and sizes. In the following some companies are presented as a reference:

Adaptive Photonics,Hamburg

Alcatel VacuumTechnology,Annecy, France

Alma, Lyon, France

Amic, Uppsala, Sweden

Andus GmbH, Berlin

ARC Seibersdorf Research GmbH,Wien, Austria

ASE, Seoul, Corea

Atotech DeutschlandGmbH, Berlin

Autoliv GmbH, Elmshorn

Basler VisionTechnologies, Ahrensburg

BDT GmbH & Co. KG,Rottweil

Beru Electronics GmbH,Bretten

Borg Instruments,Remchingen

Bosch, Reutlingen

Bruker Daltonik GmbH,Bremen

Bullith Batteries AG,München

Card Guard, Rehovat, Israel

Cardi plus, Sevilla, Spain

Condias GmbH, Itzehoe

Conti Temic microelectronics GmbH,Nürnberg

DancoTech A/S,Ballerup, Denmark

Danfoss Lighting Controls,Nordborg, Denmark

Danfoss Drives,Graasten, Denmark

Danfoss Silicon PowerGmbH, Schleswig

Datacon,Radfeld/Tirol, Austria

Degussa AG, Hanau

Dekati Oy,Tampere, Finland

Diabem, Barcelona, Spain

Diehl Avionik, Überlingen

Disetronic MedicalSystems AG,Burgdorf, Switzerland

Dräger Systemtechnik,Lübeck

EADS, Ulm

EADS space, Bremen

eBiochip Systems GmbH,Itzehoe

Elektronik ZentrumHersfeld, Bad Hersfeld

Elmos Semiconductor AG,Dortmund

Environics Oy,Mikkeli, Finland

Equicon, Jena

ESCD, Brunsbüttel

ESW-EXTEL SystemsGmbH, Wedel

EVGroup,Schärding, Austria

EZL, Limburg

Flextronics International,Althofen, Austria

FOS Messtechnik GmbH,Schacht-Audorf

Fuba GmbH, Gittelde

Fujitsu SiemensComputers GmbH,Augsburg

GKSS, Geesthacht

GLAD, Geesthacht

Heidenhain, Traunreut

HL Planartechnik GmbH,Dortmund

H. C. Starck, Leverkusen

Hella KG, Lippstadt

ICT, München

IMS, Jena

IMS, Wien, Austria

Infineon Technologies,München

JLS Designs,Somerset, UK

Jungheinrich AG,Norderstedt

Kapsch, Wien, Austria

Kember Assiciates,Bristol, UK

Kerr McGee, Krefeld

KID Systeme, Buxtehude

Kolbenschmidt PierburgAG, Neuss

Kristensen GmbH,Harrislee-Flensburg

Kuhnke GmbH, Malente

Legrant,Limoges, France

LEICA, Jena



Litef, Freiburg

Mair Elektronik GmbH,Neufahrn

Mars, Espoo, Finland

MED – EL,Innsbruck, Austria

Miele & Cie., Gütersloh

Motorola GmbH, Flensburg

MRT – Micro-Resist-Technology, Berlin

Nokia Research Center,Nokia Group,Helsinki, Finland

NU-Tech GmbH,Neumünster

OK Media Disc ServiceGmbH & Co.KG, Nortorf

Osram OptoSemiconductors GmbH,Regensburg

Oticon, A/S,Hellerup, Denmark

PAV Card GmbH, Lütjensee

Philips Semiconductors,Hamburg

Polytec GmbH, Waldbronn

PRETTL Elektronik LübeckGmbH, Lübeck

Procter &, Gamble,Newcastle, UK

Qinetiq Ltd,Worcestershire, UK

Raytheon AnschützGmbH, Kiel

Rehm Anlagenbau GmbH + Co. KG,Blaubeuren-Seissen

Robert Bosch GmbH,Salzgitter

SAES Getters S.p.A.,Lainate/Milan, Italy

Scana HolographyCompany GmbH,Schenefeld

Scanbec Oy, Oulu, Finland

Scanbec GmbH, Halle

Schott, Landshut

SEF GmbH, Scharnebek

SensorDynamics (SD),Lebring, Austria

Sentech InstrumentsGmbH, Berlin

Siemens AG, München

Siemens Mobile, München

Siemens VDO AutomotiveAG, Schwalbach

Siemens VDO, Karben

SMA Regelsysteme GmbH,Niestetal

SMI GmbH, Itzehoe

Smith Detection,Watford, UK

Sollith Batteries GmbH,Itzehoe

Sonion, Lyngby, Denmark

ST Microelectronics,Crolles, France

ST Microelectronics,Mailand, Italy

Still GmbH, Hamburg

SÜSS Microtec AG,Garching

Su unto, Vantaa, Finland

Technolas, München

Technovision GmbH,Feldkirchen

Telefonica,Madrid, Spain

Thales Avionics,Valence, France

Thales,Meudon la Forêt, France

Thales, Paris, France

Trioptics GmbH, Wedel

Tronic´s, Grenoble, France

Vishay, Holon, Israel

Vishay SemiconductorGmbH, Itzehoe

Wabco Fahrzeugbremsen,Hannover

Peter Wolters CMPSysteme GmbH, Rendsburg

Woowon Technology,Corea



Innovation Catalogue

ISIT offers its customers various products and services already developed for marketintroduction. The following table presents a summary of the essential products andservices. Beyond that the utilisation of patents and licences is included in the service.

Product / Service Market Contact Person

Testing of semiconductor Semiconductor equipment Dr. Gerfried Zwickermanufacturing manufacturers + 49 (0) 4821/17-4309equipment [email protected]

Chemical-mechanical Semiconductor device Dr. Gerfried Zwickerpolishing (CMP), manufacturers + 49 (0) 4821/17-4309planarization [email protected]

Wafer polishing, single Si substrates for Dr. Gerfried Zwickerand double side device manufacturers + 49 (0) 4821/17-4309

[email protected]

IC processes Semiconductor industry Detlef FriedrichCMOS, PowerMOS, IGBTs IC-users + 49 (0) 4821/17-4301

[email protected]

Single processes and Semiconductor industry Detlef Friedrichprocess module semiconductor equipment + 49 (0) 4821/17-4301development manufacturers [email protected]

Customer specific Semiconductor industry Detlef Friedrichprocessing semiconductor equipment + 49 (0) 4821/17-4301

manufacturers [email protected]

Microsystem Products Electronic industry Dr. Ralf Dudde+ 49 (0) 4821/[email protected]

Plasma source Semiconductor equipment Christoph Huthdevelopment manufacturers + 49 (0) 4821/17-4628

[email protected]

Plasma diagnostics Semiconductor equipment Joachim Janesmanufacturers + 49 (0) 4821/17-4604

[email protected]

Etching and deposition Semiconductor industry Joachim Janesprocess control + 49 (0) 4821/17-4604

[email protected]

Ion projection lithography Semiconductor industry Dr. Wilhelm Brüngeropen stencil mask + 49 (0) 4821/17-4228technology and email: [email protected] processes

Inertial sensors Motorvehicle technology, Dr. Bernd Wagnernavigation systems, + 49 (0) 4821/17-4223measurements [email protected]

Design for commercial Micro sensors and Dr. Bernd WagnerMST processes actuators + 49 (0) 4821/17-4223

[email protected]

Microvalves Analytic, medical technology Hans Joachim Quenzerfor gases and liquids measurement + 49 (0 ) 4821/17-4524

[email protected]

Microoptical Biomedical technology, Ulrich Hofmannscanners and projectors optical measurement industry, + 49 (0) 4821/17-4529

telecommunication [email protected]

Microoptical Optical measurement, Dr. Klaus Reimercomponents + 49 (0) 4821/17-4506

[email protected]

Mastering and replication Microoptics, Dr. Klaus Reimerof micro structures in microfluidics + 49 (0) 4821/17-4506plastic [email protected]


Design and test of Measurement, automatic Jörg Eichholzanalogue and control industry + 49 (0) 4821/17-4213mixed-signal ASICs [email protected]

Design Kits MST foundries Jörg Eichholz+ 49 (0) 4821/[email protected]

RF-MEMS Telecommunication Thomas Lisec+ 49 (0) 4821/[email protected]

MST Design and Measurement, automatic Jörg Eichholzbehavioural modelling control industry + 49 (0) 4821/17-4213

[email protected]

Electrodeposition of Surface micromachining Martin Wittmicrostructures + 49 (0) 4821/17-4541

[email protected]

Digital micromirror devices Communication technology Dr. Klaus Reimer+ 49 (0) 4821/[email protected]

Electrical biochip technology Biotechnology, related electronics, Dr. Rainer Hintsche(proteins, nucleic acids, haptens) microfluidics, environmental analysis, + 49 (0) 4821/17-4221

Si-Chipprocessing, packaging, chip loading [email protected]

Secondary lithium Mobile electronic equipment, Dr. Peter Guldebatteries based on solid medical applications, automotive, + 49 (0) 4821/17-4606state ionic conductors smart cards, labels, tags [email protected]

Battery test service, Mobile electronic equipment Dr. Peter Guldeelectrical parameters, medical applications automotive, + 49 (0) 4821/17-4606climate impact, reliability, quality smart cards, labels, tags [email protected]

Quality and reliability of Microelectronic and Karin Papeelectronic assemblies power electronic industry + 49 (0) 4821/17-4229(http://www.isit.fraunhofer.de) [email protected]

Leadfree / RoHS Electronic industry Dr. Thomas Ahrenstransformation in +49 (0) 4821/17-4605electronic assembly [email protected]

Material and damage Microelectronic and Dr. Thomas Ahrensanalysis power electronic industry + 49 (0) 4821/17-4605

[email protected]

Thermal measurement Microelectronic and Dr. M. H. Poechand simulation power electronic industry + 49 (0) 4821/17-4607

[email protected]

Packaging for microsystems, Microelectronic, sensoric and Karin Papesensors, multichip modules medical industry + 49 (0) 4821/17-4229(http://www.isit.fraunhofer.de) [email protected]

Wafer level packaging, ultra thin Microelectronic, sensoric and Wolfgang ReinertSi packaging and direct chip attach medical industry + 49 (0) 4821/17-4617using flip chip techniques [email protected]

Vacuum wafer bonding Microelectronic, sensoric and Wolfgang Reinerttechnology medical industry + 49 (0) 4821/17-4617

[email protected]

Flow sensors Automotive, fuel cells Dr. Peter Lange+ 49 (0) 4821/[email protected]

Product / Service Market Contact Person


Expenditure

In 2004 the operating expenditure of FraunhoferISIT amounted to kEuro 18.314. Salaries andwages were kEuro 6.438, consumables and othercosts were kEuro 11.876.

Income

The budget was financed by proceeds of projects of industry/industrial federations/smalland medium sized companies amounting tokEuro 13.730, of government/projectsponsors/federal states amounting to kEuro 995and of European Union/others amounting tokEuro 1.354.

Representative Figures

Salaries & wages 35%

Other positions 17%

Subcontracting 13%

Rent, leasing costs 22%

FhG-Allocations 3%

Maintenance 3%

External R&D and license-fee 6%

Consumables 11%

Others 2%

Government/project sponsor 4,8%

Federal State of Schleswig-Holstein 1,4%

European Union 6,4%

Industry 85,4%


Capital Investment

In 2004 the institutional budget of capitalinvestment was kEuro 837. The amount of operating investment was kEuro 721 and projectrelated investments were amounted to kEuro 116.

Staff Development

In 2004, on annnual average the staff constisted of 98 employees. 52 were employedas scientific personnel, 34 as graduated/technicalpersonnel and 12 worked within organisationand administration. 2 scientist, 20 scientificassistents and 5 apprentice supported the staff as external assistance.

555 10 15 20 25 30 35 40 45 500

Scientists

Graduated/technical staff

Administration staff

Scientific assistants

Apperentice

Others

External scientists

OperatingInvestments

Project relatedInvestments

0 500 1000

Project related InvestmentsOperating Investments


The Fraunhofer-Gesellschaft

The Fraunhofer-Gesellschaft undertakes applied research of direct utility to private andpublic enterprise and of wide benefit to society.Its services are solicited by customers andcontractual partners in industry, the service sector and public administration. The organi-zation also accepts commissions and funding from German federal and Länder ministries andgovernment departments to participate in future-oriented research projects with the aim offinding innovative solutions to issues concerningthe industrial economy and society in general.

By developing technological innovations andnovel systems solutions for their customers, the Fraunhofer Institutes help to reinforce thecompetitive strength of the economy in their

local region, and throughout Germany andEurope. Through their work, they aim to promo-te the successful economic development of ourindustrial society, with particular regard for socialwelfare and environmental compatibility.

As an employer, the Fraunhofer-Gesellschaftoffers its staff the opportunity to develop theprofessional and personal skills that will allowthem to take up positions of responsibility within their institute, in other scientific domains,in industry and in society.

At present, the Fraunhofer-Gesellschaft maintains some 80 research units, including 58Fraunhofer Institutes, at over 40 different locations in Germany. The majority of the roughly12,500 staff are qualified scientists and engineers,who work with an annual research budget ofover 1 billion euros. Of this sum, more thang 900 million is generated through contract research. Roughly two thirds of the Fraunhofer-Gesellschaft’s contract research revenue isderived from contracts with industry and frompublicly financed research projects. The remai-ning one third is contributed by the Germanfederal and Länder governments, partly as ameans of enabling the institutes to pursue morefundamental research in areas that are likely tobecome relevant to industry and society in five or ten years’ time.

Affiliated research centers and representativeoffices in Europe, the USA and Asia provide contact with the regions of greatest importanceto present and future scientific progress andeconomic development.

The Fraunhofer-Gesellschaft was founded in1949 and is a recognized non-profit organiza-tion. Its members include well-known companiesand private patrons who help to shape theFraunhofer-Gesellschaft’s research policy andstrategic development.

The organization takes its name from Joseph vonFraunhofer (1787-1826), the illustrious Munichresearcher, inventor and entrepreneur.

The Fraunhofer-Gesellschaft at a Glance

RostockItzehoe

Bremen

Hamburg

Berlin

CottbusTeltow

Golm

Magdeburg

Halle

Dresden

ChemnitzJena

Ilmenau

WürzburgErlangen

Nürnberg

Wertheim

Braunschweig

Hannover

OberhausenDortmund

SchmallenbergDuisburg

AachenSankt Augustin

Euskirchen

Frankfurt

Darmstadt

St. Ingbert

Saarbrücken

Kaiserslautern

PfinztalKarlsruhe

Stuttgart

Freiburg

Efringen–Kirchen

Freisingen

München

Holzkirchen

Paderborn

Locations of the Research Establishment

Representative Results of Work


Power Balling, Assembly for Power Devices

State of the art chip assembly of discrete power devices in power modules is realized by backside soldering on a DCB substrate (direct copper bonding) and frontside wire bonding (figure 1). This type of assembly is well established and reliably offering a goodcost-performance relation for standard power applications.

However, since the performance of powerdevices has been improved continously over thelast years there is a need for improved assemblytechniques, also.

Due to the implementation of trench technologyand ultra thin substrate technique in the powerdevice fabrication process the conducting andswitching behaviour was improved significantly.In order to enable this performance gain to beused on system level also wire bonding should be eliminated for special applications.

For e.g. low voltage PowerMOS transistors withRDSon values in the mOhm range, wire bondresistance can clearly contribute to the overallon-resistance. This drawback can be overcome

by front side solder bump technique of powerdevices. In addition to reduction of the on-resistance the heat transfer out of the powerdevice can be improved also via front side solderbumps. Further, the parasitic wire inductance iseliminated, too.

The technological realisation of a solderablepower device front side is being done by powerballling a specific application of wafer level chipsize packaging. This technique comprises of anunder bump metallisation (UBM) based on Al-NiV-Cu, a BCB (Benzo Cyclobuten) passivation,and solder ball attach with subsequent solderball reflow (figure 2).

Power Balling was applied on Trench IGBT wafersin two different variations. In the first case underbump metallisation was located underneath thesolder balls only, whereas in the second caseUBM was covering the entire actice area in orderto reduce the lateral surface resistance. In thiscase the Cu layer of the UBM can be seen on thechip front side. The gate terminal is located inthe middle of the device with four balls beingplaced (figure 3).

Representative Results of WorkIC-Technology

ceramiccoppersolder

utra thin IGBTsoldercopper on ceramic

base plate

Figure 1:Power device assembly on a DCBsubstrate with frontside wire bonding in a power module.

It can be concluded that high performancepower devices require high performance assemblytechniques.

A possible sandwich type assembly of powerdevices with front side solder bumps is introducedin figure 4. Here, the power devices are solderedwith the backside on a DCB substrate. The frontside solder balls are connected to aspecial interconnect board with feed throughs to the front side. This offers the possibility offurther assembly of e.g. passive components oreven ICs in order to increase the overallintegration density. Instead of using an inter-connect board with feethroughs a simple metalliclead frame is possible also.

In summary, power balling will improve moduleassembly with regard to conducting and swit-ching behaviour of power devices, to overcome thermal constraints and increase overall integra-tion density. Especially for automotive applicationwith high temperature requirements power bal-ling can be an option for advanced powerassembly.


Solder Ball

BCBPassivation

UBM

Power-Chip Solderball

Interconnect Board

CuCu

DCBFigure 4:Sandwich type module assembly for power devices with solder ball frontside.

Figure 3: Application of Power Balling on IGBT wafers. Case 1 with UBM underneath the solder balls only, case 2 with UBM covering the entire active IGBT area.

Figure 2:Principle of wafer level Power Balling.

case 1 case 2

Wafer Level Chip Size Packaging Productionat Itzehoe

Wafer Level Chip Size Packaging (WL-CSP) hasbecome the most attractive packaging techniquefor many applications e.g. CSP for high densityboard assembly, high end IC-Packaging, RF- andpower device assembly and further more.

In the past there was no commercial WL-CSPactivity within Europe, instead industrial bumpingsuppliers were located in Far-East and the USonly. In cooperation with SMI (SemiconductorManufacturing Itzehoe) a joint project was star-ted in 2003 to build up the first European centerfor WL-CSP production in Itzehoe. This decisionwas inspired by the idea to establish advancedpackaging in Germany to compete with highvolume production sites outside Europe.Therefore, competitive prices, short cycle timesand a relevant process portfolio are mandatory.

Within the second half of 2003 lead content andlead free balling processes have been qualified.Since the beginning of 2004 SMI and ISIT startedthe production ramp up with a capacity of50.000 6 inch wafers in the first year (figure 1and figure 2). By equipment invest and processimprovements the maximum line capacity in2005 has reached 100.000 wafers per year.

The production is carried out in a state of the art class 100 back end cleanroom (figure 3).

Currently, the planning of an additional clean-room for 8 inch wafers is in progress in order tooffer WL-CSP for both wafer sizes (6 and 8 inch)in 2006.

Within this cooperation ISIT is responsible for the engineering and process development, maskdesign and layout as well as infrastructure andequipment sustaining. The operating of produc-tion, marketing and customer support is in theresponsibility of SMI.

At this time a portfolio of 4 qualified CSPprocesses for lead content and lead free solderballs can be offered. Further processes forredistribution and fine pitch bumping based onsolder paste printing are near to qualification andwill be released for production in 2005 (figure 4).In a mid term view lead free solder plating forultra fine pitch bumping is envisaged.

In conclusion it has to be highlighed that theproduction and R&D location Itzehoe bringstogether complementary knowledge, experienceand abilities of different companies located atthe Fraunhofer site:

1. the high volume IC-production capability of Vishay Semiconductor Itzehoe GmbH

2. the experience of SMI in operation of production, customer specific product development and marketing

3. the R&D excellence of the Fraunhofer Institute ISIT.

This mix of competences at the same location is an outstanding performance with highattractivity for customers. The availability of the entire value-added chain from developmentup to production is the main advantage whichguarantees short cycles for time to market,competitive costs, easy cummunication andreduced effort for logistic.


20

40

60

80

100

120

140

160

180

200

0

k w

afer

/yea

r

2004 2005 2006

Figure 2:Ramp up of productioncapacity.


Figure 4:Overview on differentbumping techniques.

Productqualification

Ramp up

Process lineimprovement

Increasingthrought put

Redistribution

Solderpaste

20042003 2005

Figure 1:Time schedule

for set up a WL-CSPproduction.

Figure 3:State of the art production cleanroom for WL-CSP.

Under fill

Package Height

Bump Height

Bump Diameter

Bump Pitch

I/O Count

Yes

0.3 - 0.6 mm

20 µm

40 - 120 µm

60 µm

3000

Plated Bumps

Yes

0.3 - 0.8 mm

70 - 150 µm

80 - 220 µm

180 µm

2000

Solder Paste

Applicationdependent

0.6 - 1.1 mm

200 - 400 µm

370 - 500 µm

500 µm

200

Solder Ball


MEMS Fabrication by Using CMP

Since its introduction in the beginning of the90s, chemical-mechanical polishing (CMP) hasdeveloped into a key technology for the produc-tion of microelectronics devices. Starting with theplanarization of inter level dielectrics (ILD), manynew applications of CMP emerged over the yearslike CMP of tungsten for vias, CMP of copper asa replacement for aluminum metallisation, CMPfor shallow trench isolation (STI), or CMP of poly-Si, to name a few. Further use of CMPincludes polishing of Si-wafers or other substra-tes and of hard disk media. Since the mid-90s,CMP also found its way to the fabrication ofMEMS devices.

Micro-Electro Mechanical Systems (MEMS) aremicrostructure products whose fabrication isenabled by microstructure technologies, whichwere mainly developed for microelectronics

production. Other terms also used in this contextare microsystems, micro system technology (MST)or micromechanics. Substrate materials can besilicon, but also glass, ceramics, metals, orothers. Two MEMS-manufacturing techniqueshave been established: bulk micromachining and surface micromachining.

In bulk micromachining, the device is built in the bulk of the substrate by either wet etching(thinning) of the backside of the wafer or bydeep reactive ion etching (DRIE) into the wafer.In surface micromachining, the device is built onthe substrate as free-standing poly-silicon ormetal structures by employing sacrificial layers.

Developed in the research laboratories over thelast 15 years, microsystems and the accompany-ing fabrication techniques have recently begun


Metal contamination

wafer bonding: < 1/cm2

Starting topography

Throughput

Uniformity

Required removal rates

Required removal

Typ. layer thickness

1 – 10 µm

< 10 wafers/h

< 5 %

> 0.5 µm/min

~ 1 – 20 µm

~ 1 - 10 µm

MEMS

max. 1 µm

20 – 60 wafers/h

< 5 %

0.2 – 0.5 µm/min

~ 200 – 1000 nm

< 1000 nm

Microelectronics

alternative:grinding/polishing

Remarks

>>

>>

>

=

<

>>

Required planarity > 100 nm < 50 nm opto: < λ10>

Roughness Ra 10 nm some nm wafer bonding: 0.5 nm>

Pattern width µm - mm < 0.25 µm>>

Dishing > 100 nm < 100 nm large patterns>

Erosion > 100 nm < 100 nm large patterns>

Critical particle rel uncritical < 0.1 µm>

Particle density rel. uncritical < 1/cm2>

uncritical < 1 x 1012/cm2 bonding: fresh surface>>

Wafer size 100 – max. 200 mm 200 – 300 mm>

Substrates Si, metal, glass, ceramic Si, III-V

Layers var. SiO2, poly-Si, Si, var.metals, ceramics, polymers

var. SiO2, Si, poly-Si,W, Cu

Parameters

Table 1: Comparison of CMP requirements for MEMS fabrication vs. microelectronics manufacturing.


to move from the labs into the manufacturingfloors. Typical MEMS products, which are already fabricated in large quantities, includeacceleration sensors, gyroscopes and pressuresensors for the automotive industry. Optical swit-ches for optical fibre networks and RF switchesfor tuneable capacitors, filters or antennas forcell phones are typical telecom applications.Printing heads for ink jet printers or R/W headsfor hard disk drives are used in bulk quantities inoffice applications. Market forecasts predictannual growth rates for MEMS products of about20 % for the next years, exceeding the predictedgrowth rates for microelectronic devices.

In MEMS fabrication, CMP is used for variouspurposes with an emphasis on surface microma-chining. It is used to achieve flat, mirror-likesurfaces for optical devices, it is used to planarizethe topology from previous manufacturing stepsand it is utilised to reduce film roughness formore precise lithography or for wafer bonding.While the critical dimensions of today's mostadvanced microelectronic devices fall below 100nm, the structure dimensions of MEMS devicesare usually larger and lay in the order of 1 – 100µm or even in the millimetre range. The typicalfilm thickness occurring in MEMS can be severalµm, while in microelectronics, the future trendgoes to ever decreasing values, sometimes only a few atomic layers.

In order to optimise a CMP cluster tool for MEMSapplications, we have compared parameters of microelectronics manufacturing with typicalrequirements for MEMS devices, see table 1.

The comparison shows that MEMS-dedicatedCMP tools have to fulfil demands that differ from CMP equipment developed for ULSIdevices. Due to much thicker layers over largerstructures with higher starting topography, therequired material removal by polishing can be upto several ten micrometers. Since removal rates inmicroelectronics are typically below 0.5 µm/min,the CMP processes have to be accelerated inorder to achieve reasonable throughputs ofabout 10 wafers/h, a goal which is relaxed by afactor of 2 – 5 to the requirements in IC manu-facturing. For very high demands on materialremoval, using a combination of grinding andpolishing might be an alternative.

Standalone polisherManual loading

Polisher and CleanerManual loading

Polisher and CleanerAutomatic loading

Full CMP cluster

Figure 1:From manually loaded

lab polisher to fully automatic CMP cluster

tool: The modular concept of the Peter

Wolters PM 200 Gemini allows an

upgrade of the CMP tool with growing

production demands of the MEMS devices.

Preston's law states that the removal rate of apolishing process depends linearly on the speed v between polishing pad and wafer andlinearly on the pressure p with which the substrate is pressed against the pad:

RR = kp p v

Properties of the slurry and pad used for the process are summarised in the Preston coefficient kp.

Higher removal rates can therefore be achievedby increasing the table speed, which has a limitation due to the occurrence of high centri-fugal forces spinning-off the slurry and by increasing the pressure of the wafer against the pad. Higher pressures demand for very rigid polishing machines which can be realised e.g.by using a cast-iron frame. However, sometimesvery high pressures can lead to delamination of the underlying layers.

Other means to achieve higher removal rates are utilising chemical aspects like increasingthe slurry temperature or using accelerating additives in the slurry or utilising mechanicalaspects like employing larger, harder and/or sharperabrasive particles or using tailored polishing pads. Since several years, CMP slurries optimisedfor MEMS applications are available from the slurry suppliers. Polishing pads with fixedabrasives, developed for microelectronics manufacturing applications, can also be used for MEMS fabrication.

Dishing or erosion of the structures during CMP,which are critical characteristics for ULSI manufacturing, are less critical in the MEMSworld. However, due to the much larger structures, sometimes in the order of the planarization length of the process, planarityrequirements are harder to fulfil. Especially in the case of opto-MEMS and the fabrication



Tilting mirror

Suspension wedge-shapedStop

Electroplated Cu

Nickel post

CMP

Figure 2:Crosscut through digital micro-mirror element. The tilting mirror is suspended by torsionalhinges at the nickel posts and is deflected electrostatically by thewedge-shaped electrodes (a). For fabrication of the freelysuspended mirror, a thick electro-plated copper layer, which hasbeen planarized by CMP serves as a sacrificial layer (b).

a)

b)

of micro-mirror devices, surface qualities of λ /10 over larger distances have to be achieved.The requirements on surface roughness Ra after CMP are often less critical with theexception of surfaces prepared for wafer bonding, where Ra should be less than 0.5 nm.

A critical step in the CMP manufacturingsequence is post-CMP cleaning since slurry residues cannot be removed when once dried on the surface. The best equipment solution is a cluster set-up where the wafers are cleaned immediately after polishing.Otherwise the wafers have to be kept wet until cleaning and drying. While particle size and density has a direct impact on device yield for microelectronics manufacturing,it has a less pronounced impact on MEMS fabrication due to the larger feature sizes. Only wafer bonding requires clean surfaces comparable to microelectronics.Contamination by metal residues is of no concern in MEMS. In some cases metals likegold, silver, nickel, iron etc., which are lifetime killers for CMOS, are used as functionalmaterials for MEMS.

While the mass production in microelectronicsdemands for large wafers with up to 300 mmdiameter, the number of units of microsystems issmaller and can be produced on 100 or 150 mmwafers. Due to relaxed structure width require-ments, older generation equipment, developedfor 100 – 150 mm wafers, is often employed.Depending on the application, the wafers aremade of silicon or other semiconducting materials, but also metal, glass or ceramicssubstrates are used.

In microelectronics manufacturing, polishingprocesses for various silicon oxides, mono- orpolycrystalline silicon, conducting metals liketungsten or copper and barrier layers like tita-nium and tantalum and their nitrides have been


Figure 3:Close-up of a digital

mirror array (DMA) (a). Mirror elements with mirror and deflection

electrodes (b). Only CMP allows the fabrication

of planar tilting mirrors. For details see

also figure 2a and b.

Figure 3a shows a part of the digital mirror array.In figure 3b details of the mirror elements likesuspension posts, mirrors with torsional hingesand wedge-shaped deflection electrodes are clearly visible.

For the fabrication of a surface micromachininginertial sensor a poly-Si CMP process has beendeveloped. The active sensing element consists of interdigital structures made of 10 µm thickpoly-Si. The thick layer has been deposited usingan epitaxy reactor with high deposition rates(EPI-poly). However, the surface of the poly-Si iscomparatively rough and disturbs the lithographyprocess. In order to get sharp structures, asmooth surface is needed which has beenachieved by performing a poly-Si CMP process.The challenge is getting a polished surfacewithout loosing the alignment marks for the nextlithography steps. Two different products havebeen realised using this technology. Figure 4ashows the poly-Si moving comb structure of anangular rate sensor, while in figure 4b the inter-digital structures of an acceleration sensor is pictured.

These examples prove that a demand on CMPprocesses for the fabrication of MEMS devicesexists and is increasing in the near future withgrowing production. Modular CMP cluster toolslike the Peter Wolters PM 200 Gemini fulfil thetypical process requirements from the develop-ment lab to the production floor. Materials suppliers have addressed this trend and haveoptimised several slurries for MEMS applications.Meanwhile a number of MEMS-specific CMPprocesses have been developed and are availablefor customers.


Figure 4:Angular rate sensor (a) and acceleration sensor (b), bothmicromachined in poly-Si. The roughness of the 10 µm thickpoly-Si has been eliminated by polishing before structuring.

Projection Mask-Less Lithography (PML2):MEMS-Technology for a Programmable Aperture Plate System (APS)

The fundamental technical performance challengefor direct write lithography is throughput.Whereas optical lithography (248 nm, 193 nm,157 nm) and the successor EUV (13.5 nm) isexpected to achieve 60 wafers per hour andmore, present day e-beam lithography is typicallytwo to four orders of magnitude slower. Thelimited throughput of e-beam lithography iscaused by two factors, being the serial nature ofthe e-beam exposure process, and the limited,useable writing current. To overcome thislimitation is the goal of the European MEDEA+project T409 and the joint project “Abbildungs-methodiken für nanoelektrische Bauelemente –ABBILD” in Germany. The key is a massivelyparallel writing strategy with a few hundredthousand beams to meet the technical andeconomical requirements for fast prototypingand the fabrication of small and medium volumeelectronic devices with ≤45 nm minimum featuresize. The primary innovations of this project will be the development of a 200 x reduction

electron optical system equipped with aprogrammable aperture plate system (APS). A proof-of-concept tool will be built within theMEDEA+ project T409 by the key partners LEICAMicrosystems Lithography GmbH (Jena), IMSNanofabrication GmbH (Vienna) and theFraunhofer Gesellschaft.

Concept of APSThe APS of the PML2 replaces the mask of aconventional lithography tool. Main componentof the APS is the blanking plate, where electricalsignals generate electrostatic fields according tothe pixel data, in order to blank or unblank theindividual electron beamlets. Other plates formthe beamlets and correct the optical properties of the electron optical column (figure 1). A bignumber of apertures (about 300.000) generatesa lot of single electron beams out of an expan-ded electron beam with about 1 inch diameter,which illuminates the complete aperture area ofthe first plate. The size of the beam formingapertures can be calculated to 5 µm x 5 µmtaking into account a required pixel resolution of 25 nm on wafer level and a projection scale of200:1 of the electron optical column. TheBlanking Plate is driven by a stream of pixel dataprepared off-line in advance and transmitted viaa high speed optical data link from an outsidestorage equipment onto the plate. Using a speci-fic driving electronics for each aperture everybeam could be individually switched ON or OFF.

The project ML2-APSThe BMBF supported project ML2-APS (FKZ: 01M3154T) is part of the ABBILD-project.Within this project ISIT together with theFraunhofer institutes IOF in Jena and HHI inBerlin have the goal to fabricate and assemblethe single aperture plates including the opticaldata path and to finish at the end with acomplete APS.

MEMS processThe Microsystem process development will focuson three key processes :

Representative Results of WorkMicrosystems Technology and IC-Design


Figure 1: Functionality of APS.

beam generation

e-

beam blanking

beam forming

• High rate silicon dry etching necessary forcreating the apertures

• High aspect ratio electroplating for blankingelectrodes

• Time controlled KOH silicon membraneetching for precise membrane thickness control

The fourth key point is the integration of thesethree single process modules into a completeprocess flow. Figure 2 shows the general processflow for preparing a blanking plate chip.

But before starting the whole process flow eachsingle process step has to be optimized by itsown. The requirements for good aperture perfor-mance are twofold. First having an apertureopening of 5 µm x 5 µm the egde radius has tobe smaller than 100 nm. There standardwidefield stepper with 0.8 µm resolution forMEMS application run into problems. This couldonly realized by OPC supported optical lithogra-phy or mix and match of optical lithography ande-beam lithography. Second requirement foraperture performance is the sidewall steepnessover the 40 µm membrane thickness, whichmeans an aspect ratio of better than 8. Thereforea high rate reactive etching process has beendeveloped for the silicon apertures. Table 1 andfigure 3 show the satisfying results.

The blanking is done by electrostatic forces. Theavailable blanking voltage out of the monolithi-cally integrated driving electronics is about a fewvolts. Together with a deflection angle of nearly1 mrad the height of the blanking electrodes hasbeen calculated to be in the range of 35 µm.Even the transparency of the aperture array(number of apertures per mm2) should beimproved because of its direct influence on thewriting speed. Hence optical lithography in thickresist layers and electroplating of the blankingelectrodes has to go to the limit. Based on an AZ type resist a process has been developed with40 µm resist thickness, resolution of 8 µm and aresulting electrode height of 35 µm after goldelectroplating. Figure 4 shows gold electrodesafter resist removal.


Figure 2:General process flowfor a blanking plate.

Table 1:Results of processdevelopment forhigh aspect ratio

apertures in silicon

Figure 3:Cross section of highrate reactive etchedsilicon apertures.

ApertureØ Top[µm]

1,2 mm

1,2 mm

ApertureØ Top[µm]

1,2 mm

1,2 mm

ApertureØ Top[µm]

1,2 mm

1,2 mm

ApertureØ Top[µm]

1,2 mm

1,2 mm

ApertureØ Top[µm]

5,0

10,0

ApertureØ Bottom

[µm]

3,9

9,1

Depth ofaperture

[µm]

73

94

Sidewallangle

[°]

89,5

89,7

Figure 4:Electroplated blankingelectrodes 35 µm high.

- high rate reactive etching- etch of backside masking

- aperture filling e.g. copper and CMP

- realization of blanking electrodes by surfacemetal micromachining

- wafer thinning

- removing aperture filling- backside metalisation


Based on the result of the single processdevelopment the demonstrator mask design wascarried out. Figure 5 shows a complete APSdemonstrator chip design. The chip size is 8 mmx 8 mm and contains four aperture areas with1000 apertures respectively.

After mask fabrication the complete flow for theblanking chip demonstrator was processed. TheSEMs in figure 6 and 7 show good quality of thedemonstrator process also when looking indetails. First tests in the IMS teststand in Viennaresult in good switching properties of the electro-des with an deflection angle of 0.25 mrad/V.

Design and layout of the monolithicallyintegrated driving electronicsThe very large amount of electrodes on the APScannot be controlled by outside electronics whichis connected to the MST-chip by bond wires or by flip-chip because it is impossible to directlyconnect more than several hundred electricalcontacts. The precision for the switching of thebeamlets must be very precise, i.e. in the rangeof nano seconds. The exposure concept foreseesthat the APS is able to switch about 300.000electron beams at the same time while the wafermoves continuously. The amount of data tohandle is in the range of several Tbit per second.Therefore only a monolithically integrated drivingelectronics next to the blankers is able to fulfilthis challenge. The necessary memory, logic anddriver for each aperture has only minimumspace. To keep the mechanical precision theallowed bowing of the electronics as well as of

the APS-plate due to heating has to be verysmall, resulting in an advanced electronic techno-logy with low power dissipation. This means theelectronic focus is on 180 nm CMOS technologywhich could only be dealed by an externalprovider which allows a supply voltage down to1.25 V. In addition to the APS demonstrator anelectronic demonstrator has been designed fortesting memory, logic and driving electronics forthe APS application (figure 8). It shows the denselayout of one aperture cell, designed on a0.01 µm grid with the area for the aperture inthe center of the upper part.

AssemblyThe integration technology for the APS platescovers the assembly and interconnection of theelectronics and microsystem components on thebase plate (compare figure 9). According to themodular plate concept several components suchas the aperture chips and the hybrid electronicchip have to be mounted and electricallyconnected to the base plate. The assembly of the aperture plate system consists of threeindependent tasks:• Wafer bonding of support frame and base

plate wafer• High precision chip stacking with less than

1 µm positioning error• Assembly of the electrical and micromechanical

components on the base plate wafer


Figure 5:APS Demonstrator:

Complete chip design 8 x 8 mm2

in size.

Figure 6:Detail of a completedemosntrator chip with apertures and blanking electrodes.

Figure 7:Top view of figure 6.


cation showed undistorted images of the squareholes in the resist as demonstrated in figure 10.

Next stepsFor each of the above described working fields,the MEMS process, the monolithically integrationof the driving electronics and the assembly of allcomponents for the modular plate concept,demonstrators have been defined and realized.The actual status of evaluation of the availableresults from the defined demonstrators showgood performance. This fact makes therealisation of a fullsize APS in the next step verypromising.

A key issue of the aperture plate system is thegeometrical stability of the stack. Therefore a5 mm thick support frame is used as stiffener forthe base plate wafers. To minimize the effect ofinhomogeneous temperature loads a very goodthermal conductivity combined with a lowcoefficient of thermal expansion (CTE) is required.No adhesives can be used since the vacuum compatibility cannot be guaranteed under heavy electron exposure. The prefered solution is AuSi eutectic bonding which fulfils allrequirements with regard to electrical andthermal conductivity, vacuum compatibility, andeasy process integration.

The design of the APS plate systems containsstacked dies with a relative placement accuracyof better than 1 µm. This precision exceeds the requirements for common high precisionbonding of optical fiber components. Someequipment manufacturers specify an applicationdependent accuracy between 0.5 µm and 1 µm.Furthermore a solder connection with a highmelting point has to be used since the whole stackhas to withstand a reflow process during theassembly of the base plate wafer. Possible soldersare eutectic or intermetallic AuSn alloys.

Exposure experiments First aperture arrays have been used for exposureexperiments in an Ion Projector System to inspectcompleteness of all produced apertures and theirquadratic shape. This could be done becauseions travel in electrostatic fields on the samepaths as electrons because they are at the sameenergy much slower so that the mass effect iscompensated. The exposure with 9 x demagnifi-

Figure 8:Electronic layout for one aperture cell.

Figure 9:Modular plate

concept for theAPS, base plate

with hybride electronics andmonolithically

integrated blanking chip.

aperture chip(with monolithically integrated electronics

for blanking plate)

free beam optics base platewith one wiring level

openings forpattern lock system

hybrideelectronic chip support frame

Figure 10:Ion exposed

resist using anaperture

array as a mask.

Microscanners for Mobile Laser Projection Displays

For several years already there is a steadytendency to more and more scale down the sizeof mobile phones. But at the same time thedemand for larger image size and higher resolu-tion of the mobile displays increases. A cleversolution to meet these two colliding requirementsis to integrate a tiny laser scanning projectiondisplay into the mobile phone. The size of theprojected image then only depends on theprojection distance and thus can be several timeslarger than the mobile phone itself. Based onmore than ten years of experience in design andfabrication of optical MEMS Fraunhofer ISIT hasdeveloped a miniature two-axes microscannerchip that deflects a laser beam in a fast rasterscan for image projection.

The microscanner consists of a movable siliconmirror plate that is suspended by thin torsionalbeams in a frame that itself is movably suspendedin a fixed chip frame. Boths axes of the scannerare actuated by electrostatic forces. While themirror plate is driven in resonant mode at 4kHzthe surrounding flexible frame typically is drivenquasistatically at a frequency of 30Hz. Using con-tinueous bidirectional scanning 8000 image linesare projected per second. A high sophisticatedelectronics measures within a few nanosecondsthe instantaneous 2D-deflection of the scannerand reads out the corresponding pixel intensityfrom the image memory for correct intensitymodulation of a small laser diode. With that kindof configuration the laser modulation is synchro-



Figure 1:An integrated tiny

laser projectiondisplay will be able toproduce images thatare several times lar-

ger than the mobilphone.

Figure 2:a) The core components of the miniaturelaser beamer: A two-axes microscanner chipand a laser diode.b) Using a second laser beam and a positionsensitive diode the xy-position of the mirrorgives a high resolution position feedback.

MEMS-Scanner

Display-Laser

Monitor-Laser

xy-Position-Sensor

nised to the mirror movement at any time andunpredictable impacts, vibrations or temperaturedrifts are easily compensated without imagedistortion. But in addition that control electronicsalso offers the capability to use a lissajous scaninstead of a raster scan which can have severaladvantages, e.g. larger image size, higher scanfrequencies and less jitter. In order to demonstratethe imaging capabilities of that microscanner amicroprojector with a resolution of 512 x 256pixels was set up.

The microscanner chip has a size of only five byfive millimeters which allows the dimensions ofsuch a miniature laser beamer to be reduceddown to sugar cube scale. Each processed siliconwafer consists of 500 scanners therefore thefabrication process enables cheap mass produc-tion of these microscanners which is importantfor consumer applications. Other than thatmentioned application in mobile phones such a miniature laser projector becomes of interestalso for the automotive industry for use in head-up-displays.


Figure 3:a) Applying a voltage to the verticalcomb electrodes leads to a quasistaticdeflection of the slow axis.b) Applying an AC-voltage to the verticalcomb electrodes of the mirror leads tomirror oscillation.

Figure 4:Detail view of the two axes mirror chip that shows the tiny comb electrodes of the mirror and larger electrode structures of the second axis.

Figure 5:Two examples of projected images (graphical test image and the moon). For a better visibility a green laser source was used.

Specifications of the 2D-Scanner-Chip:

chip dimensions: 5 mm x 5 mm x 0.5 mmmirror size: 1.5 mm ∅mirror scan frequency: > 4 kHzgimbal scan frequency: 0..500 Hzmirror scan range: +/- 12°gimbal scan range: +/- 8° (quasistatic) .. +/-20° (resonant)actuation voltage: < 80 V

Development of a New Sputter Process for the Deposition of Piezoelectric Layers forMEMS-Actuators

Despite the fact that the fabrication of thin film PZT Pb(Zrx Ti1-x)O3 is a field of intensive research activities, the fabrication of thin films made of PZT is still a big challenge.Methods like screen printing or even bondingand grinding of bulk PZT plates are very limited. Screen printing requires a very high firing temperature to achieve a void free film and due to chemical reactions of the evaporated lead of the PZT the silicon substrateis damaged. Bonding and grinding allows themanufacturing of approx. 20 µm thick PZT but itis a very expensive way for the integration of the PZT material and due to thermal mismatch of the PZT to silicon very often cracks occurred.

Commonly used thin film deposition techniqueslike MOCVD ( metal organic chemical vapour deposition) magnetron sputtering or

sol-gel suffers all from the low deposition rates. For magnetron sputtering a max. sputterrate of 5 – 15 nm/min are reported while thepublished results for MOCVD are in comparableranges. On the other hand sol-gel techniques areoffering at the first sight a very attractive way forthe deposition of PZT since these techniques canbe applied without the use of expensive tools,however a more detailed consideration showssome severe drawbacks. First single sol-gel layersmust be very thin (typical 50 nm – 200 nm) to avoid the development of cracks during thefollowed thermal annealing. To achieve thickerlayers it is necessary to repeat the spin-on of thegel layer and the annealing at approx. 700° Ceach time. Secondly the resulting layers havenevertheless very often cracks and defects due to the continuous handling of the soft gel layerprior to annealing. Beside the difficulties to avoiddefects in the fabricated PZT layer, the sol-geldeviated PZT layer showed very often a gradientin their chemical composition caused by the evaporation of lead during the various annealingsteps. So in fact industrial applications of thinfilm PZT material used in an actuator are veryrare and limited. However PZT as actuator material has an enormous potential for use inMEMS devices. Microactuators like valves, relays,ink-jet print-heads, micromirrors, filters etc. driven by the piezoelectric effect of PZT are onlya small fraction of possible applications. The piezoelectric drive allows the realisation ofactuators with large forces at high frequenciesand low energy consumption.

To overcome these limitations Fraunhofer ISIT started a close co-operation with Fraunhofer ISTto develop a high rate sputter process for PZT based on the Gas Flow Sputtering techniqueinvented by Fraunhofer IST. The Project is funded by Ministerium für Wirtschaft, Arbeit und Verkehr des Landes Schleswig-Holstein. The Gas Flow Sputter technique uses a specificcathode arrangement to produce a high density plasma (figure 2). An argon gas flowtransports the material towards the substrate.



Figure 1:This figure shows the lattice of a Perovskite Type material. The dark atoms are Pb, red is oxygen and in the middle of the common used unit cell is Zr or Ti.

A reactive gas can be added outside the cathode if required. Due to the separation of the discharge from the reactive gas a chemicalreaction of the target surfaces with the reactivegas can be avoided.

Compared to the conventional magnetron sputterprocess the gas flow sputter technique enablesvery high deposition rates especially for oxides and nitrides. The sputter cathodes forthe deposition of a complex material can be realised by a set of segments made of the different elements.

A target consisting of the three metals (Pb, Zr, Ti)was used in the experiments to deposit PZT (figure 3). The oxygen was added as reactive gas

beyond the cathode. Since the cathode arrangement delivers a non-homogeneous plasma density resulting in a non-uniform filmthickness the substrate is moved perpendicular tothe plasma jet during the sputter process.

Characteristics of the GFS process:• hollow cathode discharge• sputtering of the inner surfaces of the cathode• transport of material by an Argon flow• inlet of a reactive gas beyond the hollow cathode

Using an extremely low power level of about 600 W sputter rates of 200 nm/min were observedallowing the deposition of PZT films with a thickness up to 6 µm within 30 min (figure 5).Even much higher sputter rates seems possible


Anode

Argoninlet

Hollowcathode(Target)

Reactive-Gas-Inlet

Substrat

Figure 2:Scheme of the GFS process.

Figure 3:Composite target

existing of three element rings

(Pb, Zr, Ti).



Figure 4:GFS Source in

operation.

since only a small fraction of the available powerlevel is operated. The deposited PZT films werecrackfree up to a thickness of 7 – 8 µm. The produced PZT layers were characterised with a variety of analytical methods includingSEM (Scanning Electron Microscope), EDX(Energy Dispersive X-ray), EPMA (Electron ProbeMicro Analysis), SIMS (Secondary Ion MassSpectroscopy), XRD (X-ray Diffraction) and TEM(Transmission Electron Microscope). High piezo-electric coupling coefficients require an optimumratio of Zr/Ti = 0.52/0.48 (morphotropic phaseboundary). Many parameters like length andarrangement of the targets, flow of the argonand oxygen and the used power level haveshown an influence on the composition of PZT films. Final results from EPMA measurementson deposited PZT samples demonstrated a stoichiometry near to the target composition(figure 6).

Measurements using XRD showed that the PZTfilm consists of small crystals (figure 7).Furthermore more detailed experiments resultedthat heating the substrate increases the level of the crystallinity of the deposited film as well as an additional post sputter annealing step.Beside the tests on the chemical composition orthe crystallinity electrical tests especially fordetermining the piezoelectric coupling coefficients d15, d31 and d33 are still on going. Firstmeasuring results of the dielectric constant εr ofthe thin film was found to be over 500. Onlyperovskite type materials have got such highvalues. Despite the preliminary stage of the workit could be noticed that the studied new PZTsputter process based on the gas flow sputteringis very promising and will probably lead to abroad range of new application in MEMS.


030

500

1000

1500

Co

un

ts/s

Position [˚2Theta]70605040

D_T2T_PropMir.CAF Figure 7:The red function is

measured. The blue vertical lines

represent the theoretical peeks

of this type of PZT.

Bulk #43 #43 temp #52 #53 #54 #55 #56

10

20

30

40

50

60

OTiZrPb

Ato

m%

0

Figure 5:Cross section of a

PZT layer.

Figure 6:EPMA measurements.

The stoichiometry would beperfect, if the ratios

of Pb/Zr/Ti/O2 would be20/10,4/9,6/60.

MIMOSA: Microsystems Platform for Mobile Services and Applications

MIMOSA is an European Commision fundedIntegrated Project in the frame of theInformation Society Technologies Programme,contract number IST-2002-507045, in the Sub-programme Micro and Nanosystems. Thekey figures are

• 15 partners from 7 countries• co-ordinator: ST Microelectronics , France• total budget: 23.2 Mio g; EC funding:

10.0 Mio g• duration: January 2004 - June 2006• http://www.mimosa-fp6.com

The MIMOSA objective is to create a new opensystem platform for context-aware mobile services

and applications. MIMOSA extends the area oftelecommunication business to AmbientIntelligence, i.e. a functional environment in thebackground surrounding and supporting theuser. Ambient Intelligence includes a multitude ofinterconnected sensors and smart tags providinginformation that can be utilised in mobile appli-cations as such or as an index to Internet or localservices. The MIMOSA approach is mobile phonebased and strongly human-centred, providing theusers with a smooth transition from currentmobile services to Ambient Intelligence services.

End users and application developers participatein designing and evaluating how AmbientIntelligence and short-range communication



Figure 1:MIMOSA project organisation.

WP3C

User interface toAmbient Intelligence

WP3B

Context awarenessand actuation

WP3A

Short-rangecommunication

WP3D

Energyscavenging

WP3

Technologyplatforms

WP4

Microsystemsintegration

WP2

Systemarchitecture

WP2

System integrationand system platform

WP1

Applications andservices

WP1

Proof of conceptsand demonstrators

with environment could be best utilised in theeveryday life. To demonstrate the genericcharacteristics of the platform, MIMOSA deve-lops specific applications with particular emphasison physical browsing, health monitoring, intelli-gent housing, fitness/sports, context awarenessfor Ambient Intelligence and intuitive userinterfaces.

In the area of short-range connectivity, MIMOSApositions itself to low-cost, low-bit rate territorythat can be set up with relatively modestinvestments in the infrastructure. A focus ofMIMOSA is the development of novel low-powermicrosystems, in particular wireless sensorsexploiting the RFID technology, highly integratedreaders/writers for RFID tags and sensors, low-power MEMS-based RF-components andmodules and low-power short-range radios.

Ultraminiaturized low-power sensors and novelintuitive user interfaces to Ambient Intelligenceare crucial for usability. The contribution ofFraunhofer ISIT focuses on these workpackages.For the fitness and sports application a continu-ous lactate sensing device is being developed.The MIMOSA vision is to integrate this sensor ina smart plaster system including a wireless com-munication link to the mobile phone. Theamperometric silicon-based lactate sensor con-tains the lactate oxidase as a catalyst (figure 2).To achieve a painless transfer of interstitial fluidthrough the skin, a polymer microneedle array,investigated by AMIC AB from Uppsala, will beintegrated in the sensor module.

A second sensing task is on low-cost inertialmeasuring units (IMU). These units, measuringaccelerations and angular rates in three dimen-sions are able to serve as inertial user interfacesor as motion monitoring devices in sports andfitness. The underlying MEMS technology of theIMU has been described elsewhere in this annualreport (see page 54). The work in MIMOSAfocuses on new sensor designs and low-powersensor interfaces for the mobile application.

The work on new user interfaces to AmbientIntelligence divides in optical, acoustical andinertial UIs. Fraunhofer ISIT contributes mainly inthe optical section with the development of anmicromirror-based laserscanning micro-projectorwhich is described in a separate chapter of thisreport (see page 46).


Figure 2:Priciple of thelactate sensor.

polymeric housing

lactate

LOD LOD LODH2O2H2O2

working electrode

counter electrode

silicon

agarose gel

reference electrode

Surface Micromachining Process Platform for the Development of Inertial MeasurementUnits (IMU) in Automotive Application

The detection of inertial motion like accelerationand rotation is widely used in automotive indu-stries for the control and stabilization of vehicledynamics like Airbags, Electronic StabilizationProgram (ESP) or car navigation systems. At pre-sent each functional subsystem has its own inte-grated sensor system. Providing an all-in-one sen-sor solution for the concurrent measurement ofall 6 degree of freedom of inertial motion in asingle Inertial Meassurement Unit System (IMU) isthe ambitioned mid-term objective on the auto-motive technology roadmap (figure 1). This cen-tral IMU will then be providing all relevantmotion data to a multitude of automotive subsy-stems.

For single or dual axis sensors the MEMS techno-logy has already a broad market share due to theinherent superior performance in measurementaccuracy, costs and reliability. Next to continuousperfomance improvements by design and tech-nology optimisation common future trends forMEMS inertial sensors will be cost and sizereduction by more complex technology integra-tion like the implementation of a sensor packa-ging process on wafer level.

At Fraunhhofer ISIT the surface micromachiningprocess PSM-X2 has been etablished, whichallows the production of MEMS devices such asvibratory gyrometers or accelerometers whereas



Table 1:PSM-X2 keyfigures.

Figure 1:Degrees of freedomfor inertial motionand measurement range for automotive application.

Total Device Thickness

Operating Pressure Range

Electrode Spacing

Min. Feature Size

Active Layer Thickness

1,2 mm

1 µBar < p < 1 Bar

1,5 µm

2 µm

e.g. 11 µm

the mechanical active structure is formed by e.g.an eleven micron thick poly silicon layer (figure 2).An in-plane motion can for example be achievedby electrostatic actuation of electrode fingerstructures. For the detection of out-of-planedeflection an underneath conducting layer isused as counter electrode. To maintain a definedoperating pressure condition and to protect thepoly silicon microstructures from mechanicaldamage and particel defects a wafer-level

packaging process is performed by using eutecticgold-silicon bonding. In this step a cap waferwith anisotropic etched cavities is aligned andbonded to a sensor device wafer.

The gold-silicon bonding line shows excellent gashermeticity and leakage rates below 10-13 mBarxl/s.Superior vacuum conditions are achieved by theintegration of a thin getter film in the cap wafercavity above the sensor structure. A cross sectionof a final chip device is seen in figure 3. The sensor package is robust enough to fulfill thehigh quality standards of automotive industry.Applying the process PSM-X2 gyrometers andaccelerometers with appropriate sensor perfor-mance have been demonstrated (figure 4).

In the PSM-X2 process a broad geometry flexibilityof the MEMS structure together with a high operation pressure bandwith is combined. Sincethe IMU requires different sensor designs andconcepts this process platform is uniquely suitedfor their common production. Future work willincorporate the integration of 3D accelerometersand 3D gyrometers in a one chip solution.


Figure 2:MEMS active layer: 11 µm thick polycrystalline Silicon.

Figure 4:Wafer level packagedMEMS wafer with gyrometer devices,manufactured with PSM-X2

Active Layer

Al-Pads

Bondline Getterfilm

Sensor

Cap

Counter Electrode

Figure 3:Vacuum encapsulatedMEMS device.

Training Course for MEMS Design

ISIT has a long history of developing variousprocesses, technologies and products of micro-electronic mechanical systems, MEMS. Theinstitute contributes to the dissemination ofadvanced MEMS technologies by scientific publications, conference articles, presentations –at exhibitions and at direct contacts to enterprises.Especially the transfer of MEMS technologies tocompanies and first time users was supportedduring several years by the European Unionwithin the EUROPRACTICE programme. One result of the good visibility of ISIT as a MEMStechnology provider was an increase in the number of requests from countries outside ofEurope. One such request came from the Malaysian institute for microelectronics MIMOS,Kuala Lumpur. This institute has in the pastalready cooperated with institutes from theFraunhofer network microelectronics on CMOS

technologies. Now MIMOS wants to investigate and build up competencies in micro-sensor and MEMS technologies. To prepare such technology transfer the idea was bornthat MIMOS engineers should become experienced with surface micromachining by preparing designs for several devices that are later produced within ISIT. A trainingcourse for that was set up and organised within ISIT and office space and working placeswere prepared for MIMOS employees in Itzehoe. Four MIMOS engineers with designexperience in microelectronic circuits have visited ISIT from September to December 2004.They were instructed to use ISIT design tools to design several acceleration sensors with read-out circuitry making use of the ISIT polysiliconsurface micromachining process. The design process included mathematical calculations and



Figure 1:Various steps inMEMS design.

FEM simulations to achieve given specifications,the translation of this information into a CAD layout as well as into a behavioral model to be able to simulate the sensor with an electrical simulator. With the aid of this model it was possible to design and simulate a well-suited read-out circuitry.

The sensor designs are now being manufacturedby the ISIT MEMS technology. With finishedsamples of their own designs MIMOS will buildup test set-ups to measure and characterise the final devices. With this specialised trainingprogramme MIMOS engineers have gained first hand experience in MEMS technologies and can come to a more precise decision which directions of technology development are best suited for the demands of the Malaysian industry. Transfer of MEMS technolo-

gies from Itzehoe to Kuala Lumpur that are finally identified by MIMOS will be the central point of future project ideas and negotiations.

The successfully executed training course forMIMOS engineers is a new working field for ISIT.This experience will help to decide whether such an enlargement of the ISIT training offers is a reasonable extension of the training programmes already offered for companies in the field of packaging and interconnection of integrated circuits. Increasing demand forMEMS design technologies is an indication of the broadening application and market acceptance of MEMS technologies.


.250 .500 .750 1.0 1.250

1.0

.5

1.25

1.5

2.0

2.25

2.5

.250 .500 .750 1.0 1.250

.5

0

1.0

1.5

2.0

2.5

3.0

.250 .500 .750 1.0 1.250

.5

0

1.0

1.5

2.0

2.5

3.0

.250 .500 .750 1.0 1.250

1.0

.75

1.25

1.5

1.75

2.0

2.25ω

time (ms)

v

Transient Analysis ´tran´ : time = (0 s -> 2.5 ms)

Vrefout rec

ω

time (ms)

v


Vrefout

ω

time (ms)

v


Vrefout ca

ω

time (ms)

v


Vrefout hp

Figure 2:Simulation of

MEMS devices.

Pathogen Detection on Electrochemical Microarrays

The detection of pathogens is today as importantas it has been in the past. One top issue is thethreat of bioweapon attacks by terrorist organi-sations with microorganisms like anthrax (Bacillus anthracis). Another topic are newevolving pathogens, causing severe diseases, like SARS and bird flu epidemics and also antibio-tic-resistant microorganisms. Bacteria strains, likemethicillin resistant Staphylococcus aureus (MRSA),can cause life-threatening surgical woundinfections and can become a serious problemwithin the healthcare system. Methods forroutine identification of microorganisms take at least several hours, a day or even more andare therefore of little use in giving fast neededanswers (figure 1).

That is where modern analytical techniques,combined with molecular biology, offer substan-tial benefits. The development of electrochemicalmicroarrays with ISIT’s high-end silicon technologytogether with portable instruments for on-siteanalysis in our group are the basic tools for thispurpose. Offering easy handling and fast results,we adapted the established biochip platform totwo different strategies as examples for highlysensitive, nucleic acid based pathogen detection.

All nucleic acid based applications start with the immobilisation of target specific captureoligonucleotides to individual interdigitating goldultramicroelectrodes on the biochip. Specificrecognition on a certain position occurs throughhybridisation with a directly or indirectly biotin-labelled target, present in a given sample.The biotin-label mediates the affinity binding ofthe enzyme conjugate ExtrAvidin®-alkalinephosphatase. The enzyme itself initiates a site-specific, electrochemical reaction on theelectrode with the substrate p-amino phenylphosphate, called redox-recycling. On electrodepositions with enzyme a characteristic currentprofile is monitored and used for detection with a 16-channel potentiostat. Starting after theisolation of the nucleic acid material, the typicalanalysis program takes around 30 minutes.

The first strategy targets ribosomal 16S RNAfrom bacteria responsible for different widespreadurinal tract infections. The 16S rRNA is present inbacteria cells at a high copy number around20.000 per cell (E. coli), leading to a detectionlimit of 10.000 cells/mL.

The method is most straightforward in applica-tions where enough nucleic acid can be isolated.The total RNA is directly extracted from the cellsand bacteria specific analysed on the electrodesafter a few steps. 16 of such microelectrodes arearranged into a precisely fabricated microarrayon a silicon based biochip, that is coated withtarget specific capture oligonucleotides. In a set-up for 5 different bacteria species, 3 positionseach or a total of 15 are used for pathogen

Representative Results of WorkBiotechnical Microsystems


Figure 1:Escherichia coli andcultiviation plate.

identification, the last position is an internal posi-tive control. The sample scheme and an examplefor the positive detection of 16S rRNA ofStaphylococcus aureus is illustrated in figure 3.

The second nucleic acid based strategy includes a very important tool in molecular biology, calledPCR (polymerase chain reaction). It is used forexponentially amplifying target DNA of patho-gens. In a cell, DNA is present only in very lowamounts, usually just as a single copy per cell.But using the material from only a few cells,specific regions of the DNA can be selected andcopied millionfold with PCR in a process thattakes usually 1-2 hours.

We recently established a special PCR variant,that amplifies DNA in a form that can be directlyanalysed on our microarrays and developed auto-mated programs for the technical platform forthe applications. The next step underway is thedesign and testing of microarrays that can beused for the detection of DNA from pathogens,like Bacillus anthracis or ortho pox viruses.


Figure 3: Microarray for detection of 5 bacteria species, scheme of capture sequences and an example for the positive detection of RNA from Staphylococcus aureus (slope value analysis).

position

slo

pe

[nA

/min

]

Staphylococcus aureus

2 1615141312111098765431

50

100

150

200

0

Figure 2: Structure of aDNA 19mer.

High Vacuum Wafer Bonding TechnologyAuSi Eutectic Wafer Bonding with Integrated Getter Thin Film for Long TermStable High Vacuum

MEMS operation requirementsMicrosensor packaging is one of the mostimportant and challenging, technology areas. Inparticular, hermetic packaging on wafer level is akey technology of many microelectro-mechanicalsystems (MEMS). The hermetic sealing protectsthem from harmful environmental influences,significantly increasing their reliability and lifetime.In addition some MEMS need a specific gas orpressure environment within the package tofunction as specified, see table 1. This articleintends to give an overview on the relevanttechnological topics to produce hermetic sealed,micromachined devices on wafer level with con-trolled cavity pressures ranging from 10-4 mbar to1000 mbar.

Wafer-level processes are particularly interestingfor the MEMS packaging since they can reducethe fabrication costs and open up possibilities forbatch processing. Various wafer level sealingtechnologies may be used, including wafer bon-ding, cavity sealing by thin-film deposition, andreactive sealing.

Fraunhofer ISIT develops together with the project partners Saes Getters, ST Microelectronics,Thales Avionics, EV Group, and University Paviawithin the european project VABOND a processon eutectic AuSi wafer bonding to produce low-cost and long-term reliable hermetic MEMSpackages. Figure 1 shows the main functionalelements of a surface micromachined MEMSdevice with integrated getter film in the cap.

Beside maintaining vacuum, encapsulation onwafer level solves the problem of device

protection during the wafer dicing operation.The improved robustness of capped devicesallows MEMS devices to be handled in existingstandard semiconductor backend processes.

AuSi eutectic bonding AuSi eutectic bonding is a technology usingeutectic formation at 363° C between a siliconwafer and gold deposited on another siliconsubstrate. The bond temperature used is in the range of 380 – 400° C. This is compatiblewith Al device metallisations. Due to the liquidmelt formed, this technology tolerates wafertopography coming from previous processingoperations. The technology is also compatiblewith extended outgassing cycles and the activation requirements in case a deposited getter layer is present in the device cavity.Compared to glass frit bonding, AuSi eutecticbonding does not outgas during the wafer bonding cycle, and requires only very small bondframe widths, typically in the range of 60 – 100 µm. This increases the throughputwhich is a major parameter for low-costproduction.

Getter technology The use of Non Evaporable Getter (NEG) material(Zr based alloy) is required to ensure suitablevacuum (total pressure under 1 x 10-3 mbar) andlong-term stability in MEMS devices. NEG canchemically sorb all active gases, including H2O,CO, CO2, O2, N2 and H2. The main constraintsimposed by the device design and process arethe compatibility of the getter with the fabrica-tion process, the thickness of the getter film andan activation temperature compatible with thebonding process. Besides this, SAES Getters labo-ratories offers a patterned deposition of the get-ter material on the cap wafer by a proprietarytechnology: PaGeWafer®‚.

The thick getter film can be selectively placedinto the cavities without affecting the lateralregions of the wafer where the hermetic sealingis to be performed. The typical pattern lateraldimensions are in the range of the millimeter,while the getter film can be placed in the cavities

Representative Results of WorkModule Integration


bolometer

resonator

absolute pressure sensor

accelerometer, switch

sensor/device type

< 10-4 mbar

10-1 – 10-4 mbar

1 – 10 mbar

300 – 700 mbar

vacuum level

Table 1: Required vacuum level

for different MEMS.


with any depths, ranging from few microns up tohundreds of microns. Figure 2 shows the precisedeposition of the getter material inside thecavities.

The getter film consists of a special Zr alloywhose composition is optimized to maximizesorption performance or to maximize performan-ce in specific sealing or bonding processes.

Cap wafer cleaningWafer cleaning of the cap wafer is usually required before bonding to remove organics from the gold bond frames. The

getter layer must tolerate the cleaning chemistries. It has been discovered that a caustic chemical treatment of the getter film both cleans the film and enhances itsperformance without measurable degradation of its structural integrity. For example, caustic chemical treatment SC1 withNH40H/H202/H20 and SC2 with HCl/H202/H20 did not affect the morphology and the sorption capacities of the getter film and significantly increased the sorptioncapacity, measured after ASTM standard F 798-82. The getter film at wafer level can withstand

oxide

monosilicon substrates

monosilicon substrates

CrPd or TiPd

polysilicon

buried interconnections

sealingring

sealingring

sealingring

metal pad

Figure 2:Cap wafer with

deposited getter layers.

Figure 1:MEMS construction with getter.

also treatment with a highly aggressive HNO3 process up to 65 % @120 °C. The fullcompatibility of the getter film towards bothtemperature and chemical treatment withregards to the activation and capacity of the getter film is demonstrated. Typical absorptionspeed and absorption capacity of the patternedgetter film per unit area at room temperature for hydrogen and carbon monoxide are reportedin figure 3.

Getter activationThe getter film is supplied in a stable, passivatedform to protect the getter and to ensure that itperforms as specified. The PaGeWafer‚ can besafely handled in clean room air. Once the getterfilm is in a vacuum or noble gas environment, itneeds to be activated. Activation is achieved byapplying thermal energy to the getter to diffusethe passivation layer into the bulk, rendering the surface of the grains chemically active andready to pump contaminants out of the MEMSpackage.

The getter film activation can be achievedthrough three main scenarios:1. the classic scenario is activation of the getter

as part of the wafer bonding process. Thetemperatures under vacuum reached in thebonding process will simultaneous activate the getter as well as bond the device and capwafers. In this case, the getter film will alsoimprove the process conditions, by achieving a higher vacuum between the two wafers inthe cavity.

2. The second scenario is to apply heat to thecap wafer after bonding

3. The third scenario is first to heat the cap waferunder vacuum and then align the wafers andbond them.

BackfillingTo realize a defined gas damping for resonating sensors, a gas-filling procedure has to be established. Only inert gases or gases that do not consume the getter or alterthe getter sorption performance may be backfilled in the device cavities. Most oftenArgon is selected because of good damping characteristics and low out diffusion. The backfill operation is typically one step in the wafer bond cycle. Figure 4 shows the dependency of the device Q-factor from cavity pressure for a typical BOSCH type yaw rate sensor. The cavity pressure can be tuned to any value between 10-4 mbar and 1000 mbar, even overpressure is possible depending on the waferbonder infrastructure.

Hermeticity testingThe pressure inside of the vacuum encapsulateddevices depends on the outgassing of the innersurfaces, the leakage rate through fine leaks andpermeation through the walls, see figure 5. Theoutgassing depends mainly on the fabricationprocess of cap and device wafer, which has to beoptimized. Fine leaks arise from imperfect bonding or crackinitiation. The pressure change per unit time in adevice can be expressed asdP/dt ≈ L / Vwhere L is the leak rate and V the cavity volumeof the device. Typical cavity volumes range from0.1 mm3 to around 5 mm3.



0.001 0.01 0.1 10.0001

1

10

100

1000

cc/s

.cm

2

0.1

cc.torr/cm2

Sorption test after SC1 and SC2 treatment

ReferenceSC1 + SC2

Sorption temperature: 25 °CActivation: 450°C x 45' CO

H2H2

CO

Figure 3:Sorption characteristics for H2 and CO per cm2 of getter film after a SC-1 and SC-2 treatments.

Since fine leaks may always be present a leaktest is necessary to guarantee a leakage ratewhich is small enough to be compensated by thegetter. This leak rate may be called the criticalleak rate, as it defines the devices within thestatistical cavity pressure distribution that fail the first after the guarantied lifetime is fulfilled.As an example: for a device with a life timedemand of 15 years and internal vacuumrequirement better than 0,1 mbar and a gettercapacity of approximately 1.7 x 10-5 mbar·l per cavity the maximum tolerable leakage ratefor a cavity volume of 0.26 mm3 is 3.6 x 10-14

mbar·l/s. Due to the high Helium permeation inSi and silica a long-term stable, high vacuumbetter than 10-4 mbar is very difficult to achieve. Fraunhofer ISIT has developed a in-line, ultra-fineleak test on wafer level to determine the leakrate of every single resonating device beforeshipping out. This ultra-fine leak test overcomesthe limitations of He and Kr85 fine leak test and iscompatible with integrated getter and unaffectedby the typically very small cavity volumes. Critical leak rates down to 10-16 mbar·l/s can bedetermined without interference betweenneighboring devices.

ConclusionsIn respect to process yield, a eutectic waferbonding technology with a liquid phase of > 1 µm thickness will considerably improve thetolerance of the bonding process in respect tosurface topography and bondframe imperfections(scratches, particles). A cap wafer cleaningprocedure with SC1 and SC2 has found to bevery effective to achieve a good bond homoge-neity, and at the same time even improves thegetter sorption capacity. It is not recommended

to apply Ar ion milling or backsputtering on any of the used wafers. PaGeWafer‚ can assurehigh performance MEMS sensors, considerablyincreasing the device life time by maintaining the Q-factor of the device, at the same time relaxingthe stringent requirements for minimum leak rates.

AcknowledgementsISIT greatfully acknowledge the project fundingby the European Commission (IST-2001-34224).


10000

100000

0.01 0.1 1

Q f

a cto

r

1000

pressure (mbar)

Figure 4:Dependency of the Q-factor vrs. cavity pressure [N2]for a typical surface micromachined resonator.

getter

silicon

2.

3.

1.

bond line

2.

3.

1. Permeation

Leakage

Desorption

Figure 5:Effects degrading the

cavity pressure.

Studies on Underfilling ComponentsWith Area Array Solder Terminals in SurfaceMount Technology

IntroductionChip-Scale-Packages (CSP) have area array termi-nals placed on the components bottom sidemade of small balls of solder. Up to now, the useof underfill (UF) for them is not established inconventional manufacturing routes. As a result of a thermomechanical mismatch between theCSP-component (Si-chip) and the PCB, thermalcycling will initiate fatigue cracks in the solderballs. The result is that CSP-components areoften the reliability-limiting components inelectronic assemblies.For Ball-Grid-Arrays (BGA), component underfil-ling is conceivable if the application requires highreliability at simultaneously high stress. It makessense to underfill large-area, non thermally

matched systems. Underfilling is even beingproposed for the larger SMD-types, the BGA,when the relevant components are exposed toharsh environmental conditions, e.g. electronicsfor automotive applications.The potential of underfilled CSP and BGA com-ponents to increase product reliability has up tonow not been fully utilised. One reason for thishas been the lack of fundamental studies on therequirements of the special underfill materialsand on process reliability.

ObjectiveThe main objective of the project was to qualifyunderfill materials which are suitable forunderfilling CSP and BGA components andwhich can withstand 2000 temperature cycles(–40° C°/ +125° C) with a dwell time of 30minutes on each temperature level.The underfilling of CSP and BGA componentswith area array lead free and lead containingsolder terminals in surface mount technology hasbeen systematically studied and evaluated. Oneof the goals of the research was to define theparticular requirements that have to be put onCSP/BGA underfill materials and to estimatewhat level of process reliability for underfillingcan be achieved. The knowledge and experiencewith flip chip underfilling could not be directlytransferred to CSP and BGA assemblies due tothe differences in material combinations andgeometry of the joint gap as well as thedifferences in the nature and magnitude of thestress. Ageing and stress tests on test assemblieswith commercially available and alternativeunderfill materials highlighted the specificadvantages of underfilling CSPs and BGAs.

The studies had been realized in cooperationwith the „Fraunhofer-Institut fuer Fertigungs-technik und Angewandte Materialforschung“(IFAM), the „Institut fuer Aufbau- undVerbindungstechnik der Elektronik“, TechnischeUniversitaet Dresden and the Fraunhofer-Institutfuer Siliziumtechnologie (ISIT). The authors wouldlike to acknowledge the financial support for thiswork by the German Federal Ministry ofEconomics and Labour (AiF-project 13.138B).



Figure 1:Layout of the test PCB.

ResultsSimulations to specify underfill material properties

First of all a simulation was carried out. Theobjective of this simulation was to characterisean ideal underfill material and to derivethermomechanical requirements as an aid topreselecting suitable alternative polymers forunderfilling. The finite element method was usedfor the calculations. Prediction of the lifetimewas carried out using the relationship of Coffin-Manson.The simulation results showed that stiff underfillsincrease the lifetime and equalise the stress onthe solder joints. On the other hand, there is anincreased risk of cracks forming in the Si-chipand other defects (e.g. delamination). It is hencerecommended to select an underfill with amodulus of elasticity E not larger than necessaryto guarantee the required lifetime of the solderjoints.The effect of the coefficient of thermal expansionof the underfill is considerably greater for stiffunderfills than it is for soft underfills. The opti-mum value depends on the stiffness of theunderfill. In order to avoid additional tensile andcompressive stress on the solder joints betweenthe chip and PCB, it is recommended to have asoft material such that the coefficients of thermalexpansion α of the underfill and solder areapproximately the same: αUF ≈ αsol. For a very stiff underfill it is recommended thatthe coefficients of thermal expansion CTE andthe modulus of elasticity E of the underfill andPCB are approximately the same: αUF ≈ αPCB andsimultaneously EUF ≈ EPCB.In this situation the underfill and PCB form ahomogenous clamp around the solder terminalwhich reduces the undesired stresses in thesolder joint and thus increases its lifetime.

Screening for suitable materialsA search was carried out to screen alternativematerials that were commercially available. Fouralternative materials matching the requirementsfrom the simulation were chosen. Thesematerials, along with the other underfills, were

subjected to a screening procedure in order tomake a preselection. The objective of thisscreening was to qualify a limited number of the numerous underfills and alternative materialsfor underfilling original components. After all results came in, an evaluation matrixwas drawn up in order to define 8 materials forfurther testing on the test assemblies. The fourcriteria “CTE value”, “reworkable”, “flowbehaviour at 70° C” and “alternative material”were identified as key differentiating and selec-tion criteria for this project. A low CTE value isimportant for the automotive sector (temperatureshock test load). For the consumer productsector, a high CTE value (mechanical shock load)and a reworkable underfill are advantageous. The underfill materials that were used to buildthe assemblies had key properties in thefollowing ranges:• CTE value: 27 ppm/K below Tg up to

229 ppm/K above Tg

• Glass transition temperature: 9° C to 144° C• Reworkable underfill materials: two underfills.


Figure 2:FFBGA1152/WUF after 1250 cycles TS -40/+125° C.

Figure 3:FFBGA1152/UF after 2000 cycles TS -40/+125° C.

Test assembly manufacturing and testing procedureµSMD, CSP and BGA assemblies were selected inorder to have maximum variation of thecomponents. The respective components canhowever be viewed here as each being represen-tative of a type of component. The assemblieswere soldered with lead-free solder and alsolead-containing solder (figure 1). They wereunderfilled and the initial state was characterised.After exposure to temperature shock cycles (TS, -40° C / +125° C, with 30 minutes dwelltime on both levels) all the components wereelectrically tested at room temperature after 30,60, and 125 hours and then every succeeding125 hours. Metallographic cross sections havebeen prepared and analysed for selectedsamples.

Reliability investigation by temperature shock test cyclingThe properties of the underfill materials have asignificant influence on the very complex loadconditions of the solder contacts. Materials witha high stiffness lead to a significant increase oflifetime due to a more uniform stress acting onthe contacts. On the other hand there is anincreased risk of cracks in the silicon chip andother defects (e.g. delaminations etc.). Therefore,the E-modulus of the underfill materials shouldbe chosen not higher than it is really needed forthe guarantee of the required lifetime of thesolder contacts. The influence of the coefficientof thermal expansion (CTE) is much moresignificant when underfill materials with highstiffness are in use compared to applications with lower stiffness materials.One underfill was shown to be the most suitablefor most of the components that were studied.The defined target to withstand 2000 temperatureshock test cycles (TS) was essentially fulfilled(figure 3). The reference samples of the samecomponent type without underfill (WUF) failedafter just 1250 cycles (figure 2). A lower CTE incombination with a high Tg makes them verysuitable for the application under study.For the underfilled assemblies there was a cleardifference between the reliability of WL-CSPsoldered with lead-containing and lead-freesolder (figure 4 and figure 5). Temperature shocklifetime of the lead-free soldered componentswas much shorter. This may be due to differen-ces in the composition of the solder paste and tothe differing residues (contaminated PCBsurfaces) as well as to the observed failuremechanisms. The electrical tests on lead free WL-CSP components without underfill and withseveral underfills showed that there were veryearly failures (< 100 cycles). In addition to thealready known causes of failure such as crackformation in the solder and detachment of theunderfill from the component and PCB a newcause of failure was observed. Some materialscause damage to the overall system on the PCB.Tensile stresses occur in the solder at hightemperatures which are larger than when lead-containing solder is used. Lead-free solders are



Figure 4: Fatigue life: WL-CSP

(lead-containing) after TS -40/+125° C.

10 100 1000

com

po

nen

t fa

ilure

pro

bab

ility

(%

)

number of temperature cycles

WL-CSP lead-containing

1

2

5

10

20

30

40

50

60

70

80

90

95

98

99

WUFUF1UF2UF3

UF4UF6UF7UF8

more creep resistant and hence less compliant.The tensile stress within the solder joint deformsthe copper traces in Z-direction, obviously causedby the high CTE of the underfill. Cracks form atthe periphery to the microvia due to high defor-mation of the pad in the Z-direction, additionally,delamination is observed beneath the pads dueto Z-axis expansion and detachment of theunderfill from the solder resist (figure 6). Thesolder joints’ strength to the copper pad via theintermetallic phases is larger than the adhesionof copper to the FR4; therefore, the copper padis necessarily deformed during temperatureshock load while delaminating from the FR4. Due to the cyclic tension and compression of thesolder joint, the periphery of the microvia isstressed by cyclic bending; thus, fatigue fractureis caused after a short time.As a measure of the underfill performance, aranking of the underfill materials has been set upwith respect to the component type.The underfill that was chosen from the favourably-priced alternative materials is in the lower middleof the ranking. This material may be taken as aneconomic alternative, provided the requirementson reliability are of less importance.However, not every underfill is equally suitablefor all types of components. An underfill for onecomponent type may be in the top group, foranother at the end of the ranking.The repairable underfill materials are at thebottom of the ranking. The ability to be repairedand increased reliability after temperature shocktest cycles cannot be combined in the materialsunder test.It must however be emphasised that the mainconcern of this project was the reliability intemperature shock test cycles. This is a keyrequirement for automotive applications. For“hand-held” applications with the mainrequirement to withstand mechanical shock, the ranking of the underfill materials may betotally different.

Selected underfills were applied to industrialelectronic control assemblies. These systems weresubjected to temperature shock test cycles aspart of the internal qualification programme by

the industrial partners. Intermediate results after1000 cycles showed similar results to the testassemblies used in this project. Underfill materialsthat proved suitable on the test assemblies alsoshowed no failures on the industrial demonstra-tion systems. Underfill materials that showedunsatisfactory reliability on the test assembliesshowed the same failure behaviour (such ascracks in the laminate and in the soldered joints).Therefore, transfer of the results to industrialapplications is possible and application in seriesproduction can be expected soon.


Figure 5:Fatigue life: WL-CSP

(lead-free) after TS -40/+125° C.

10 100 1000co

mp

on

ent

failu

re p

rob

abili

ty (

%)

number of temperature cycles

WL-CSP lead-free

1

2

5

10

20

30

40

50

60

70

80

90

95

98

99

WUFUF1UF2UF3

UF4UF6UF7UF8

Figure 6:Fatigue life: WL-CSP/UF (lead-free),

microvia removedafter 1000 cycles TS -40/+125° C.


lead, cadmium, and mercury – are extremelytoxic. Similar hazardous materials and substancesare used in production of popular mass marketproducts such as telephone, radio, TV, faxmachines, video players, CD players, mobilephones etc.

Decades of irresponsible use of hazardous chemi-cals and substances used in manufacturing ofelectronics goods resulted in highly contaminatedgroundwater and community health problems ina number of countries, including EU memberstates. Further, electronics production, seen overthe entire life cycle of the products, contributesto a number of environmental problems,including ozone depletion, global warming,acidification, human toxicity, fauna and floratoxicity, resource depletion (materials and energycarriers), and smog.

On the example of computers, it is estimatedthat more than 60 million new PCs enter themarket and 12 million are disposed of each yearin the European Union. Add the unknownnumbers of old computer products hidden inbasements or garages, and the result is a stagge-ring mass of plastic, metal, chemical, and glass"junk". The waste will contain more than 4 billionpounds of plastic, 1 billion pounds of lead, 1.9million pounds of cadmium, 1.2 million poundsof chromium, and nearly 400,000 pounds ofmercury. Amazingly, less than 10 % of outdatedcomputer products are refurbished or recycled. E-waste has become one of the world's fastestgrowing and most toxic waste streams. The indu-stry depends on unimaginative solutions such asland filling and incineration as disposal methods.This leads to even more pollution and greaterthreats to human health.

Scientists and health professionals have longunderstood that lead causes serious healthproblems, including brain damage as well asblood and neurological disorders. Specificallyneurological development of unborn babies andyoung children are at risk when exposed to leadin food chain. It is widely used in manufacturedproducts, however, because of its strength andlow melting temperature. Lead is imbedded intothe glass of CRT monitors as a radiation shield,


Lead-Free Soldering for RoHS Compliance –Challenge, Task and Chance

Imposition of change in electronics production When people think of their most popularelectronics goods used on day to day basis, theymay not understand the environmental impactsand externalities of these products’ life cycle. For example, computers and their components –semiconductor chips, circuit boards, and diskdrives – are made from more than 1,000 materials.Many of these materials – such as solvents,gases, acids, brominated flame retardants, plastics,

Figure 1:Lead-free wave soldering; transport direction (from right to left).

a) chip wave instandby mode.

b) glass plate over chip wave showing flux activity.

c) on laminar second wave, nomore flux avtivity.

e) wave soldering R0805, nitrogen inert gas:no bridging, few solder balls (right).

d) wave soldering R0805, air: sol-der bridging (left).

used as solder on circuit boards, and incorpora-ted into computer parts.

Thus, it is high time that the EU acts. The policyformations of the Integrated Product Policy basedon life cycle analysis, such as the WEEE and RoHSdirectives, are a step in the right direction toaddress the environmental issues in electronicsproducts lifecycle from cradle to grave. By cradleto grave is meant the life cycle spanning fromraw material extraction all the way to end of liferecycling, recovery, disposal. Since February 13,2003, when two european guidelines were setinto action, a new era started for electronicsproduction: The new EU legislation on electronicwaste stream and restriction of hazardous sub-stances presents consequences for all partiesinvolved in the electronics products supply chain:OEM manufacturer, contract assembly houses,equipment manufacturer, solder and fluxmanufacturer, PCB manufacturer, componentmanufacturer and distributor, and otherconsumables (gas/nitrogen, tooling) manufacturer,and, last not least, recycling companies andcommunal waste management.

However, the environmental problems will besolved the quickest and in the most expedientmanner if the industry is not only imposed a setof more stringent norms but is actively supportedin the transition process. The problems arising ofthe enforced laws are especially harsh for SMEassembly houses:• Substantial cost factor due to necessary

investments in new equipment • Incomplete availability of RoHS and process

compliant components• Lack of compatibility of lead-free processing

at higher temperature with existing devicespecifications

• Lack of experience with lead-free-specificinspection and repair routines

• strong deficits of personnel skills regardinglead-free soldering

• disruption of running commercial productionduring experimental introduction, feasibiltytests and in-house training lead-free technolo-gies not only in RoHS relevant, but also RoHSexempted applications.

Joint research for lead-free solderingwith ISIT

Together with a group of companies from theHamburger Lötzirkel, experiments were performedon industrial line wave solder systems at the sitesof equipment manufacturers. It was found thatunder air the solder on the second wave oxidizedso quickly, that passive SMDs (Surface MountedDevices) on the solder side formed frequentbridges between adjacent solder joints (figure1d), although the pad layout was in accord withcurrent recommendations. The reason was thatthe flux layer was consumed completely on thefirst wave (figures 1b to 1d). Under nitrogen,there was no bridging, because there was nooxidation on the second wave (figure 1e).

More wave solder experiments under inert gasconditions were performed with different alloys,also in comparison with tin-lead. Systematic testswith over 200 boards showed that for SMD, nonew defects appeared for lead-free when thedesign recommendations as known for tin-leadwave soldering were used. Indeed, design aidslike solder thieves in the wake of the solder wave


Figure 2:wave solder applications under inert gas.a) SnAg3.5.b) SnCu0.8Ni.1.

prevent bridging for lead-free alloys just as wellas for tin-lead, as shown on a QFP44 with 0.8mm pitch (figure 2a). Even design tolerancescould be shown: Where pad design intended forreflow soldering was placed on the wave solderside next to the dedicated wave solder design,there were no missed pads found (figure 2b):wave design/top row vs. reflow design/bottomrow). This is not to be misunderstood as arecommendation for small pads and narrowspacing in lead-free wave soldering, howeverwhen process verification is done, there is sometolerance left with regard to the originalrecommendation, e. g. from Philips Guidelinesfor Pad Design.

However, design is crucial at THT (Through-Hole-Technology) with high thermal demand. This isshown in figures 3a and 3b. The contact timewas rather short, only ca. 1.5 s. The massivecopper rail conducts the solder heat away fromthe joint area, and the vertical fill is insufficient(figure 3a). A modified rail however, with sawcuts to increase thermal resistance, keeps theheat closer within the joining area. The result isthus an acceptable vertical fill (figure 3b).

As to reduce green house effect gases, alcoholbased solvents are also to be reduced in accordwith Council Directive 1999/13/EC of 11 March1999 on the limitation of emissions of volatileorganic compounds (VOC) due to the use oforganic solvents in certain activities and installa-tions. Although up to now this directive does notapply to electronic assembly, there is a tendencytowards low-VOC or VOC-free soldering flux. Foronce, to make advantage of the higher activitywhen soldering with lead-free alloys at highertemperatures, secondly to reduce hazardous(flammable) chemicals in the productionenvironment, and of course to reduce greenhouse effect emissions altogether.

For selected flux formulations, ISIT has investiga-ted long term corrosion effects from flux residues by means of a standardized SIR (SurfaceInsulation Resistance) test in accord with IPC-TM650, using the IPC-B24 comb structure testcoupon, humid heat at 85° C/85 %rH, 50 V dccontinuous voltage and 100 V for the resistancemeasurement. Figure 4a shows the resistance vs.time diagram after 168 h, figure 4b the combstructure as inspected after the test, with noindication of dendrites or other harmful residues.During the one week test period, the resistancenever dropped below 1 GΩ for all test couponsrun over the spray fluxer, regardless if they wereturned to point upwards with the fluxedstructure, or if they were left with the structuredownwards over the solder wave. This meansthat all tested formulations passed therequirements for no clean flux in accord withIPC-J-STD-001 and -004.

Assistance for electronics manufacturersThe process step of lead-free soldering in itself is already a manageable task, though to bemastered with narrow process tolerances.Assistance for this step in electronics productionis given e. g. by equipment manufacturers forindividual users. However, there is such greatshort term demand by industry for help andassistance in making the transition for conformitywith the IPP (Integrated Product Policy) andspecifically WEEE (Waste Electrical and Electronical



Figure 3:THT current railwave soldered with SnCu0.8 Ni0.1

a) b)

Equipment) and RoHS (Restriction of the Use ofcertain Hazardous Substances) legislations, thatLEADFREE will not be able to satisfy the entirehuge demand across Europe alone. A 2004 study from Technikum Wien says that over 40 %of electronics manufacturing companies inAustria and Germany are only starting their RoHStransformation activities in 2005 or even later.These companies are in grave danger for disruptedproduction and last minute failures which canthreaten their existence. Fraunhofer ISIT hascontributed to over 30 regional and internationalnetworking events to give information ontechnology and discuss transformation issues.

These events provided efficient feedback fromdesign, production and logistics departments outof the rows of participants. They showed theneed for external practice. Thus the ISIT Qualityand Reliability group opted to broaden itsspectrum of services and started activities toimplement a full scale production line for trainingindustrial personnell. This line will make use ofthe in-depth ISIT know-how in temperature mea-surement and solder process simulation, and ofthe experience gained with test board designand handling. The production environment willfurther incorporate the since long available ISITrework center, so that e.g. component fitness forthe increased thermal load in lead-free solderingcan be tested from storage via double sidedreflow to wave or selective soldering, all the wayto multiple rework in one facility, and then testedfor integrity.

Life Environment LEADFREE: Implementationof a “lead-free training line“ in ISITThe solution proposed is a non-for-profit, pre-competitive European competence centre fordemonstration, training and exercises to be used

by European electronics manufacturers, whobring their own materials and test vehicles topractice with state-of-the-art lead-free solderingequipment, assisted by scientific engineeringsupervision and analysis including hands-ontraining.

An innovation lies in the approach to mediatethis environmental and product friendly approachalso to single clients, thus presenting thepossibility for SME to practice on their own dis-cretion without the need to prior investment.The aim is to assist in evolution of sustainingtechnology in economically weak regions. In thisway, the acceptance of environmental goals willbe further increased, when it is demonstratedthat environmental and economic goals do notexclude each other.

With the assistance of IZET, the aspect ofreproduction and dissemination is covered by this partner experienced in marketing oftechnological infrastructure and possibilities on a european scale. Furthermore, IZET will focus onthe project management which will be a difficulttask with the view on the shear number ofanticipated 300 SME clients taking part in thetraining and exercise actions. Thus, ISIT can focuson the aspects of skills and technology transfer.

For this goal, ISIT has applied for funding by theLIFE ENVIRONMENT programme to establish afully functional industrial scale production line,which is to be set up in the well controlledenvironment based under the wafer fab facility.Complemented by the analytical and qualifyingtest methods provided by ISIT, this line will assistassembly producers as well as componentmanufacturers in qualification of materials andprocesses for environmental friendly products.


Figure 4:SIR test result – copper comb after 168 h in environmental chamber at 85° C/85 %rel.H.a) Resistance vs. time diagram.b) Inspection after test shows clean surface.

0 50 100 150 200 250

Surf

ace

Res

ista

nce

/Oh

m

Time/h

Comb Structure: IPC-B-24, Cu 168h, Environment 85° C, 85 %r Pre-Voltage: 50V Mesurement-Voltage: -100V

100M

1G

10G

100G

1T

Installation and Ramping-up of a Lithium-Polymer Rechargeable Battery Production Line

Re-chargeable batteries enter more and morefields of every-day life. Portable electronicdevices, such as mobile telephones, notebooks,walkmen etc., rely on accumulators for theirpower supply. Other applications with a heavilygrowing market potential are smart tags or smartlabels that are self-sufficient in power. New accu-mulator developments are also expected for allkinds of vehicles from automobile to electricallyassisted bicycles and wearable electronics. Leadaccumulators, nickel-cadmium (NiCd), nickelmetal hydride (NiMH), re-chargeable alkali-manganese cells and lithium systems offer a widespectrum as regards the range of performance,the quality and the prices.

It is the lithium ion accumulators in particular onwhich developments are focused since they pro-vide the highest energy density of all availablesystems. However, this advantage is dearly "paidfor". The liquid electrolytes used in the currentlyavailable lithium ion accumulators are sensitive tohydrolysis and require a high technological input.A rigid metal housing e.g. is therefore essentialfor this type of accumulator.

Not only does the hermetic metal encasement ofthe lithium ion accumulators, which can take upto 30 % of such an accumulator's weight,reduce the effective gravimetric energy density.

Apart from its disadvantageous weight, the rigidencasement also considerably reduces the free-dom to adapt its shape to the small size ofmodern and optimized systems into which itwould have to be fitted. Some potential applica-tions ask for mechically flexible accumulatorswhich cannot be realized by utilizing a rigidhousing.

Great efforts have therefore been made at inter-national level, to lessen the problem of the liquidelectrolyte by housing it in a sponge-like matrixwhich acts as a carrier or by gelifying. Apart fromincreasing the safety level, the electro-chemicallyactive layers as well as the housing can thus bemade as foils. Work has been going on the relevant systems for several years now, but onlynow first product are brought into market. The reason is that the problems arising whentransferring the lab-scale production to industriallevel has been underestimated.

The new development in lithium polymer techno-logy carried out by Sollith Batteries/Fraunhofer-ISiTwas driven by the above mentioned marketdemands:

• Reduction of weight• Improved safety for the end user• Increased flexibility in dimensions and capacity

Representative Results of WorkIntegrated Power Systems


Inserting battery body intopackaging foil

Drying of batteries

Adding of electrolyte underinert atmophere

Closing of pouch

Homoginization

Lamination of electrode tapesto current collectors

Punching out battery elementsfrom rolls

Stacking of battery elements

Lamination of bicells

Ultrasonic welding of tabs

Film Production Film processing, cell fabrication Packaging

Preparation of slurries fortapecasting

Tapecasting of- Positve electrode- Negative electrode- Separator

Pre-processed expanded metal

Storage and quality control Evacuation and final sealing Formation

Figure 1:Process flow

of Sollith Batteries‘Lithium polymer

rechargeable batteriesproduction line.


• Reduction of production costs even atmoderate numbers of customer specificaccumulators

• Opening of new fields of application by pro-duction of thin, large-area accumulators

Reduction of weight and improved safety areachieved by the specific set-up of Sollith Batteriescells. The abandonment of the rigid metalhousing leads to an improved gravimetric energydensity. Additional safety is coming from theimmobilization of the liquid electrolyte in apolymer matrix and in particular from the set-upof the separator. It contains a solid state ionicconductor as ceramic filler that leads in combi-nation with the immobilized electrolyte to amechanically stable separator layer with highionic conductivity. The mechanical stability of the separator is under safety aspects of greatimportance because it protects against internalshort circuits in the battery due to e.g. dendritegrowth from lithium metal deposition at theanode in case of overcharging. The use of a foilbased housing additionally leads to improvedsafety because in case of overheating of thebattery, leading to gas development, explosionsare avoided. The polymer battery simply opensalong the seal. In case of rigid metal housings anexpensive relief valve or a burst protection has tobe provided.

The improvements in flexibility in dimensions aswell as in capacity is a problem associated withproduction set-up. This is accounted for by SollithBatteries by a new production concept in whichalmost all components of the accumulator arestamped out in the required size from pre-pro-cessed foils. The thus obtained components arethen joined together to so-called bicells by lami-nation. For given lateral dimensions the capacityof a cell can then be achieved by stacking of theneccessary numbers of bicells. The housing isrealized in foil technology as it is known frompackaging of pharmaceuticals or food.

Sollith Batteries GmbH (Itzehoe) and BullithBatteries AG (Munich), its partner company, are

both spin-off companies out of ISiT with SollithBatteries located in the direct neighbourhood ofthe Fraunhofer-ISiT. The ISiT is research partnerand licenser for both companies. Within the year2004 Sollith Batteries GmbH has carried out thefinal equipment installation and the ramping-upof a lithium-polymer rechargeable battery pro-duction line. For the first time a completely newproduction concept addressing to flexibility incustomized design of rechargeable batteries hasbeen realized.

This line allows for the production of prismaticcells in the range of:

The basic process flow for the production Lithiumpolymer rechargeable batteries realized by SollithBatteries is shown in figure 1.

Thickness

Cell length

Cell width

2

55

40

Minimum

6

140

105

Maximum(mm)

Figure 2:Production of SollithBatteries lithiumpolymer rechargeablebatteries.



Important Names, Data, EventsAnnual Report 2004


Lecturing Assignments atUniversities

H. Bernt:Halbleitertechnologie I und II, Technische Fakultät der Christian-Albrechts-Universität, Kiel

A. Heuberger:Lehrstuhl für Halbleitertechnologie,Christian-Albrechts-Universität, Kiel

Memberships inCoordination Boards and Committees

T. Ahrens:Member of ELF NET (EuropeanLeadfree Network)

T. Ahrens:Coordinator of AOI-Anwenderkreis(Automated Optical Inspection)

T. Ahrens:Member of DVS FachausschussLöten

T. Ahrens:Member of DVS FachausschussMikroverbindungstechnik

T. Ahrens:Member of Hamburger Lötzirkel

W. H. Brünger:Member of Steering Committee:Electron, Ion and Photon Beamsand Nanofabrication, EIPBN, USA

W. H. Brünger:Member of VDI Fachausschuss:Maskentechnik, VDI, Düsseldorf

W. H. Brünger:Section Head: Micro and NanoEngineering, MNE 04, Rotterdam

J. Eichholz:Member of MEMSTAND WorkshopInternational Steering Committee

A. Heuberger:Advisory Editor of InternationalJournal of SemiconductorManufacturing Technology;Microelectronic Engineering

A. Heuberger:2. Chairman of an InternationalConference on Micro Electro,Opto, Mechanic Systems andComponents

K. Pape:Member of VDI FachausschussAssembly Test, VDI, Frankfurt

K. Pape:Member of BVS, Bonn

K. Pape:Member of FED

W. Reinert:Speaker of working group „Waferlevel packaging“ in ZVEI

W. ReinertMember of Arbeitskreis A 2.4Drahtbondtechnik, DVS

M. Reiter:Member of Gf Korr “ArbeitskreisKorrosionsschutz in der Elektronik“

M Reiter:Member of “Arbeitskreis Lotpasten“

M Reiter:Member of “Arbeitskreis Bleifreie Verbindungs-technik in der Elektronik“

M Reiter:Member of “Industrie-ArbeitskreisKnow-How-Transfer mikrotechnischer Produktion“

G. Zwicker:Head of FachgruppePlanarisierung/ FachausschussVerfahren/ FachbereichHalbleitertechnologie und –fertigung der GMM des VDE/VDI

Distinctions

Rainer Hintsche (ISIT), Walter Gumbrecht (Siemens),Roland Thewes (Infineon)Deutscher Zukunftspreis 2004,Preis des Bundespräsidenten für Technik und Innovation:Labor auf dem Chip – elektrischeBiochiptechnologie, Berlin,November 11, 2004

Peter MerzMAZ level one Award:Glass Flow-Process for Custom-sized microlenses,Hamburg, June 17, 2004

Important Names, Data, Events


Cooperation withInstitutes and Universities

Universität Autonoma de Barcelona,Spain

Hahn-Meitner-Institut, Berlin

Robert-Koch-Institut, Berlin

Rijksinstituut voor Volksgezondheiden Milieu, Bilthoven, Netherlands

Technische UniversitätBraunschweig, Institut für medizinische Informatik

Veterinary and AgrochemicalResearch Centre, Brüssel, Belgium

Cambridge University, UK

Organisatie voor ToegepastNatuurwetenschappelijk, Delft, Netherlands

Rutherford Appleton Laboratories,Didicot, UK

Technische Universität Dresden,Institut für Halbleiter- undMikrosystemtechnik

VTT, Espoo, Finland

Fachhochschule Flensburg

University of Gdansk, Poland

University of Greenwich, UK

Ernst-Moritz-Arndt-Universität(EMAU), Greifswald

CEA Leti, Grenoble, France

UniversitätskrankenhausEppendorf, Hamburg

Universität Hamburg, Abteilung fürBiochemie und Molekularbiologie

Universität der Bundeswehr,Hamburg

BAE SYSTEMS AdvancedTechnology Centre, Hamshire, UK

Fachhochschule Westküste, Heide

Technical University of Budapest,Department of ElectronicTechnology, Hungary

Technische Universität, Ilmenau

Joint Research Centre Ispra, Italy

Institut für Fügetechnik undWerkstoffprüfung (IFW), Jena

Christian-Albrechts-Universität,Technische Fakultät, Kiel

Fachhochschule Kiel

MIMOS, Kuala Lumpur, Malaysia

École Polytechnique Fédérale deLausanne, Switzerland

IMEC, Leuven, Belgium

University of Linkoeping, Sweden

CNRS-Université Claude Benard,Lyon, France

Consejo superior deInvestigaciones Cientificas, Madrid, Spain

Universität, Madrid, Spain

Max Planck Institut fürPolymerforschung, Mainz

Institut für Diabetesforschung,München

Wehrwissenschaftliches Institut,Munster

CSEM, Neuchâtel, Switzerland

Safety Equipment DevelopmentAB, Ösköldsvik, Sweden

SINTEF, Oslo, Norway

Universität Oulu, Finland

Centre National de la RechercheScientifique, Pa laiseau, France

Universtity of Pavia, Italy

National Inst. for NBC Protection,Pribram, Czech Republic

Royal Institute of Technology(KTH), Stockholm, Sweden

Swedish Defence Research Agency,Stockholm, Sweden

VTT, Technical Research Center ofFinland, Tampere, Finland

VDI/VDE-TechnologenzentrumInformationstechnik, Teltow

LAAS-CNRS, Toulouse, France

Centre d’Etude le Bouchet, Vert le Petit, France

Fachhochschule Wedel

Technische Universität, Wien, Austria

Trade Fairs andExhibitions

SMT Hybrid Packaging 2004. System Integration in MicroElectronics, Exhibition andConference, June 15 – June 17, 2004,Nürnberg

Optatec 2004.7. International Trade Fair forFuture Optical Technologies,Components, Systems andManufacturing, June 22 – June 25, 2004,Frankfurt/Main

Electronica 2004.21. International Trade Fair for

Components and Assemblies inElectronics, November 9 – November 12, 2004,München

Miscellaneous Events

“Aspekte modernerSiliziumtechnologie” Public lectures. Monthly presenta-tions, ISIT, Itzehoe

ISIT presentation at BMBF Kick-off conference “Mikrowelten – Zukunftswelten”,February 4 – February 5, 2004,Berlin

Der Lötprozess in der Fertigungelektronischer BaugruppenSeminar: March 1 – March 3 andOctober 18 – October 20, 2004,ISIT, Itzehoe

SMT-Rework-Praktikum auch mitbleifreien LotenSeminar: April 20 – April 22 andNovember 2 – November 4, 2004,ISIT Itzehoe

Manuelles Löten von SMT-Bauelementen auch mitbleifreien LotenSeminar: April 20 – April 22 andNovember 2 – November 4, 2004,ISIT, Itzehoe

12. CMP Users MeetingApril 23, 2004, Forum amDeutschen Museum, München

Bleifreie LöttechnikSeminar: May 5 – May 6, 2004,ISIT, Itzehoe

Regular Europractice Workshop“Microsystem Production inEurope”, May 25 – May 26, 2004,Hamburg/Itzehoe

ISIT presentation for HeideSimonis and an internationaldelegation of ambassadors. Speaker: Prof. Anton Heuberger,June 24, 2004, ISIT, Itzehoe

Day of open house together with Vishay, SMI, SollithBatteries, Condias and IZET, August 21, 2004, Itzehoe

13. CMP Users MeetingOctober 15, 2004, TU-Dresden

Press conference “Hohe Investi-tionen in Zukunftstechnologienam High-Tech-Standort Itzehoe”. Speakers: Dr. Bernd Rohwer(Wirtschaftsminister des LandesSchleswig-Holstein), Dr. GeraldPaul (President and COO of VishayIntertechnology) and Prof. AntonHeuberger, October 27, 2004, ISIT,Itzehoe

MEMS workshop: Vacuum WaferBonden.ZVEI – Seminar, December 17, 2004, Stuttgart


Journal Papers and Contributions toConference

H. Etzel, H. Oertel, R. Dudde, P. Staudt:Analysis of Wafer Process Duration for ab initio Calculationof Capacity, Throughput andBottleneck Equipments in a WaferFab. Proceedings Annual,IEEE/SEMI ASMC, 2004

M. Gabig-Ciminska, H. Andresen,J. Albers, R. Hintsche, S. -O. Enfors:Identification of PathogenicMicrobiol Cells and Spores byElectrochemical Detection on a Biochip. Microbiol Cell Factories,3:2, April 16, 2004

M. Gabig-Ciminska, A. Holmgren,J. Albers, R. Hintsche, M. Los, A. Czyz, G. Wegrzyn, S. -O. Enfors:Detection of BacteriophageInfection and Prophage Inductionin Bacterial Cultures by Means of Electric DNA Chips. AnalBiochem., January, 324(1), p. 84 – 91, January 1, 2004

M. Gabig-Ciminska, A. Holmgren,H. Andresen, K. Bundvig Barken,M. Wümpelmann, J. Albers, R. Hintsche, A. Breitenstein, P. Neubauer, M. Los, A. Czyz, G. Wegrzyn, G. Silfversparre, B. Jürgen,S. Schweder, S.-O. Enfors:Electric Chips for Rapid Detectionand Quantification of Nucleic Acids.Biosens Bioelectron., January, 19(6),p. 536 – 46, January 15, 2004

H. Jacobsen, E. Stachowiak, G. Zwicker, W. Lortz, R. Brandes:Metrological Assessment of theCoefficient of Friction of VariousTypes of Silica Using the MotorCurrent During ILD-CMP. Advancesin Chemical-Mechanical Polishing,MRS Symp. Proc. 816, K3.3.1, Warrendale, PA, 2004

T. Lisec, C. Huth, B. Wagner:Dielectric Material Impact onCapacitive RF MEMS Reliability. Proc.34. European Microwave Conference,p. 73 – 76, Amsterdam, 2004

T. Lisec, C. Huth, M. Shakhray, B. Wagner, C. Combi:Surface-Micromachined CapacitiveRF Switches with High Thermal Stability and Low Drift using Ni asStructural Material. Proc. 5thWorkshop on MEMS for Millimeter-wave Communications, MEMSWAVE2004, C33 – C36, Uppsala, 2004

G. Mörsch, G. Zwicker:Planarization with CMP for MEMS Fabrication. Semiconductor Manufacturing, p. 48 – 50, November, 2004

E. Nebling, T. Grunwald, J. Albers, P. Schäfer, R. Hintsche:Electrical Detection of Viral DNAUsing Ultramicroelectrode Arrays.Anal Chem., February, 76(3): p. 689 – 696, February 1, 2004

M. H. Poech:Schädigungsmechanismen in blei-freien und bleihaltigen Lötver-bindungen bei erhöhter Temperatur.GMM Fachbericht 44, „ElektronischeBaugruppen“, DVS/GMM 2004, p. 273 – 278, VDE Verlag GmbH,Berlin Offenbach, 2004

M. H. Poech:Modelling of Thermal Aspects ofPower Electronic Assemblies.Proceedings IMAPS Nordic AnnualConference, p. 120 – 125,Helsingor, Denmark, September 26 – September 28, 2004

W. Reinert:Vacuum Wafer Bonding Technology.Proceedings IMAPS Nordic AnnualConference, Helsingor, Denmark,September 28, 2004

H. Schimanski, Thomas Harder:Laserlöten von Silizium/Pyrexmittels Glaslot zur Kapselung vonMikrosensoren auf Waferebene.Plus-VTE Produktion von Leiter-platten und Systemen, Eugen G. Leuze Verlag, p. 1010, June, 2004

H. Schimanski, M. H. Poech:Untersuchungen zur Unterfüllungvon Bauteilen mit flächig verteiltenLötanschlüssen in der Ober-flächenmontagetechnik. Plus-VTEProduktion von Leiterplatten undSystemen, Eugen G. Leuze Verlag,p. 2118, December, 2004

L. v. Trotha, G. Mörsch, G. Zwicker: Advanced MEMS Fabrication UsingCMP. Semiconductor International,p. 54 – 56, August, 2004

X. Xie, D. Stüben, Z. Berner, J. Albers, R. Hintsche, E. Jantzen:Development of an Ultramicro-electrode Arrays (UMEAs) sensorfor Trace Heavy Metal Measure-ment in Water. Sensor and Actuators,Band 97, p. 168 – 173, 2004

G. Zwicker:Advanced CMP Technology andApplications. ECS Proc., Vol. 2004-11, p. 235 – 243, 2004

G. Zwicker, H. Jacobsen, W. Lortz,E. Stachowiak, R. Brandes:Characterisation of Oxide-CMPSlurries with Fumed-Silica AbrasiveParticles Modified by Wet-JetMilling. Proc. 9. CMP-MIC,p. 216 – 223, Marina del Rey,February, 2004

Talks and PosterPresentations

T. Ahrens:Lötqualität. Seminar: Der Löt-prozess in der Fertigung elektroni-scher Baugruppen, ISIT, Itzehoe,March 1 and October 18, 2004

T. Ahrens:Baugruppen- und Fehlerbewertung.Seminar: Der Lötprozess in der Fertigung elektronischer Bau-gruppen, ISIT, Itzehoe, March 2 and October 19, 2004

T. Ahrens:Was wird anders durch bleifreiesLöten. Seminar: Der Lötprozess inder Fertigung elektronischerBaugruppen, ISIT, Itzehoe, March 3and October 20, 2004

T. Ahrens:Bleifreies Löten: Nicht nur eine Prozess-, sondern auch eineManagementaufgabe. Seminar:Aspekte moderner Siliziumtechnolo-gie, ISIT, Itzehoe, March 3, 2004

T. Ahrens:Betriebszuverlässigkeit elektronischerBaugruppen. 7. Europäisches Elektro-niktechnologie-Kolleg, Technologienfür die elektronische Baugruppe,Mallorca, March 19, 2004

T. Ahrens:Bleifrei Reparaturlöten. Seminar:Manuelles Löten von SMT-Bauelementen auch mit bleifreienLoten, ISIT, Itzehoe, April 20 and November 2, 2004

T. Ahrens:Rework-Qualifikationen vor demSerienprozess. Seminar: ForumBleifreie Löttechnik, ISIT, Itzehoe,May 5, 2004

T. Ahrens:Reliability of Lead-Free Solder Joints.Conference: Status in Lead-freeElectronics Assembly Copenhagen,June 14 – June 15, 2004



H. Schimanski:Reparatur komplexer SMT-Bau-gruppen. Seminar: Manuelles Lötenvon SMT-Bauelementen, ISIT, Itzehoe,April 20 and November 2, 2004

H. Schimanski:Einführung in die bleifreie Reparatur.Finetech Workshop “GrüneReparatur”, Berlin, May 13, 2004

H. Schimanski:Beurteilung von bleifreienLötergebnissen mittel AOI und AXI.Finetech Workshop “GrüneReparatur”, Berlin, May 13, 2004

H. Schimanski:Rework-Strategien für bleifreiesLöten – Sichere Prozessführungdurch Optimierung und Festlegungder Arbeitsschritte. OTTI-Profiforum, Produktion elektroni-scher Baugruppen, Regensburg,May 24 – May 25, 2004

H. Schimanski:Unterfüllung von Bauteilen mit flächig verteilten Pb-haltigen und Pb-freien Lötanschlüssen inder SMD-Technik. 12. FED-Konferenz: Elektronik-Design Leiter-platten Baugruppen 2004, Neu-Ulm, September 18, 2004

H. Schimanski, T. Ahrens, J. Pontow, D. Prochota:Rework an bleifreien Elektronik-Baugruppen. Hilpert electronics Fach-seminar: “Lead-Free”, Baden-Dättwil, Switzerland, April 29, 2004

H. Schimanski, M.-H. Poech:Vom Wärmefluss in der Lötanlagezum optimierten Lötprofil. BleifreiForum der Peter Jordan GmbH,Offenbach, April 28, 2004

B. Wagner:Sensor Technologies and UserInterfaces for Ambient Intelligence.European Micro- and NanosystemsEMN04, MIMOSA Satellite Workshop,Paris, October 19, 2004

G. Zwicker:Wet-Jet Milling of Slurries. 12. CMPUsers Meeting, Munich, April 23, 2004

G. Zwicker, W. Schreiber-Prillwitz:Backside CMP for the Fabrication ofIntegrated Sensors. 13. CMP UsersMeeting, Dresden, October 15, 2004

G. Zwicker:Anwendung von CMP für dieMEMS-Fabrikation. Seminar: Aspektemoderner Siliziumtechnologie, ISIT, Itzehoe, November 3, 2004

G. Zwicker:Advanced CMP Technology and Appli-cations. 3. International Conferenceon Semiconductor Technology (ISTC2004), Shanghai, 2004

G. Zwicker, H. Jacobsen, W.Lortz, E. Stachowiak, R. Brandes:Characterisation of Oxide-CMPSlurries with Fumed-Silica AbrasiveParticles Modified by Wet-Jet Milling.9. CMP-MIC, Marina del Rey,February 24 – February 26, 2004


Diploma Theses

A. Hanisch:Entwicklung von ELISA’s aufMikroelektrodenchips zum Nachweis von Proteinen und Haptenen.Fachhochschule Wedel, February, 2004

S. Kreutzer:Konstruktion und Aufbau einesrechnergestützten Messplatzes zur Bestimmung der Schock-festigkeit von MEMS-Bauteilen undAufnahme einer Messreihe.Fachhochschule Lübeck, December,2004

M. Kröner:Extraktion von Materialparameternaus Resonanzmessungen.Fachhochschule Münster, October,2004

S. Kurnaz:Manuelles Reparaturlöten von THT (Through hole Technology) –Bauteilen mit bleifreiem Lot.Fachhochschule Wedel, February,2004

A. Nerowski:Entwicklung eines Herstellungs-verfahrens von elektrischenDurchführungen aus Silizium und Glas auf Waferebene.Fachhochschule Lübeck, October,2004

M. Oldsen:Entwicklung eines eutektischenAu-Si Verbindungsprozesses aufWaferebene.Fachhochschule Wedel, September, 2004

C. Wulf:Aufbau eines vollautomatisiertenVakuumprobermessplatzes zurCharakterisierung von mikromecha-nischen Drehratensensoren.Fachhochschule Lübeck, September,2004


General View on Projects

• Prozesse/ Verfahren für dieHerstellung ultradünner Trench-IGBTs auf sub-100µm Silizium-Substraten

• Entwicklung einer UBM/BCB Technologie fürWafer Level Packaging

• Fabrication of Si-Microstructuresbased on SOI-Wafers

• Prozessentwicklung undUnterstützung bei derProduktion von Philips-Wafern

• Prozessierung von Wafernmittels Silizium-Trockenätzenzur Erzeugung spezieller Si-Strukturen

• Fabrication of Capacitor Structures• Entwicklung von Post-CMP-

Reinigungsprozessen für die Fertigung von zukünftigenintegrierten Schaltkreisen in der Si-Technologie

• Evaluierung von Slurries zum chemisch-mechanischenPolieren von SiO2

• Schleifen und Rückseiten-polieren von Wafern für MEMS-Anwendungen

• Entwicklung vonPlatinwiderständen aufKeramiksubstraten

• Untersuchung an mikromecha-nischen Drehraten-Sensoren

• Herstellung und Replikation von großflächigen 3D-Nano-und Mikrostrukturen

• Entwicklung von kapazitivenHF-Schaltern

• Fertigung eines Spiegelarraysmit elektrischem Anschluss und Beurteilung der Mikro-spiegeltechnologie

• Entwicklung von piezo-elektrischen Schichten für Si-Mikroaktuatoren

• Design schaltbarer optischer Netze

• Fabrication, Assembly andTesting of a Miniature Two-AxisLaser Scanner and a High Voltage Amplifier

• Kostengünstige Herstellung vonMikrosystemen: Verbundtechnikvon Kunststoff und Silizium

• Herstellung mikrooptischerLinsenarrays aus Glas

• Herstellung mikrooptischerLinserarrays in Polycarbonat

• Entwicklung einesWasserstoffsensors

• Microsystems platform for Mobile Service and Applications – MIMOSA

• AMICOM: Advanced MEMS forRF and Millimeter WaveCommunications, Network of Excellence

• P-ML 2, Projection MasklessLithography; Development ofan Aperture Plate System

• Microsystem ManufacturingCluster, EUROPRACTICE AMICUS

• Customer Support and DesignCentre for PhysicalMeasurement Systems, EURO-PRACTICE CCMeSys

• Microactuator CompetenceCentre, EUROPRACTICE CCMicro

• MIMOS Training programmMEMS Design European Accessto Manufacturing Service forMEMS on SOI MicromachiningTechnologies

• Electric DNA Chips forBioprocess Control

• Nanoskalige elektrischeMessverfahren für portableAnalysesyteme nieder-molekularer Verbindungen

• Aufbau einer technologischenPlattform zur Erregerdiagnostikmit Elektrischen Biochips (TTZ Kiel)

• Intelligent Controll Assistent for Diabetes, INCA

• Chipkartenbestückung mit Grautonblenden

• Ultra-Thin Packaging Solutionsusing Thin Silicon

• Flip Chip Die Bonder for Ultra-Thin Silicon

• Untersuchung zur Unterfüllungvon Bauteilen mit flächig verteilten Lötanschlüssen in derOberflächenmontagetechnik,CSP Underfill

• Long-Term Stability of Vacuum-Encapsulated MEMS DevicesUsing Eutectic Wafer Bonding,VABOND

• Stressarme Montage vonSensoren und Mikrooptik –Komponenten mittelsMikroklebtechnik

• Evaluation of packaging concepts for the gyro-sensor,Gyrosil, BMBF

• Fertigung von Testwafern zurJustierung von Bestückungsanlagen

• Die elektronische Baugruppeder Zukunft

• Stressoptimierte Montage und Gehäusetechnik für mikro-mechanisch hergestellteSilizium-Drehratensensoren

• Ag thick Film Bumping onWafer Level

• Entwicklung einer AOIKalibrierprobe

• Thin Wafer Handling forBacksite Processing

• Volumeneffekte und technische Zuverlässigkeit vonbleifreien Lötstellen

• Oberflächeneffekte vonKomponenten zum bleifreienLöten

• Glassfritt Vacuum WaferBonding

• Finepitch solder flip chip on flex• Glaslotbonden mit

strukturierten Capwafern und Musterwafern

• Bewertung vonAufbaukonzepten für ein Leistungsmodul

• Assembly test on PCB• Qualitätsbewertung an blei-

freien Baugruppen• Musterfertigung von

Blendenkarten mit Soft-Blenden

• Hearing-Aids with RechargeablePower Supply, HARPOS

General View on Projects

Patents

H.J. Quenzer, A. Schulz, P. MerzVerfahren zur Strukturierung einesaus glasartigem Material bestehen-den Flächensubstrats, glasartigesFlächensubstrat und Verwendungdes glasartigen FlächensubstratsDE 102 41 390

H.J. Quenzer, B. WagnerAnordnung mit variabler KapazitätEP 1 307 398

H.J. Quenzer, A. SchulzSollösung zur Herstellung vonGlasbeschichtungen für elektrischleitende, zum anodischen Bonden einsetzbare MaterialienEP 1 407 487 B1

P. Staudt-Fischbach, H. J. Quenzer, J. EichholzParalleler Analog-Digital-Umsetzer mitSchwellenwertspannungs-EinstellungEP 0 771 077 B1

B. Wagner, H.J. Quenzer, X. TuoDurchstimmbarer Hochfrequenz-KondensatorEP 1 224 675 B1

Patents

P. Birke, G. NeumannPastöse Massen mit NanokristallinenMaterialien für elektrochemischeBauelemente und daraus hergestell-te Schichten und elektrochemischeBauelementeTW 195841

P. Birke, G. NeumannPastöse Massen mit anorganischen,flüssigen Leitern und daraus hergestellte Schichten und elektro-chemische BauelementeTW 195404

P. Birke, G. NeumannPaste-like masses for electro-chemical components, layers produced therefrom, and electrochemical componentsUS 6,706,441 EP 1 108 271

P. Birke, G. NeumannHerstellung von Elektroden,Elektrolyten und Protonenleitern in PastenformTW 189433

P. Birke, F. Salam-BirkeFilms for electrochemical components and method for producing the sameSG 88565

J. EichholzGrauton-Lithographie für raum-sparende A/D-WandlerEP 0 771 077

T. Lisec, S. Mühlmann, S. GrünzigPipettensystem und Pipetten-array sowie Verfahren zum Befülleneines PipettensystemsDE 100 52 819

T. Lisec, B. Wagner, H. J. QuenzerMicrosensor for measuring theposition of liquids in capillariesUS 6,748,804

T. Lisec, S. Mühlmann, S. GrünzigPipettensystem und PipettenarrayEP 1 344 028 B1

H.J. Quenzer, B. Wagner, B. WenkAssembly having variable capacitanceUS 6,700,299

H.J. Quenzer, B. WagnerMicroactuator arrangementUS 6,684,638


Contact

Please contact us for further information. We would be glad to answer your questions.

Fraunhofer-Institut für SiliziumtechnologieFraunhoferstraße 1D-25524 ItzehoeTelephone +49 (0) 48 21 / 17-42 11 (Secretary)Fax +49 (0) 48 21 / 17-42 50email [email protected]://www.isit.fraunhofer.de

Press and Public RelationsClaus WackerTelephone +49 (0) 48 21 / 17-42 14email [email protected]

Imprint

Editor Claus Wacker

Layout / SettingAnne Lauerbach and Team, Hamburg

LithographyTypoDesign GmbH, Hamburg

PrintingBeisnerdruck GmbH & Co KG, Buchholz, Nordheide

Photographs:Büro Deutscher Zukunftspreis: p. 6, p. 9 top right and bottom right, p. 10 left, p. 12, p. 18 bottom left

Photo Company Itzehoe: p. 14 right, p. 15 top right andbottom left, p. 16, p. 17 bottom, p. 21 top, bottom rightand bottom left/top, p. 33 bottom, p. 47 bottom, p 73

SMI Silicon Manufacturing Itzehoe GmbH: p. 19 top, p. 35

Uwe Tölle, Berlin: p. 9 top left, middle left and right

Vishay Semiconductor Itzehoe GmbH: p. 22, p. 23 top

Peter Wolters Surface Technologies GmbH Rendsburg: p. 17 top

All other pictures ISIT

Documents

Achievements and Results Annual Report 2004 › content › dam › isit › de › ... · Itzehoe (SMI). The outlines of a contract have been drafted that will enable SMI and ISIT