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By sharing our latest experiences, we can help anticipate

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be proud of. Agilent – achieve your best design.

Memory Design

Challenges Explained

Gordon Getty

Agilent Technologies

© Agilent Technologies, 2012

Agenda

1) The Future of Memory Technology

– Memory technology has hit a wall because of physics limitations- understand what

these limitations mean for your designs

2) New Logic Analyzer capable of capturing DDR4 data

– Is your equipment moving as fast as your designs? The Agilent U4154A AXIe-based

logic analyzer module provides the highest accuracy measurements on high-speed

digital systems operating up to 4 Gb/s with eye openings as small as 100 ps by 100

mV. Don’t let your designs be limited by the equipment you use to test them.

3) DDR Probing and Analysis Tool

– Memory system designers have huge concerns on probing meeting the high

bandwidth requirement for best signal fidelity. Understand the Agilent solutions

offered to make this as easy as possible for you so you can concentrate on solving

problems, not wondering where the problems are.

Hottest Memory Applications Computer System

Mobile and Wireless Applications

Servers-email, web,

database

DDR3

Notebooks, Desktops

DDR2/3

SD UHS-I slot

Smart phone

Consumer products

Graphics card

GDDR5 DRAMs

LPDDR2 DRAM

SD UHS-I card

- max storage

LPDDR1/2, DDR2, DDR3

Industry Roadmap

DDR3 1867 & 2133Mt/s - 2011

DDR4 (up to 3.2Gb/s, 1.2V) - 2012

Industry Roadmap

• DDR4

• LPDDR3

• Wide I/O (~12Gb/s)

•Faster data rate

•Lower DRAM cost

•Higher density

•Lower power

Current Memory Technology Types

Memory Technology Where Used?

Standard

DDR Double Data Rate

• Desktop Computing

• Servers

JESD79E, JESD79-2E,

JESD208, JESD79-3C

GDDR Graphics Double Data Rate

• Graphics Boards

• Embedded Systems (future)

JESD212

LPDDR Low Power Double Data Rate

• Mobile

• Embedded

JESD209A, JESD209-2

QDR Quad Data Rate

• Specialty QDR Consortium

Nand/Nor • Flash Memory JESD79-2, JESD79-3

e-MMC™/SD Embedded Multimedia Card

Secure Digital

• Managed Flash

• Mass Storage Devices

JESD84-B45

SD Card Association

Memory Technology Types

Memory Technology Where Used?

DDR Double Data Rate

• Desktop Computing

• Servers

DDR3

• Current speed = 2133 Mb/s

• May increase to 2.3 Gb/s

• Vdd options = 1.5, 1.35, 1.25

• First “3DStack”

DDR4 (2012)

• Current speed = 2.4 Gb/s

• Goal is to increase to 3.2 Gb/s

Big push to lower power

Memory Technology Types

Memory Technology Where Used?

GDDR Graphics Double Data Rate

• Graphics Boards

• Embedded Systems (future)

GDDR: Graphics boards for desktop computers

• Very high speeds

• Current speed = 6 Gb/s

• May increase to 8 Gb/s in 2012

• GDDR5:

• Point to point connection to help with signal integrity

• 1st to implement error feedback

Memory Technology Types

Memory Technology Where Used?

LPDDR Low Power Double Data Rate

• Mobile

• Embedded

LPDDR2

• Current speed = 800 Mb/s

• Fully specified to 1067 Mb/s

LPDDR3 (~Dec 2011)

• Goal = 1600 Mb/s

• Pin out compatible with LPDDR2

LLI (Low Latency Interface)

• Serial ASIC to ASIC low overhead memory bus

(MIPI alliance)

Memory Technology Where Used?

QDR Quad Data Rate

• Specialty

Nand/Nor • Flash Memory

Memory Technology Types

QDR (Quad Data Rate):

• Static memory, read/write to simultaneously

Nand: 100-1,000+ writes before failure

• Toggle

• ONFI –speed 400MT/s, BGA packages

Nor: ~100,000+ writes before failure

As memory size increases the number of writes before failure decreases

Memory Technology Types

Memory Technology Where Used?

eMMC/SD Embedded Multimedia Card

Secure Digital

• Managed Flash

• Mass Storage Devices

eMMC / SD (Managed): Can be embedded or removable

• eMMC = embedded multimedia card

• SD = removable flash

• Next generation = UFS, SDA UHS-II

Mb/s

ec p

er

Pin

Speed Doubles With Each Generation

Year

28

Gb

/se

c/c

hip

1.6

4.3

4.8

N

N+

1

N+

2

N+

3

N+

4

N+

5

N+

6

Generation

Gb

/s p

er

Pin

Memory is Finally “Boxed In” by Physics

# I/O Pins

Channel

Throughput

(GBytes/sec)

Signal Propagation

Physics

Faste

r

Signal Integrity Problems

Crosstalk

Loss

Reflection

Gb

/s p

er

Pin

Memory is Finally “Boxed In” by Physics

# I/O Pins

Channel

Throughput

(GBytes/sec)

Materials and Process

Physics

Wider

MFG issues

Materials

Reliability

Higher density

Solution? Go Faster & Go Wider

Gb

/s p

er

Pin

# I/O Pins

„06 „04

„02

Faster

&

Wider

Current Memory

Technology

Key Memory Design Challenges Solutions

Challenges

o Increased system failures

o Compliance to new standards

o Signal Integrity verification

o Margin testing

o Probing issues

o Probe load reduces system margin

o Signal accessibility is limited

o Conventional probing limits signal

insights

o Probing can cause signal reflection

and other SI issues

Solutions

o Follow the signal flow

o Accurate captures

o Capture high data rates with

small eyes

o Precise triggering

o Bus level signal integrity insight

o Minimize signal integrity issues

caused by BGA probing

o Verify adherence to standards

Analysis Tool Data Acquisition

2 Gb/s High Speed Logic Analysis Module

Probing

BGA Probes

Mid-Bus Probing

SoftTouch

Decoder

Protocol Compliance

Performance Analysis

Trigger

Signal Integrity

Oscilloscope

Logic Analyzer

4 Gb/s 2.5Gb/s Ultra High Speed Logic Analysis

Module

Connect Acquire View & Analyze

Interposers

Agilent Memory Solutions-> Follow the Signal Flow

Analysis Tool Data Acquisition

2 Gb/s High Speed Logic Analysis Module

Probing

BGA Probes

Mid-Bus Probing

SoftTouch

Decoder

Protocol Compliance

Performance Analysis

Trigger

Signal Integrity

Oscilloscope

Logic Analyzer

4 Gb/s 2.5Gb/s Ultra High Speed Logic Analysis

Module

Connect Acquire View & Analyze

Interposers

Agilent Memory Solutions-> Follow the Signal Flow

Capture High Data

Rate Signals

with small eyes

Precise Triggering

Accurate

capture

Memory Depth up to 200M per Channel Channels/Width 136 channels per module up to 3 modules in a set Timing Speed 5 GHz 68 Channels 2.5 GHz 136 Channels Timing Zoom 12.5 GHz Full Channel x 256K

Trigger Highlights

Sequence Rate 2.5GHz

Sequencer Levels 8

Burst recognizers

Burst of 8 x 4

Burst of 4 x 8

Burst of 2 x 16

U4154A Key Characteristics State Speed 4Gb/s on 68 Channels

2.5Gb/s on 136 Channels

Data valid window ≤100ps x 100mV

Sampling Resolution 5ps by 5mv

EyeScan Colorized all signals

HW Accelerate (>x10 speed)

New – Qualified Colorized Scan Display all Signals

Earlier generation

Colorized

Scalable

Qualified

HW accelerated

10x faster

hours to minutes

5psx5MVresolution

DDR EyeScan customized views

• Group signals on tabs

• Qualified DDR scan examples:

Read / Write separation

Byte Lanes

Burst Scans

Analysis Tool Data Acquisition

2 Gb/s High Speed Logic Analysis Module

Probing

BGA Probes

Mid-Bus Probing

SoftTouch

Decoder

Protocol Compliance

Performance Analysis

Trigger

Signal Integrity

Oscilloscope

Logic Analyzer

4 Gb/s 2.5Gb/s Ultra High Speed Logic Analysis

Module

Connect Acquire View & Analyze

Interposers

Agilent Memory Solutions-> Follow the Signal Flow

SI Measurement with Oscilloscope

•Read and write data parametric testing

•Identify cross talk and ISI failures

•Track infrequent events

•Jitter characterization

•Compliance as per JEDEC standard

Memory Design Phases that requires SI testing

Prototyping (alpha and beta)

•SI characterization to

compare results with design

simulation and specification

•Margin testing – varying

temperature and voltage levels

Post Production

• Margin testing for checking

compatibility issues

SI Validation Tasks requires Highest Measurement Accuracy Tools

Memory Oscilloscope Measurement Tool

DDR/SD Compliance

Software Packages

DDR/SD Fixtures

and Probes

9000/90000 series Oscilloscope

InfiniiScan+ InfiniiSim Serial Data Package

DRAM

Most Complete Memory Test Tools

DDR Probing and Analysis Tool When Vias Are Not Accessible

For embedded system with tight board spaces and fully populated DIMM configuration, BGA probes

provides signal access

Example 1: Scope optimized

BGA probe on DIMM

configuration

High BW for accurate

compliance measurements.

Example 2: Flex wing BGA probe

access for most signals

Quick connection for either logic

analyzer or scope

De-embedding is used for parametric

measurements

BGA probe and Via probing Comparison

Skew caused

by delay

Channel 1: Probing at VIA

Channel 2: Probing at scope pad point on adapter board

Decrease in amplitude

Before de-embedding

Not acceptable for SI check:

Signal performance is affected using the

BGA probe for SI check. How do I simulate

an ideal probe?

Channel 1: At VIA (DQS strobe)

Channel 2: At scope adapter board

Turn on Bandwidth Limit to 4G on the

channel to reduce the ringing effect due to

high frequency content.

After de-embedding

InfiniiScan+ demo

2 distinctive bursts pattern

for read & write commands

read/write data

• Signal Integrity

• Basic Compliance (i.e.

clock, voltages)

• Read/write timing

Customer Measurement Experience / Sequence

Power On Test • LA training

• Bus Timing / Power management

• Memory training/initialization

• Bus-wide SI scan

• FA- Subsystem / signal Isolation

• System Functionality

• LL SW Integration

• Cross-bus traffic

• Performance tuning

• Root cause parametric failure analysis

• Detailed parametric characterization

• Compliance / Vendor qualification

Boots may be unstable OS boots up Live application/stress