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ACCIDENT INFORMATION SYSTEM ACCIDENT INFORMATION SYSTEM Mini Project Report Submitted By DON MATHEW In Partial Fulfillment of V1 th semester of Bachelor of Technology In ELECTRONICS AND COMMUNICATION OF COCHIN UNIVERSITY OF SCIENCE AND TECHNOLOGY DEPARTMENT OF ELECTRONICS AND COMMUNICATION COLLEGE OF ENGINEERING, POONJAR KOTTAYAM – 686 582 Email: [email protected] Website :http:/www.cep.ac.in APRIL 2012 Dept. of ECE, College of Engineering. Poonjar 1

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Page 1: Accident Information System

ACCIDENT INFORMATION SYSTEM

ACCIDENT INFORMATION SYSTEM

Mini Project Report Submitted

By

DON MATHEW

In Partial Fulfillment of V1th semester of

Bachelor of Technology

In

ELECTRONICS AND COMMUNICATION

OF

COCHIN UNIVERSITY OF SCIENCE AND TECHNOLOGY

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

COLLEGE OF ENGINEERING, POONJAR

KOTTAYAM – 686 582

Email: [email protected]

Website :http:/www.cep.ac.in

APRIL 2012

Dept. of ECE, College of Engineering. Poonjar 1

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ACCIDENT INFORMATION SYSTEM

ABSTRACT

An accident information system is an electronic device installed in a vehicle to

enable the owner or a third party to track the vehicle's location when an accident has occurred. Most

systems use Global Positioning System (GPS) modules for accurate location of the vehicle. This

system has a communication component (GSM) to communicate with the vehicle’s location to a

remote user.

Vehicle information can be viewed on Google maps via specialized software. This

system uses a transducer (accelerometer) which converts the mechanical stress to electrical energy. If

the value from the accelerometer exceeds the threshold value, then the system will inform the third

party about the accident and also send him the latitude and longitude information through GSM. This

system also has aloud alarm that makes it easier for police or ambulance to track the vehicle location.

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ACCIDENT INFORMATION SYSTEM

CONTENTS

1. INTRODUCTION 1

2. MAIN OBJECTIVES 2

3. PROJECT DESIGN 3

4. HARDWARE SECTION

4.1 BLOCK DIAGRAM

4.2BLOCK LEVEL EXPLANATION 5

4.3 CIRCUIT DIAGRAM

4.4 CIRCUIT EXPLANATION 8

4.5 CIRCUIT COMPONENTS 10

4.6 PCB LAYOUT 23

5. SOFTWARE SECTION

5.1 PROGRAM FLOWCHART 24

5.2 PROGRAM 25

6. ADVANTAGES AND DISADVANTAGES 32

7. RESULTS AND DISCUSSIONS 32

8. BIBLIOGRAPHY 33

9. CONCLUSION AND FUTURE SCOPE 33

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ACCIDENT INFORMATION SYSTEM

LIST OF FIGURES

Figure 1 Block Diagram 4

Figure 2 Circuit Diagram 7

Figure 3 Pin out of MAX232 18

Figure 4 Logic diagram of MAX232 20

Figure 5 GPS 21

Figure 6 PCB Layout 23

Figure 7 Flow chart 24

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1. INTRODUCTION

Traffic safety plays a key and integral role in a sustainable transportation development strategy. The main negative impact of modern road transportation systems today is injury and loss of life as a result of road accidents. The success of traffic safety and highway improvement programs hinges on the analysis of accurate and reliable traffic accident data While of the road accident situation is slowly improving in the high income industrialized countries, most developing countries such as India, face a worsening situation . With the number of vehicles on the road growing rapidly, more road conflicts develop traffic accidents.

Most of these accidents result from human error and carelessness on the part of the drivers or pedestrians. However, the probability of occurrence, and its severity, can often be reduced by the application of proper traffic control devices, and good roadway design features. It has long been recognized that the most effective means towards accident reduction lies in a systematic and scientific approach based on the use of accurate and reliable traffic accident data. But the quantity of data important for the analysis is not always sufficient

Much of the accident information available in police files is all too often incomplete and therefore has not been utilized to the fullest extent. In addition, records are also needed to provide facts to guide programs including enforcement, education, maintenance, vehicle inspection, emergency medical services, and engineering to improve streets and highways.

There is a need for better information of the circumstance of collisions, especially with regards to location in order to come up with a general picture of the data. More precise location data could help provide facts to guide programs including enforcement, education, maintenance, vehicle inspection, emergency medical services, and engineering to improve streets and highways.

Our main objective through this project is an effective accident information system using GPS & GSM. When an accident is occurred, the GPS receiver is activated it receives the longitude & latitude of current location of the vehicle & this data is send through GSM in to the number saved inside GSM modem.

The website is monitored at a control room and if an accident is occurred,

instant rescue facilities can be provided to the victims. Day to day increasing vehicle

accidents is the fact which leads us to do this project work.

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ACCIDENT INFORMATION SYSTEM

2. MAIN OBJECTIVES

1. ACCIDENT INFORMATION (if an accident happens, the system will

detect the accident and the location will be send to the control room.).

2. INSTANT RESCUE (we can provide emergency medical services to the

victims much faster.)

3. REDUCE DEATH (by providing emergency medical services to the

victims death rate due to accidents can be reduced.)

3. PROJECT DESIGN

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ACCIDENT INFORMATION SYSTEM

Our project has mainly two sections

Hardware

Software

a) HARDWARE SECTION

It includes

1. GPS module

2. GSM module

3. GPSR module

4. PIC16F877A

b) SOFTWARE SECTION

It includes programming of

1. ADC conversion

2. GPS reception

3. GSM initialization

4. GPSR initialization

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HARDWARE SECTION

4.1 BLOCK DIAGRAM

Fig 1:Block diagram

4.2 BLOCK LEVEL EXPLANATION

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PIC 16F877A

GPS RECEIVER

GSM MODEMLCD DISPLAY

CRASH SENSOR

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ACCIDENT INFORMATION SYSTEM

POWER SUPPLY It provides +5V and ground

DISPLAY

This block provides machine to man communication and alert and instructs the

driver in various conditions.

CRASH SENSOR

This is used to sense the accident of the vehicle. After the accident is reported,

the system will give indication to remote person.

GLOBAL POSITIONING SYSTEM RECEVIER This section will decode the signals transmitted by the Global Positioning

Satellites and provides information about the location, speed, time etc. Using this

module we will extract longitude, latitude, speed of the vehicle and time.

GSM modem

This system will send SMS to remote person about the accident of the vehicle

and its location, after an accident has occurred. User has also provision to check the

location of the vehicle by sending a request by user.

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PIC167877A

For our project we are using PIC micro-controller. PIC is a family

of Harvard architecture micro-controllers made by Microchip Technology. The name

PIC initially referred to "Peripheral Interface Controller". PICs are popular with both

industrial developers and hobbyists alike due to their low cost, wide availability, large

user base, extensive collection of application notes, availability of low cost or free

development tools, and serial programming (and re-programming with flash memory)

capability.

It is a 40 pin 8 bit CMOS FLASH microcontroller that operates at a clock input of 11.0592 MHz provided with a crystal.

FEATURES:

operating speed :DC-20 MHz clock input

interrupt capability upto 14 sources

ADC resolution:5 mV

10 bit multi channel analog-to-digital converter(ADC)

Universal synchronous asynchronous receiver transmitter(USART) with 9 bit address detection

wide operating range:2-5.5 V

programmable code protection

upto 8kX 14 words of FLASH program memory and 256X8 bytes of EEPROM data memory

ADVANTAGES:

High performance RISC CPU

Only 35 single instructions

Low power high speed CMOS FLASH technology

Supports a number of peripherals like ADC,LCD,TIMER,USART etc

4.3 CIRCUIT DIAGRAM

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Fig 2: Circuit diagram

4.4 CIRCUIT LEVEL EXPLANATION

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Circuit diagram is shown in figure. In this portion, the main components

are, PIC16F877A, GPS section, GPRS section, Accelerometer, MAX 232 , and power

supply unit.

POWER SUPPLY

The power supply unit consist of a voltage regulator IC 7805, which gives

regulated 5 v as output

ACCELEROMETER SECTION

The accelerometer used here a capacitive type, ie output voltage varies

corresponding to the change in the capacitance semiconductor materials (polysilicon)

using semiconductor processes (masking and etching). It can be modeled as a set of

beams attached to a movable central mass that move between fixed beams. The

movable beams can be deflected from their rest position by subjecting the system to

acceleration

As the beams attached to the central mass move, the distance from them to the fixed

beams on one side will Increase by the same amount that the distance to the fixed

beams on the other side decreases. The change in distance is a measure of acceleration.

The g-cell beams form two back-to-back capacitors). As the center beam moves with

acceleration, the distance between the beams changes and each capacitor's value will

change, (C = Aε/D). Where A is the area of the beam, ε is the dielectric constant, and D

is the distance between the beams.

The accelerometer used here is a three axis accelerometer which is capable of measuring acceleration or deceleration in 6 directions. The three output pins of module gives acceleration in voltage along the 3 axes. The default voltage at output pins is 1.65

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v. When there is a acceleration the voltage will rise to 2.45 v, when there is a deceleration the voltage falls to 0.85 v. This three output pins are connected to the ADC inputs of PIC 16F877A A RC filter in the output is used to avoid clock noise

GPS MODULE

GPS module is used to trace the position of the vehicle. The speed and

position of the vehicle are received from the GPS module and these details are

processed by the microcontroller unit.

MAX 232

The voltage level of PIC 16F877A is in TTL level. But the GPS is

operating in RS 232 mode. thus to convert the voltage level from TTL to RS 232, the

MAX 232 IC is used

.

4.5 CIRCUIT COMPONENTS

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a. PIC 16F877A

Basic diagram

Pin diagram

High-Performance RISC CPU:

• Only 35 single-word instructions to learn

• All single-cycle instructions except for program branches, which are two-cycle

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• Operating speed: DC – 20 MHz clock input – 200 ns instruction cycle

• Up to 8K x 14 words of Flash Program Memory, Up to 368 x 8 bytes of Data

Memory (RAM), Up to 256 x 8 bytes of EEPROM Data Memory

• Pin out compatible to other 28-pin or 40/44-pin PIC16CXXX and PIC16FXXX

microcontrollers

Peripheral Features:

• Timer0: 8-bit timer/counter with 8-bit prescaler

• Timer1: 16-bit timer/counter with prescaler, can be incremented during Sleep

via external crystal/clock

• Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler

• Two Capture, Compare, PWM modules

- Capture is 16-bit, max. resolution is 12.5 ns

- Compare is 16-bit, max. resolution is 200 ns

- PWM max. resolution is 10-bit

• Synchronous Serial Port (SSP) with SPI™ (Master mode) and I2C™

(Master/Slave)

• Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI)

with 9-bit address detection

• Parallel Slave Port (PSP) – 8 bits wide with external RD, WR and CS controls

(40/44-pin only)

• Brown-out detection circuitry for Brown-out Reset (BOR)

Analog Features:

• 10-bit, up to 8-channel Analog-to-Digital Converter (A/D)

• Brown-out Reset (BOR)

• Analog Comparator module with:

- Two analog comparators

- Programmable on-chip voltage reference (VREF) module

- Programmable input multiplexing from device inputs and internal voltage

reference

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- Comparator outputs are externally accessible

Special Microcontroller Features:

• 100,000 erase/write cycle Enhanced Flash program memory typical

• 1,000,000 erase/write cycle Data EEPROM memory typical

• Data EEPROM Retention > 40 years

• Self-reprogrammable under software control

• In-Circuit Serial Programming™ (ICSP™) via two pins

• Single-supply 5V In-Circuit Serial Programming

• Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation

• Programmable code protection

• Power saving Sleep mode

• Selectable oscillator options

• In-Circuit Debug (ICD) via two pins

CMOS Technology:

• Low-power, high-speed Flash/EEPROM technology

• Fully static design

• Wide operating voltage range (2.0V to 5.5V)

• Commercial and Industrial temperature ranges

• Low-power consumption

ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS

RECEIVER TRANSMITTER (USART)

The Universal Synchronous Asynchronous Receiver Transmitter (USART)

module is one of the two serial I/O modules. (USART is also known as a Serial

Communications Interface or SCI.) The USART can be configured as a full-duplex

asynchronous system that can communicate with peripheral devices, such as CRT

terminals and personal computers, or it can be configured as a half-duplex synchronous

system that can communicate with peripheral devices, such as A/D or D/A integrated

circuits, serial EEPROMs, etc. The USART can be configured in the following modes:

• Asynchronous (full-duplex)

• Synchronous – Master (half-duplex)

• Synchronous – Slave (half-duplex)

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Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to be set in order to

configure pins RC6/TX/CK and RC7/RX/DT as the Universal Synchronous

Asynchronous Receiver Transmitter. The USART module also has a multi-processor

communication capability using 9-bit address detection.

USART Baud Rate Generator(BRG)

The BRG supports both the Asynchronous and

Synchronous modes of the USART. It is a dedicated 8-bit baud rate generator. The

SPBRG register controls the period of a free running 8-bit timer. In Asynchronous

mode, bit BRGH (TXSTA<2>) also controls the baud rate. In Synchronous mode, bit

BRGH is ignored. Table 10-1 shows the formula for computation of the baud rate for

different USART modes which only apply in Master mode (internal clock). Given the

desired baud rate and FOSC, the nearest integer value for the SPBRG register can be

calculated using the formula in Table 10-1. From this, the error in baud rate can be

determined.

It may be advantageous to use the high baud rate (BRGH = 1) even for

slower baud clocks. This is because the FOSC/(16 (X + 1)) equation can reduce the

baud rate error in some cases. Writing a new value to the SPBRG register causes the

BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer

overflow before outputting the new baud rate.

USART Asynchronous Mode

In this mode, the USART uses standard Non-Returnto- Zero (NRZ) format

(one Start bit, eight or nine data bits and one Stop bit). The most common data format is

8 bits. An on-chip, dedicated, 8-bit Baud Rate Generator can be used to derive standard

baud rate frequencies from the oscillator. The USART transmits and receives the LSb

first. The transmitter and receiver are functionally independent but use the same data

format and baud rate. The baud rate generator produces a clock, either x16 or x64 of the

bit shift rate, depending on bit BRGH (TXSTA<2>). Parity is not supported by the

hardware but can be implemented in software (and stored as the ninth data bit).

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Asynchronous mode is stopped during Sleep. Asynchronous mode is selected by

clearing bit SYNC (TXSTA<4>).

The USART Asynchronous module consists of the following important elements:

• Baud Rate Generator

• Sampling Circuit

• Asynchronous Transmitter

• Asynchronous Receiver

USART ASYNCHRONOUS TRANSMITTER

The USART transmitter block diagram is shown in Figure 10-1. The heart

of the transmitter is the Transmit (Serial) Shift Register (TSR). The shift register

obtains its data from the Read/Write Transmit Buffer, TXREG. The TXREG register is

loaded with data in software. The TSR register is not loaded until the Stop bit has been

transmitted from the previous load. As soon as the Stop bit is transmitted, the TSR is

loaded with new data from the TXREG register (if available). Once the TXREG

register transfers the data to the TSR register (occurs in one TCY), the TXREG register

is empty and flag bit, TXIF (PIR1<4>), is set. This interrupt can be enabled/disabled by

setting/clearing enable bit, TXIE (PIE1<4>). Flag bit TXIF will be set regardless of the

state of enable bit TXIE and cannot be cleared in software. It will reset only when new

data is loaded into the TXREG register. While flag bit TXIF indicates the status of the

TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR

register. Status bit TRMT is a read-only bit which is set when the TSR register is

empty. No interrupt logic is tied to this bit so the user has to poll this bit in order to

determine if the TSR register is empty. Transmission is enabled by setting enable bit,

TXEN (TXSTA<5>). The actual transmission will not occur until the TXREG register

has been loaded with data and the Baud Rate Generator (BRG) has produced a shift

clock (Figure 10-2). The transmission can also be started by first loading the TXREG

register and then setting enable bit TXEN. Normally, when transmission is first started,

the TSR register is empty. At that point, transfer to the TXREG register will result in an

immediate transfer to TSR, resulting in an empty TXREG. A back-to-back transfer is

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thus possible (Figure 10-3). Clearing enable bit TXEN during a transmission will cause

the transmission to be aborted and will reset the transmitter. As a result, the

RC6/TX/CK pin will revert to high-impedance. In order to select 9-bit transmission,

transmit bit TX9 (TXSTA<6>) should be set and the ninth bit should be written to

TX9D (TXSTA<0>). The ninth bit must be written before writing the 8-bit data to the

TXREG register. This is because a data write to the TXREG register can result in an

immediate transfer of the data to the TSR register (if the TSR is empty). In such a case,

an incorrect ninth data bit may be loaded in the TSR register. When setting up an

Asynchronous Transmission, follow these steps:

1. Initialize the SPBRG register for the appropriate baud rate. If a high-speed

baud rate is desired, set bit BRGH (Section 10.1 “USART Baud Rate Generator

(BRG)”).

2. Enable the asynchronous serial port by clearing bit SYNC and setting bit

SPEN.

3. If interrupts are desired, then set enable bit TXIE.

4. If 9-bit transmission is desired, then set transmit bit TX9.

5. Enable the transmission by setting bit TXEN, which will also set bit TXIF.

6. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D.

7. Load data to the TXREG register (starts transmission).

8. If using interrupts, ensure that GIE and PEIE

USART ASYNCHRONOUS RECEIVER

The receiver block diagram is shown in Figure 10-4. The data is received

on the RC7/RX/DT pin and drives the data recovery block. The data recovery block is

actually a high-speed shifter, operating at x16 times the baud rate; whereas the main

receive serial shifter operates at the bit rate or at FOSC. Once Asynchronous mode is

selected, reception is enabled by setting bit CREN (RCSTA<4>). The heart of the

receiver is the Receive (Serial) Shift Register (RSR). After sampling the Stop bit, the

received data in the RSR is transferred to the RCREG register (if it is empty). If the

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transfer is complete, flag bit, RCIF (PIR1<5>), is set. The actual interrupt can be

enabled/disabled by setting/clearing enable bit, RCIE (PIE1<5>). Flag bit RCIF is a

read-only bit which is cleared by the hardware. It is cleared when the RCREG register

has been read and is empty. The RCREG is a

double-buffered register (i.e., it is a two-deep FIFO). It is possible for two bytes

of data to be received and transferred to the RCREG FIFO and a third byte to begin

shifting to the RSR register. On the detection of the Stop bit of the third byte, if the

RCREG register is still full, the Overrun Error bit, OERR (RCSTA<1>), will be set.

The word in the RSR will be lost. The RCREG register can be read twice to retrieve the

two bytes in the FIFO. Overrun bit OERR has to be cleared in software. This is done by

resetting the receive logic (CREN is cleared and then set). If bit OERR is set, transfers

from the RSR register to the RCREG register are inhibited and no further data will be

received. It is, therefore, essential to clear error bit OERR if it is set. Framing error bit,

FERR (RCSTA<2>), is set if a Stop bit is detected as clear. Bit FERR and the 9th

receive bit are buffered the same way as the receive data. Reading the RCREG will load

bits RX9D and FERR with new values, therefore, it is essential for the user to read the

RCSTA register before reading the RCREG register in order not to lose the old FERR

and RX9D information.

When setting up an Asynchronous Reception, follow these steps:

1. Initialize the SPBRG register for the appropriate baud rate. If a high-speed

baud rate is desired, set bit BRGH “USART Baud Rate Generator (BRG)”).

2. Enable the asynchronous serial port by clearing bit SYNC and setting bit

SPEN.

3. If interrupts are desired, then set enable bit RCIE.

4. If 9-bit reception is desired, then set bit RX9.

5. Enable the reception by setting bit CREN.

6. Flag bit RCIF will be set when reception is complete and an interrupt will be

generated if enable bit RCIE is set.

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7. Read the RCSTA register to get the ninth bit (if enabled) and determine if any

error occurred during reception.

8. Read the 8-bit received data by reading the RCREG register.

9. If any error occurred, clear the error by clearing enable bit CREN.

10. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON

register are set.

SETTING UP 9-BIT MODE WITH ADDRESS DETECT

When setting up an Asynchronous Reception with address detect enabled:

• Initialize the SPBRG register for the appropriate baud rate. If a high-speed baud

rate is desired, set bit BRGH.

• Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN.

• If interrupts are desired, then set enable bit RCIE.

• Set bit RX9 to enable 9-bit reception.

• Set ADDEN to enable address detect.

• Enable the reception by setting enable bit CREN.

• Flag bit RCIF will be set when reception is complete, and an interrupt will be

generated if enable bit RCIE was set.

• Read the RCSTA register to get the ninth bit and determine if any error

occurred during reception.

• Read the 8-bit received data by reading the RCREG register to determine if the

device is being addressed.

• If any error occurred, clear the error by clearing enable bit CREN. ADDEN bit

to allow data bytes and address bytes to be read into the receive buffer and

interrupt the CPU.

c.MAX232

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Fig 3: Pin out of MAX232

_ Meets or Exceeds TIA/EIA-232-F and ITU

Recommendation V.28

_ Operates From a Single 5-V Power Supply

With 1.0-_F Charge-Pump Capacitors

_ Operates Up To 120 kbit/s

_ Two Drivers and Two Receivers

_ ±30-V Input Levels

_ Low Supply Current . . . 8 mA Typical

_ ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

_ Upgrade With Improved ESD (15-kV HBM)

and 0.1-_F Charge-Pump Capacitors is

Available With the MAX202

_ Applications

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− TIA/EIA-232-F, Battery-Powered Systems, Terminals, Modems, and

Computers

Fig 4: logic diagram of MAX232

The MAX232 is a dual driver/receiver that includes a capacitive voltage generator to

supply TIA/EIA-232-F voltage levels from a single 5-V supply. Each receiver converts

TIA/EIA-232-F inputs to 5-V TTL/CMOS levels. These receivers have a typical

threshold of 1.3 V, a typical hysteresis of 0.5 V, and can accept ±30-V inputs. Each

driver converts TTL/CMOS input levels into TIA/EIA-232-F levels

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d. GPS BASICS

Fig 5: GPS basics

GPS has been under development in the USA since 1973. The US

department of Defence as a worldwide navigation and positioning resource for military

as well as civilian use for 24 hours and all weather conditions primarily developed it. In

its final configuration, NAVSTAR GPS consists of 21 satellites (plus 3 active spares) at

an altitude of 20200 km above the earth’s surface (Fig. 1). These satellites are so

arranged in orbits to have atleast four satellites visible above the horizon anywhere on

the earth, at any time of the day. GPS Satellites transmit at frequencies L1=1575.42

MHz and L2=1227.6 MHz modulated with two types of code viz. P-code and C/A code

and with navigation message. Mainly two types of observable are of interest to the user.

In pseudo ranging the distance between the satellite and the GPS receiver plus a small

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corrective term for receiver clock error is observed for positioning whereas in carrier

phase techniques, the difference between the phase of the carrier signal transmitted by

the satellite and the phase of the receiver oscillator at the epoch is observed to derive

the precise information. The GPS satellites act as reference points from which receivers

on the ground detect their position. The fundamental navigation principle is based on

the measurement of pseudoranges between the user and four satellites (Fig. 2). Ground

stations precisely monitor the orbit of every satellite and by measuring the travel time

of the signals transmitted from the satellite four distances between receiver and

satellites will yield accurate position, direction and speed. Though three-range

measurements are sufficient, the fourth observation is essential for solving clock

synchronization error between receiver and satellite. Thus, the term “pseudoranges” is

derived. The secret of GPS measurement is due to the ability of measuring carrier

phases to about 1/100 of a cycle equaling to 2 to 3 mm in linear distance. Moreover the

high frequency L1 and L2 carrier signal can easily penetrate the ionosphere to reduce

its effect. Dual frequency observations are important for large station separation and for

eliminating most of the error parameters.

There has been significant progress in the design and miniaturization of

stable clock. GPS satellite orbits are stable because of the high altitudes and no

atmosphere drag. However, the impact of the sun and moon on GPS orbit though

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significant, can be computed completely and effect of solar radiation R1 pressure on the

orbit and tropospheric delay of the signal have been now modeled to a great extent from

past experience to obtain precise information for various applications.

4.6 PCB LAYOUT

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Fig 6: PCB Layout

5.SOFTWARE SECTION

5.1 PROGRAM FLOW CHART

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No Yes

SENT MESSAGE

THROUGH GSM

Fig 7: Flow chart

5.2 PIC PROGRAM

#include<pic.h>

#include "lcd4bit.h"

#define _XTAL_FREQ 20000000Dept. of ECE, College of Engineering. Poonjar 28

START

Initialize GSM&GPS

READ INPUT PIN OF PIC

If accident

ACTIVATE GPS

STOP

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#define SRL_DISP(a) { TXREG=a; while(!TRMT); }

#define CRASH RD2

#define BUZZER RD1

#define ON 1

#define OFF 0

void puts(char *ptr);

void gsmInit(void);

void sms_send(void);

unsigned char gps[27],access=0,i=0,rcv_val=0,status=0,j=0;

// ************************************isr***********************************//

void interrupt isr(void)

{

if(RCIF)

{

RCIF=0;

rcv_val=RCREG;

if(!status)

{

if((rcv_val=='$')&& (access==0)) { access=1;}

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else if((rcv_val=='R')&&(access==1)) {access=2; }

else if((rcv_val=='M')&&(access==2)) {access=3; }

else if((rcv_val=='C')&&(access==3)) {access=4; }

else if((rcv_val==',')&&(access==4)) {access=5; }

else if((rcv_val==',')&&(access==5)) {access=6; }

if(access==6) { gps[i++]=rcv_val;}

if(i>26) { access=0; i=0; status=1; }

}

}

}

void main()

{

unsigned char k;

// ********************direction register configuration**********************//

TRISC=0x80; //serial communication rx tx enable

TRISB =0x0;

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TRISD=0x04;

//********************port register configuration***************************//

PORTB=0;

PORTD=0;

// *******************SFR register configuration***************************//

SYNC=0;SPEN=1;TXEN=1;CREN=1;BRGH=1;SPBRG=129; // serial communication

GIE=1;RCIE=1;PEIE=1;

//***********************code ***********************//

BUZZER = 1;

lcd_init();

__delay_ms(50);

lcd_send(0,0x85,0);lcd_send(1,'A',0);lcd_send(1,'I',0);lcd_send(1,'S',0);

lcd_word(16,"Loading... ");

gsmInit();

lcd_word(16," ");

__delay_ms(200);

BUZZER = 0;

__delay_ms(200);

BUZZER = 1;

__delay_ms(200);

BUZZER = 0;

__delay_ms(200);

BUZZER = 1;

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__delay_ms(200);

while(1)

{

if(status)

{

lcd_send(0,0x80,0);

for(k=3;k<9;k++) {lcd_send(1,gps[k],0);}//********** Latitude direction ****** ****//

lcd_send(1,gps[13],0);

lcd_send(0,0xc0,0);

for(k=15;k<22;k++){lcd_send(1,gps[k],0);}

lcd_send(1,gps[26] ,0);

status=0;

}

if(CRASH)

{

lcd_send(0,0x01,0);

__delay_ms(100);

lcd_word(0,"Accident Occured");

while(!status);

sms_send();

BUZZER = 0;

__delay_ms(500);

lcd_word(16,"Message Send ");

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while(1);

}

}

}

//**********************passing a string serial port********************//

void puts(char *ptr)

{

while(*ptr)

{TXREG=*(ptr++);

while(TRMT==0);

}

}

//*********************************gsm modem initialization ******************//

void gsmInit()

{

SRL_DISP('\r');

puts("AT\n\r");

__delay_ms(1000);

puts("ATE0\n\r");

__delay_ms( 1000 );

puts("AT+CMGF=1\n\r");

__delay_ms(1000 );

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puts("AT+CNMI=1,1,0,0,0\n\r");

__delay_ms(1000 );

puts("AT+CSAS\n\r");

__delay_ms( 1500 );

}

//*****************sms send ******************//

void sms_send()

{

puts("AT+CMGS=\"9961517087\"\n");

__delay_ms(300);

puts("ACCIDENT_OCCURRED\n");

puts("LOCATION:\n");

//************* Latitude *****************//

puts("LATITUDE:");

for(j=3;j<9;j++)

SRL_DISP(gps[j]);

//********** Latitude direction ****** ****//

SRL_DISP(gps[13]);

puts("\n\r");

// ************ Longitude *****************//

puts("LONGITUDE:");

for(j=15;j<22;j++)

SRL_DISP(gps[j]);

//******** Longitude direction **********//

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SRL_DISP(gps[26]);

SRL_DISP(0x1A);

}

# C# POGRAMMING LANGUAGE

C# (pronounced "see sharp") is a multi-paradigm programming language

encompassing imperative, functional, generic, object-oriented (class-based), and

component-oriented programming disciplines. It was developed by Microsoft within the

.NET initiative and later approved as a standard by Ecma (ECMA-334) and ISO

(ISO/IEC 23270). C# is one of the programming languages designed for the Common

Language Infrastructure. C# is intended to be a simple, modern, general-purpose,

object-oriented programming language. Its development team is led by Anders

Hejlsberg, the designer of Borland's Turbo Pascal, who has said that its object-oriented

syntax is based on C++ and other languages. The most recent version is C# 3.0, which

was released in conjunction with the .NET Framework 3.5 in 2007. The next proposed

version, 4.0, is in development.

6. ADVANTAGES AND APPLICATIIONS

Very useful in increasing vehicle security

Instant accident notification can reduce the tragedies of accident

Very economical

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7. RESULTS AND DISCUSSIONS

Our project “ACCIDENT INFORMATION SYSTEM ” is implemented as

per the design. It is an innovative idea proposed by the group which is an effective way

to reduce causalities of an accident and thus increases traffic security. This project

helped us to understand more about PIC 16 series microcontroller, Crash sensor, GPS

& GSM module. We are thankful to all those who gave us valuable help and guidance

to complete our project work successfully

8.BIBLIOGRAPHY

http:/dx.doi.org/10.1109-ICMET.2010.5598437

9. CONCLUSION AND FUTURE SCOPE

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The project is a microcontroller based one. During the course of carrying out the

project, many unforeseen obstacles and minor mistakes forced us to thoroughly analyze

the circuit and design. This helped us to acquire more knowledge in the microcontroller.

Now our system has been designed and constructed successfully. Through this project,

we get courage and confidence to undertake this kind of work to the future also. It

enriches our knowledge regarding designing, construction, fabrication and other aspects

of many devices.

In future,

1. We can introduce an alcohol sensor to this circuit. Vehicles will get

started only after making sure that driver is not drunk.

2. We can introduce a system in which vehicles will get decelerated when

it comes close near a vehicle or an obstacle.

3. We can introduce a license card to this system. Using this license card

all the details of driver can be collected.

Thank you…!

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