IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 46, NO. 8, AUGUST 1999 1685

AC Floating Body Effects and the ResultantAnalog Circuit Issues in Submicron FloatingBody and Body-Grounded SOI MOSFET’s

Ying-Che Tseng,Student Member, IEEE, W. Margaret Huang,Member, IEEE, David J. Monk,Member, IEEE,Pamela Welch, Jenny M. Ford,Senior Member, IEEE, and Jason C. S. Woo,Senior Member, IEEE

Abstract—We report the extensive study on ac floating bodyeffects of different SOI MOSFET technologies. Besides the severekink and resultant noise overshoot and degraded-distortion inpartially depleted (PD) floating body SOI MOSFET’s, we haveinvestigated the residue ac floating body effects in fully depleted(FD) floating body SOI MOSFET’s, and the different bodycontacts on PD SOI technologies. It is important to note that thereis a universal correlation between ac kink effect and Lorentzian-like noise overshoot regardless of whether the body is floating orgrounded. In addition, it was found that third-order harmonicdistortion is very sensitive to floating body induced kink ordeviation on output conductance due to the finite voltage drop ofbody resistance. These results provide device design guidelines forSOI MOSFET technologies to achieve comparable low-frequencynoise and linearity with Bulk MOSFET’s.

I. INTRODUCTION

I NTEGRATION of a system on a single chip demandsthat the impact of device technology on digital, memory,

and analog circuit performance be considered. SOI substrateprovides promising advantages for CMOS technology, suchas lower parasitics, crosstalk immunity, and inexpensive com-patible processes, suggesting that CMOS on SOI can bea potential candidate for the mixed-mode application [1].However, floating body effects remain an obstacle for theimplementation of partially depleted (PD) floating body SOItechnology, not only inducing the hysteresis/history effects inSOI digital switching circuits [2], [3], but also degrading thedynamic data retention in SOI DRAM [4], [5]. Over the pastdecade, the improvement of the process constraint on fullydepleted (FD) SOI MOSFET technology has become matureand it has been suggested to be an alternative to bulk siliconMOSFET’s due to reduced floating body effects and a highercurrent drivability [6]. On the other hand, body contact onPD SOI technology has recently demonstrated the promisingcircuit performance on 0.5 V SOI DTMOS digital circuits [7],

Manuscript received October 6, 1998. This work was supported by theSemiconductor Research Corporation under Project SJ-407. The review ofthis paper was arranged by Editor D. P. Verret.

Y.-C. Tseng and J. C. S. Woo are with the Department of ElectricalEngineering, University of California, Los Angeles, CA 90095 USA.

W. M. Huang, D. J. Monk, and P. Welch are with Embedded SystemsTechnology Laboratories, Motorola Inc., Mesa, AZ 85202 USA.

J. M. Ford was with Embedded Systems Technology Laboratories, MotorolaInc., Mesa, AZ 85202 USA. She is now with MOS6, Order FulfillmentOrganization, Motorola, Inc., Mesa, AZ 85202 USA.

Publisher Item Identifier S 0018-9383(99)06015-3.

[8] and 1-Gbit SOI DRAM [9]. However, baseband and RFanalog SOI circuits have not been well understood.

While FD SOI MOSFET’s offer a reduced body effect anda nearly ideal ratio when biased in the weak/moderateinversion region [10], a weak (not fully eliminated) cur-rent–voltage ( ) kink still exists and the improvement onthe severe ac kink effect and the resultant analog circuit per-formance’s degradation, such as kink-enhanced nonlinearity[11] and kink-induced noise overshoot [12] in the PD floatingbody SOI MOSFET’s, are still unknown. On the other hand, anideal body contact can eliminate the above unwanted effects.However, a nonzero body resistance due to the finite neutralbody underneath the gate and the increase of the parasitics[1] raise the concern of ac nonideal body-tied (NBT) effectfor the aforementioned applications. Different approaches havebeen proposed to analyze the circuit issues of FD and body-tied (BT) SOI for analog applications by using small-signalbehavior to predict/perform speed improvement [11] and usingbody resistance thermal noise to modeling excess noise [13].However, the detailed analysis on their ac performance arestill deficient. In this paper, the role of the ac body voltagein floating body and BT devices is identified and the resultantac floating body effects are investigated. Also, floating bodyinduced Lorentzian-like noise overshoot and degradation inharmonic distortion in different SOI technologies are alsostudied. In addition, the universal ac phenomena in SOIMOSFET’s will be addressed.

II. DEVICE TECHNOLOGY AND CHARACTERIZATION

Motorola thin-film SOI MOSFET technology [1], withthree types of device layout [Fig. 1(a)], was used in thisstudy with gate oxide, silicon film, and buried oxide of10.5 nm, 100 nm, and 360 nm, respectively. Nearly fullydepleted (NFD) and FD devices were achieved by adjustingthe threshold implant [Fig. 1(b)]. Two conventional ohmicbody contact technologies were evaluated. One is an H-gate structure modified from PD SOI technology with lateralbody contacts placed symmetrically on the edge of transistor.Therefore, the silicon film is only contacted on the two sidesleading to a tradeoff between body contact efficiency andunwanted parasitic components. The other is source/body-tied(SB-tied) devices with an extra pimplant at the source whichhas been optimized to offer a kink-free output and “pure”

0018–9383/99$10.00 1999 IEEE

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(a)

(b)

Fig. 1. (a) Schematic layout of different SOI MOSFET technologies.(I) Floating body SOI w/oxide isolation. (II) H-gate SOI w/junction isolation.(III) SB-tied SOI. (b) Schematic cross section of SOI MOSFET’s for differentoperation modes.

(a) (b)

Fig. 2. DC floating body effects of PD, NFD, FD floating body, and SB-tiedSOI nMOSFET. (a) Subthreshold characteristics and (b) output characteristicsbiased atVGT = 0:2 V.

noise. Fig. 2 shows the dc characteristics of theseSOI devices. Shifting from PD toward FD or using bodycontact, the subthreshold kink can be suppressed. However,a weak kink or a deviation in dc output conductance isstill observed in FD floating body and NBT SOI nMOS, asshown in Fig. 2(b) and the inset of Fig. 13, respectively. Theefficiency of suppressing ac floating body effect for differentSOI MOSFET technologies is evaluated by both harmonicdistortion and low-frequency (LF) noise characteristics. Thelatter was measured from 1 Hz to 10 MHz using an HP 3048APhase Noise Measurement System with 50input resistance,an HP 3561A Dynamic Analyzer, an HP 3585B SpectrumAnalyzer, and a bias network. The gate of the transistorswas ac grounded in order to extract the input-referred gatenoise power correctly. Distortion behavior was characterizedon single transistor common-source amplifiers measured at1 kHz to avoid the input capacitance effect, where harmonicdistortion is determined by the higher order derivatives of thedrain voltage with respect to gate voltage [11]. The ac outputconductance were measured using HP 4284A/HP 4285 Preci-sion LCR meters and an HP 4145B Semiconductor ParameterAnalyzer controlled by IC-CAP [14].

Fig. 3. Output conductance versus drain bias of PD floating body SOInMOSFET biased atVGT = 0:2 V with L = 0:45 �m for differentfrequencies [15].

III. AC FLOATING BODY EFFECTS

The unique characteristics in PD floating body SOI MOS-FET’s is the operation-dependent body voltage. In dc or steadystate, body charge (or body voltage) is balanced betweencarrier recombination and generation mechanisms [15], asshown in (1)

(1)

where is body voltage and and are source/bodyjunction capacitance and reverse leakage current, respectively.This body charge induces a threshold voltage reduction,resulting in a kink in the output characteristics (a spike in

). Due to the finite time constant of the G/R mechanisms,SOI switching circuits suffer severe dynamic floating body ef-fects such as the hysteresis and history effects. While dynamicfloating body effects are the primary concern in digital SOIdevice design, it is important to investigate the ac small-signalbehavior for analog applications, especially the ac outputconductance or equivalently, the transistor intrinsicgain . When biased in the post-dc kink region

, ac body voltage can be filtered through source/bodycapacitance as frequency increases, resulting in thefrequency dependence of the kink effect [16]. Fig. 3 clearlyshows that the onset of the ac kink is a strong function offrequency for PD floating body SOI MOSFET’s. That is,the onset of the kink effect, which can be defined as thevoltage where the maximum perturbation in the channel (peakof ) occurs for a given frequency, shifts towardhigher voltage as frequency increases.

This frequency dependence of the ac kink (as well as thedc kink) can be suppressed by shifting from PD toward FDoperation [12]. This is evidenced by the convergence of theac and dc drain conductance curves of the NFD and FDdevice for frequencies of 10 kHz and 100 kHz, respectively,as shown in Fig. 4. This weaker dependence of kink effect onfrequency is due to the reduced potential barrier of the S/Bjunction in NFD and FD devices, which results in a larger andfrequency independent diode leakage current, which dominatesthe body discharge behavior at low frequencies. However, athigh frequencies, the ac hole current can flow across the S/Bjunction capacitor . This current path competes with thediode leakage and can dominate the body discharging at high

TSENG et al.: AC FLOATING BODY EFFECTS 1687

(a)

(b)

Fig. 4. Output conductance versus drain bias of (a) NFD floating bodyand (b) FD floating body SOI nMOSFET biased atVGT = 0:2 V withL = 0:45 �m for different frequencies. The inset shows the zoom-inGDSof NFD and FD device, respectively.

frequencies, resulting in a weaker frequency dependent ac kinkeven for FD devices.

On the other hand, an ideal body contact in SOI MOSFET’scan remove the excess majority carriers in the body. Inpractice, the finite neutral region underneath the gate resultsin a resistive discharging path, which establishes a potentialdrop as excess carrier flows to the lateral body contact andintroduces a new term to (1) as follows:

(2)

For a low or negligible body resistance, the good outputcharacteristics can be achieved, as shown in Fig. 5. However,for a finite body resistance, a deviation or a kink (Fig. 5) indc was observed and is frequency independent exceptfor higher frequency operation. These results suggest thatthe output conductance characteristics of NBT is dominatedby the lateral resistive body discharging path at dc andlow frequencies. As frequency increases, the longitudinalcapacitive discharging mechanism competes with the lateralresistive discharging path, resulting in the ac kink dispersion,as shown in Fig. 5.

IV. RESULTANT ANALOG CIRCUIT ISSUES

A. Low-Frequency Noise Characteristics

The trend toward integration of system on a single chip hasdriven further optimization of CMOS compatible technology

Fig. 5. Output conductance versus drain bias of two H-gate body-groundedSOI MOSFET’s biased atVGT = 0:2 V with L = 0:45 �m with negligibleand high body resistance, respectively. The latter’s device width is 10� thatof the former’s.

Fig. 6. Equivalent input-referred gate noise power spectrum versus fre-quency for PD floating body SOI nMOSFET biased atVGT = 0:2 V withL = 0:45 �m: arrows indicate the location of the corner frequencyf0 atdifferent drain biases [15].

into the RF arena, especially for SOI CMOS technology.Besides the promising SOI RF characteristics and insulatorsubstrate, low-frequency noise is one of the most importantfigures-of-merit necessary to investigate, due to the existenceof kink-related Lorentzian-like noise overshoot in PD floatingbody SOI nMOSFET’s [17]. This noise spectrum consists of aLorentzian-like noise, characterized by a flat plateau followedby a roll-off at the corner frequency and a noise,and can be expressed empirically as [18]

(3)

where the first term represents the flicker noise and the secondterm represents the Lorentzian-like overshoot noise, with adrain-bias dependent corner frequency which shiftstoward higher frequencies as increases, as shown inFig. 6. While this overshoot occurs with device bias in thepost dc kink operation and poses a significant obstacle for theapplication of SOI in the RF arena, it has to be overcome withproper device design. One way is to reduce floating body effectby shrinking the neutral body region to achieve full depletion.Fig. 7 shows the spot noise of a FD and a PD floating bodySOI nMOSFET’s biased at the same gate overdrive. Insteadof the noise overshoot in PD SOI, FD SOI does providekink-free noise at low frequency [19]. However, there is stilldrain-biased dependence of noise in the high-frequency range

1688 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 46, NO. 8, AUGUST 1999

(a) (b)

Fig. 7. Input-referred gate noise power(SVG) versus drain bias at 1 Hz,100 Hz, and 100 kHz for (a) PD floating body and (b) FD floating body SOInMOSFET’s biased atVGT = 0:2 V with L = 0:45 �m.

(a)

(b)

Fig. 8. Equivalent input-referred gate noise power spectrum versus fre-quency for (a) NFD and (b) FD floating body SOI nMOSFET biased atVGT = 0:2 V with L = 0:45 �m. Arrows indicate the location of thecorner frequencyf0 at different drain biases.

(e.g. 100 kHz). As drain bias increases, however, the LF noisecharacteristics deviate from the pure behavior, exhibitinga Lorentzian-like noise overshoot spectrum with a cornerfrequency higher than 100 kHz, as shown in Fig. 8(b). Inaddition, the related overshoot amplitudeand corner frequency increase as drain bias increases in FDSOI nMOS. Therefore, the existence of overshoot noise inthe tens of kHz to MHz range, which can induce higherphase noise at the respective offset frequencies in moderncommunication systems, impedes the implementation of FDfloating body SOI MOSFET’s for RF analog applications.

One solution to this problem is to ground the body bymodifying the device structure. Frequency independent kink-free output and “pure” noise characteristics have been

achieved in the optimized H-gate body-grounded [18] and SB-tied SOI nMOS with negligible body resistance, as shownin Fig. 9(a). The latter characteristic has demonstrated thatSOI MOSFET’s, free of floating body effects, can providea comparable noise level with that of a bulk siliconGCMOS [20]. Nonetheless, achievement of good body contactefficiency could sacrifice the performance due to the increaseof parasitics, but NBT‘s also impact ac performance throughtheir effect on the LF noise characteristics. A “pure”noise was observed in the NBT SOI nMOS (with ac kinkdispersion in the high-frequency range, as shown in Fig. 5)at low-frequency range. However, a similar noise overshootphenomenon at high frequency to that of a FD SOI devicestill occurs [Fig. 9(b)].

B. Harmonic Distortion

In a nonlinear system, a pure sinusoidal input signal resultsin an output signal, which includes the sinusoidal signal as wellas higher harmonics. The corresponding-th order harmonicdistortion can be expressed as follows [21]:

distortion (4)

In long-channel MOSFET’s, since is almostbias independent, the harmonic distortion is dominated bydistortion, which has been well-examined [22]. However, insubmicron bulk MOSFET’s, output resistancecannot simply be modeled by a constant early voltage [23].In order to demonstrate the effect of this nonlinearity ofon harmonic distortion, we can adopt an inverse harmonicdistortion analysis, expressed as

distortion (5)

This equation has been shown to be equivalent to that forby Bult [21], where

(6)

Therefore, the impact of on distortion can be divided intotwo factors: 1) bulk MOSFET effect (bias dependence ofoutput resistance) and 2) SOI effects, such as kink effect andearly bipolar breakdown.

While a low overdrive value is necessary to reacha higher ratio (especially for FD SOI with nearlyideal body factor of ), it is important to note thatoutput characteristics are more sensitive to floating bodyinduced reduction

. Therefore, single transistor amplifiers werebuilt to evaluate the harmonic distortion in both pre andpost kink region with low gate overdrive. Fig. 11 shows thetotal harmonic distortion (THD) of a good BT SOI amplifierversus a bulk 0.5 m amplifier with small output swing.

TSENG et al.: AC FLOATING BODY EFFECTS 1689

(a)

(b)

Fig. 9. Equivalent input-referred gate noise power spectrum versus fre-quency for (a) SB-tied SOI nMOS with negligible body resistance and(b) H-gate body-grounded SOI nMOSFET with high body resistance biasedat VGT = 0:2 V with L = 0:45 �m.

The dependence of decreases as drain bias reduces(inset of Fig. 10) and increases the distortion at the low drainbiases [11]. Not only does a good BT SOI device providesimilar linearity to bulk devices for small-signal behavior,but they also demonstrate comparable large signal distortionbehavior for low- or high-voltage applications, as shownin Fig. 11. Consequently, achievement of similar distortionperformance suggests that SOI MOSFET technology withgood body contact efficiency can be an alternative and thedistortion of the other SOI MOSFET technologies could beexamined compared with that of good BT devices.

Fig. 10 also shows the THD of a PD floating body SOInMOS amplifier as a function of drain bias. Below kinkonset voltage at 1 kHz (1.1 V), its distortion performanceis similar to that of bulk silicon or good BT SOI nMOSFET’s.Approaching the kink’s onset (peak of ), the THDdrastically increases as expected by (5). It is also necessary tounderstand the large signal distortion behavior, which cannotbe predicted by small-signal analysis. When biased in thepre-kink region ( V), PD SOI amplifiers exhibit asimilar linearity to that of good BT devices (Fig. 12) for smalloutput swings. FD SOI amplifiers, with suppressed floatingbody effect, achieve THD levels comparable with those ofgood BT SOI for a wide dynamic range (Fig. 12). However, asthe output swing reaches the weak kink, third-order harmonicdistortion drastically increases which precludes theuse of FD SOI in wide dynamic range applications. On theother hand, when biased in the post-kink (1.5 V) region, the

Fig. 10. Total harmonic distortion(THD = (HDi)) of bulk, SB-tied,and PD floating body SOI nMOS amplifiers as a function ofVDS with 0.4V output swing. The devices were biased atVGT = 0:1 V and test signal=1 kHz. The inset shows theVDS dependence of output resistance of SB-tiedSOI nMOS.

Fig. 11. Total harmonic distortion of bulk and SB-tied SOI amplifiers asa function of peak-to-peak output swing as device operated at low voltage(1 V) and high voltage (2 V).

SOI amplifier performance degrades due to both the reducedtransistor intrinsic gain (due to the increase of ) and thelarge increase in harmonic distortion for both PD and FDfloating body SOI nMOS (Fig. 12).

For a nonideal body-tied device, a lateral resistive bodydischarging path causes a reduction in threshold voltage andthe output current deviates from the ideal body contact case.The inset of Fig. 13 shows the of two H-gate body-grounded SOI nMOSFET’s with negligible body resistance(indicative of good body contact) and finite body resistance(low case), respectively. Their curves start to di-verge and total harmonic distortion (THD) degrades for asmall output swing as the drain bias increases beyond 1.5 V.Three operating regions were characterized for large outputswing, as shown in Fig. 14. At low voltage (0.75 V), bothBT SOI nMOS amplifiers with negligible and lowachieve similar second- and third-order harmonic distortionperformance . However, at the point where their

curves diverge (1.5 V) due to the voltage drop of bodyresistance, the SOI amplifier with low experiences a drasticdegradation in due to the sharp peak in

1690 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 46, NO. 8, AUGUST 1999

Fig. 12. Harmonic distortion of SB-tied, FD floating body, and PD floatingbody SOI nMOS amplifier as a function of output swing atVGT = 0:1 Vandf = 1 kHz. The devices were biased in pre-kink (0.75 V) and post-kink(1.5 V) region.

Fig. 13. Total harmonic distortion of PD floating body, two H-gatebody-grounded SOI nMOS (with negligible and finite body resistance,respectively) amplifiers as a function ofVDS with 0.4 V output swingbiased atVGT = 0:1 V and test signal= 1 kHz. Inset shows their outputconductance and the arrows indicate the three operation regions.

caused by a large increase in . At high voltage(2 V), degrades due to both the increases ofand the nonzero , but decreases due to thediminishing . It can thus be seen that eventhough the BT SOI devices with low do not exhibit akink like the PD floating body SOI nMOS, their finite bodyresistance still degrades linearity due to the deviation of ,especially for third-order harmonic distortion, which is veryimportant in analog design.

V. DISCUSSION

A. Universal Correlation Between AC Kink Effectand Lorentzian-Like Overshoot Noise

There are two ac perturbation phenomena in PD floatingbody SOI nMOS. One is frequency dependence of kink’sonset voltage (the shifts toward higher voltage asfrequency increases), and the other is drain bias dependence ofLorentzian’s corner frequency (the overshoot noise corner

Fig. 14. Harmonic distortion of two H-gate body-grounded SOI nMOS (withnegligible and finite body resistance, respectively) amplifiers as a function ofoutput swing atVGT = 0:1 V. (I): VDS = 0:75 V. (II): VDS = 1:5 V.(III): VDS = 2 V. (IV) Schematic diagram ofGDS for a body-tied devicewith finite body resistance and its derivative. (O and/ representHD2 andHD3 of BT with low RB , respectively. Dashed line and solid line representHD2 andHD3 of good BT, respectively.) The arrows indicate the increaseof HDi in N-BT.

Fig. 15. Empirical correlation of the noise overshoot (corner frequencyf0)and ac kink effect(Vkink) of floating body SOI MOSFET’s. Technology Ais L = 0:45 �m andtox = 10:5 nm, and Technology B isL = 0:25 �mand tox = 5 nm. (O:Vkink, peak of dGDS=dVDS:f0, corner frequencyof Lorentzian-like overshoot noise).

frequency also increases as drain bias increases). The existenceof a strong correlation between these two ac phenomena leadsto a new thought of SOI device physics [18]. A similarcorrelation is also observed in FD floating body and nonidealbody-tied devices. As shifting from PD through NFD toFD, the frequency range which ac coincides with dccurves (no ac channel perturbation) increases (Fig. 4) andthe frequency range which LF noise spectrum remains pure

spectrum increases (Fig. 8). In addition, it was found thatthis correlation also exists in 0.25m PD floating body SOInMOS with 5 nm gate oxide thickness. Fig. 15 demonstratesthe well correlation between two ac perturbations for differentfloating body SOI MOSFET technologies. In addition, thenoise overshoot’s in nonideal body-tied device is alsocorresponding to its ac kink dispersion at high frequencies(Figs. 5 and 9). Therefore, there exists a universal correlationfor SOI MOSFET’s regardless of whether the body is floatingor grounding. This suggests that the possible noise overshootmechanism is not directly caused by dc impact ionizationcurrent as previously suggested by other [24], but rather

TSENG et al.: AC FLOATING BODY EFFECTS 1691

linked to the ac behavior of longitudinal source/body junction.The latter implies that the body voltage perturbation in SOIMOSFET’s, due to the onset of the ac kink shifting towardhigher frequencies as drain bias increases, shows the similardependence on frequency. Therefore, the aforementioned uni-versal correlation suggests that the drain bias dependence ofLorentzian-like overshoot noise in SOI MOSFET’s is due tofrequency dependence of body voltage perturbation.

B. Limitation of Third-Order Harmonic Distortion

Instead of a first-order derivative on output conductance, harmonic distortion which corresponds to higher order

derivative results in larger sensitivity to output characteristics.It has been shown in the previous section that and

are very sensitive to a spike on (floating bodyinduced kink) or a deviation on (voltage drop on bodyresistance). As devices were biased in post kink or postdeviation regions, not only was intrinsic transistor gain reducedbut THD also drastically degraded. Therefore, the devicesneed to operate before kink or ’s deviation. In addition,only can be reduced by proper circuit architecture(such as differential pair) resulting in the restriction of theimplementation of floating body SOI MOSFET’s on analogapplications (except for small output swing low-voltage cases).On the other hand, smaller variation on output characteristicsof nonideal body-tied devices offers a larger tolerance fordistortion requirements. Based on the application specification,nonideal body-tied PD SOI MOSFET’s can be implementedon linearity-sensitive paths coupled with multi- floatingbody SOI MOSFET’s implemented on the rest of the chip toachieve a high performance single-chip mixed-mode system.

VI. CONCLUSION

This paper presents a comprehensive study of the ac floatingbody effects and the resultant analog circuit issues of differentSOI MOSFET’s technologies. While PD floating body SOIMOSFET’s suffer severe ac kink effect resulting in LF noiseovershoot and degradation of harmonic distortion, FD floatingbody SOI MOSFET’s only provide limited improvement dueto their weak kink effect. Improvements seen by ideal bodycontact on PD SOI technology may be sacrificed due toincreased parasitics. Therefore, in baseband analog application,further source engineering optimization [6] on FD SOI tech-nology is necessary to effectively remove the residue carriersin the body. For body contact on PD SOI technology, thefinite body resistance causes the deviation of limitingthe dynamic range. The optimal device width and the channelengineering has to take into account the tradeoff between theperformance requirement and penalty of extra parasitics. In RFanalog applications, a universal low-frequency noise overshootphenomenon in SOI MOSFET’s has been identified. Reducedbody resistance in nonideal body-tied devices or optimizedsource/body engineering in FD SOI devices can shift theac kink phenomenon toward higher frequencies. Therefore,the suppression of ac kink effect shifts the Lorentzian-likenoise toward higher frequencies providing a pure noisespectrum within the bandwidth of interesting.

ACKNOWLEDGMENT

The authors are grateful to B. Yeung, D. Spooner, andD. Ngo for their support with ac measurements and the RF-TFSOI group at Embedded Systems Technology Laboratories,Motorola Inc., for providing the samples.

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[24] E. Simoen, U. Magnusson, A. L. P. Rotondaro, and C. Claeys,“The kink-related excess low-frequency noise in silicon-on-insulatorMOST’s,” IEEE Trans. Electron Devices, vol. 41, pp. 330–339, May1994.

Ying-Che Tseng (S’95) was born in Kaohsiung, Taiwan, R.O.C., in 1969.He received the B.S. degree in electrical engineering in 1991 from NationalTaiwan University, Taipei, and the M.S. degree in electrical engineering in1996 from the University of California, Los Angeles, where he is currentlypursuing the Ph.D. degree.

From 1996 to 1998, he worked as a summer intern in the SemiconductorProducts Sector, Motorola Inc., Mesa, AZ. His research interests are focusedon the deep-submicronmeter SOI CMOS device physics, aimed at low-powerRF applications.

W. Margaret Huang (S’81–M’82) received the B.S.E.E. degree from theUniversity of Illinois, Urbana, in 1981 and the M.S.E.E. degree from theUniversity of California, Berkeley, in 1982.

From 1982 to 1990, she was with Hewlett Packard, developing CMOS andhigh-speed bipolar technology. In 1990, she joined Motorola Inc., Mesa, AZ,where she engaged in mixed-mode BiCMOS technology development. Since1992, she has been working on low-voltage TFSOI CMOS and CBiCMOStechnology development. Her current interests include CMOS and BiCMOStechnology development for RF/IF applications. She has over 40 publicationsand holds nine patents in the field of integrated circuit technology.

David J. Monk (M’88) received the B.S. degree from the University of NewMexico, Albuquerque, in 1985 and the M.S. degree in electrical engineeringfrom Arizona State University, Tempe, in 1992.

He joined Motorola’s Research and Development Laboratory, Mesa, AZ,in 1985. Since that time, he has done work in a wide variety of disciplinesincluding analog device characterization, statistical parameter extraction,1=fnoise measurements, TFSOI BiCMOS integration, and high-speed analogCMOS. He is currently with Motorola’s Embedded Systems TechnologyLaboratories, Mesa.

Pamela Welch received the B.A. degree from Wells College, Aurora, NY,in 1981.

In 1981, she joined Motorola. She began her career in SPS R&QA/FailureAnalysis and moved into BICMOS process development in 1985. Since 1985,she has been involved in SiGe and TFSOI technology development andis currently working on RF CMOS integration for Motorola’s EmbeddedSystems Technology Laboratories, Mesa, AZ.

Jenny M. Ford (S’79–M’82–SM’98) was born on February 4, 1960 inMinneapolis, MN. She received the B.S. and M.S. degrees in electricalengineering, simultaneously, in June 1982, from the Massachusetts Instituteof Technology (MIT), Cambridge.

In 1982, she joined Motorola’s Semiconductor Research and DevelopmentLaboratory, Phoenix, AZ, where she was engaged in the development of0.5-�m CMOS devices. In 1986, she joined Motorolas Bipolar TechnologyCenter, Mesa, AZ, focusing on development of advanced CMOS and BiCMOSprocesses and devices. In 1996, as Device Engineering Manager for siliconRF device development at Motorola’s Communications Products Laboratory(CPL), she led development of silicon RF technologies, including exoticMOSFET (LDMOS and GCMOS), SiGe heterojunction bipolar and thin-film-silicon-on-insulator BiCMOS processes for deployment in communicationssystems. Currently, she leads the manufacturing team responsible for deliver-ing Motorola LDMOS and 0.5-�m BiCMOS products. She is the author of32 journal and conference papers in the areas of CMOS and BiCMOS devicedevelopment, characterization, and modeling. She holds four U.S. patents inthese fields.

Jason C. S. Woo(S’83–M’87–SM’97) received the B.A.Sc. (honors) degreein engineering science from the University of Toronto, Toronto, Ont., Canada,in 1981, and the M.S. and Ph.D. degrees in electrical engineering fromStanford University, Stanford, CA, in 1982 and 1987, respectively.

In 1987, he joined the Department of Electrical Engineering, the Universityof California, Los Angeles, where he is currently a Professor. His researchinterests are in the physics and technology of novel device and devicemodeling, and he has authored or coauthored more than 100 papers in technicaljournals and the referred conference proceedings in these areas.

Dr. Woo served on the IEEE IEDM Program Committee from 1989 to 1990and from 1994 to 1996, and was the Publicity Vice Chairman in 1992 andthe Publicity Chairman in 1993. He has been the Workshop Chairman anda Technical Committee Member of the VLSI Technology Symposium since1992. He has served on the committee for the IEEE SOI Conference since1995. He received a Faculty Development Award from IBM from 1987 to1989.