Aaic Adc Casestudy Note

8/3/2019 Aaic Adc Casestudy Note

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1Tai-Cheng Lee

Spring 2006

Analog-to-Digital ConverterCase Study

2Tai-Cheng Lee

Spring 2006

Folding ADC Case Study

1. An 80-MHz, 80-mW, 8-b CMOS Folding A/D Converter withDistributed Track-and-Hold Preprocessing

A. G. W. Venes and R. J van de PlasschePage(s): 1846-1853, JSSC 1996 Dec

2. An 8-b 100-MSample/s CMOS Pipelined Folding ADC

M-J Choe, B-S Song and K BacraniaPage(s): 184-194, JSSC 2001 Feb

3. An Embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mmK. Bult and A BuchwaldPage(s): 1887-1895, JSSC 1997 Dec


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5Tai-Cheng Lee

Spring 2006

A Folding A/D with Distributed Track-and-Hold Preprocessing

The design spec for each block:

Multiple clock switchesSingle clock switchClock distribution

No additional power

dissipation apart of inputgain stages

High power dissipation in

buffer amplifier to ensurelow distortion

Overall power dissipation

8-bit accuracy divided by

the gain in the input gain

stages

8-bit accuracyDynamic accuracy

Settling

Hold mode feedthrough

Clock switch charge

injection

Linearity in 1/16 of theinput range of the A/D

converter

Linearity in entire inputrange (1.6Vpp) of A/D

converter

Linear region

Distributed track-and-

hold operation

Single track-and-hold

amplifier

6Tai-Cheng Lee

Spring 2006


Reference ladder feedthrough:

Equivalent circuit model to calculate the maximum allowableresistor


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Implementation of a folder signal:

Active interpolation circuit:

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Spring 2006


Differentialinterpolation circuit:

Comparator:


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11Tai-Cheng Lee

Spring 2006

An 8-b 100-MSample/s CMOS Pipelined Folding ADC

The concept of the two-stage and folding ADC:

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Spring 2006


Flash ADC:


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Spring 2006


Folding ADC:

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Folding amplifier:


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Spring 2006


Conventionalfolding ADC:

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Spring 2006


Folder design: k=4and k=3


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Spring 2006


Pipeline folding ADC

Timing

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Spring 2006


Top level block diagram


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Second stage folder

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Spring 2006


INL due to gain mismatch


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Effect of tail current sourcemismatch

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Spring 2006


comparator design


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Spring 2006


conventional digital error correction

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Spring 2006


generic digital error correction


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25Tai-Cheng Lee

Spring 2006

An Embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm2

Conventional preamplifier and resistor-averaging preamplifier

26Tai-Cheng Lee

Spring 2006


First resistor averaging in:K.Kattmann and J.Barrow,A technique for reducing differentialnonlinearity errors in ash A/D converters, in ISSCC Dig. Tech. Papers,San Francisco, CA, Feb. 1991, pp. 170171.

Effect of resistor averaging:


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Improved resistor averaging:

Transconductor stage:

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Analysis of the effect of resistor averaging:

Correlation between neighboring signal after averaging:


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Simulated DNL and INL after resistor averaging:

Example of 3X folding signal:

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Understanding the pipeline folding signal:

ADC floor plan


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31Tai-Cheng Lee

Spring 2006

Digitally Calibrated Pipeline ADC

1. A 15-b 1-Msample/s digitally self-calibrated pipeline ADCKaranicolas, A.N.; Hae-Seung Lee; Barcrania, K.L.Page(s): 1207-1215, JSSC 1993 Dec

2. A single-ended 12-bit 20 Msample/s self-calibrating pipelineA/D converterOpris, I.E.; Lewicki, L.D.; Wong, B.C.Page(s): 1898-1903, JSSC 1998 Dec

32Tai-Cheng Lee

Spring 2006

Digitally Calibrated Pipeline ADC -- I

Ideal pipeline ADC:

Transfer characteristics:


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nonideality of transfer curve:

Gain is less than 2 per stage

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Top level diagram of backward calibration:

Residue plot for gain


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Actual implementation of non-radix-2 ADC:

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Digitally Calibrated Pipeline ADC -- II

Over-range implementation:

Residue plot:


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12-bit ADC with 3 over-range stage:

Code combine and requirement of over-range stage

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Principle of digital error correction ADC and its implementation:


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Differential-to-single ended converter

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kT/C noise (I)

RMS voltage for kT/C noise:


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kT/C noise (II)

The bottom line for a switched-cap circuit for different capacitance

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kT/C Noise in Switched-Cap Circuit kT/C noise in SC circuit


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Noise in OP amp (I) Single-stage op amp

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Noise in OP amp (II) Two-stage op amp


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OP amp based SHA (I)

Different OP amp SHA

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OP amp based SHA (II)

How to pick the optimal sampling capacitor


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OP amp based SHA (III)

An optimal samplingcapacitor can be obtained.

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OP amp based SHA (V)

Other design considerations:(1) Gain error

Does it matter?

(2) Slew rate:


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OP amp based SHA (IV)

Other design considerations:(3) switch on resistance:

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Multi-stage Offset Cancellation What is the offset voltage after cancellation?


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Auto-Zero Comparator Charge injection due to S1:

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Spring 2006

High-Speed Pipelined ADC

ADC top level diagram:


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feedback factor and load capacitance for different resolution

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digital correction


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subtractor implementation: R-DAC and C-DAC

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The requirement of stage accuracy


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The requirement of stage accuracy

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The design algorithm of pipelined ADC:


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The power dissipation vs. sampling frequency for variousresolution ADCs:

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Different resolutions for each stage:


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Scaling for each stage:

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Total power for scaling and non-scaling ADC:


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Low-Power Low-Voltage Pipelined ADC

1.5 bits per stage:

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Digital error correction:


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First-stage SHA:

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Timing for pipeline ADC


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Dynamic Comparator

A dynamic comparator with built-in threshold generator:

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Low-voltage OP

A 3.3-Volt OP amp


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Low-voltage OP

Output CMFB circuit

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Low Voltage Operation of SC Circuits

CMOS switch


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Boosted circuit:

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Floating well to prevent latch up:


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Bias Circuits for OP amp

The bias of cascode op:

Clock Generator

Clock generator and line up the edge:

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Aaic Adc Casestudy Note