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Analog front-ends for monolithic and hybrid pixels developed with a 3D CMOS process. S.Zucca a,c , L. Gaioni b,c , A. Manazza a,c , M. Manghisoni b,c , L. Ratti a,c V. Re b,c , E. Quartieri a,c , G. Traversi b,c. a Università degli Studi di Pavia b Università degli Studi di Bergamo - PowerPoint PPT Presentation
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S.Zuccaa,c, L. Gaionib,c, A. Manazzaa,c, M. Manghisonib,c, L. Rattia,c V. Reb,c, E. Quartieria,c, G. Traversib,c
aUniversità degli Studi di PaviabUniversità degli Studi di Bergamo
cINFN PaviadUniversità degli Studi di Pisa
eINFN Pisa
8th International Meeting on Front-End Electronics FEE 2011
Bergamo, 23-27 May 2011
Analog front-ends for monolithic and hybrid pixels developed with a 3D CMOS
process
FEE 2011-Bergamo, 23-27 May 2011
Outline
SuperB experiment and SVT Layer0 requirements
Vertical Integration (3D) CMOS Technologies
Analog FE for Apsel VI 3D MAPS chip
Why are they so attractive for HEP applications?
Issue for large matrices: voltage drop on analog VDD/GND lines.
3D Analog FE for Superpix1 hybrid pixels chipComparison with the Apsel VI analog FEFine tuning system for the threshold correction
Conclusion and future plans
DNW MAPS and hybrid pixels in 3D technology
General description
FEE 2011-Bergamo, 23-27 May 2011
The SuperB factory, an high luminosity e+-e- collider intended for HEP experiments, has been recently funded by the Italian Ministry for Education, University and Research.
SuperB factory
Two possible approaches for the SuperB Layer0 at full luminosity:
Silicon Vertex Tracker very similar to that of the 5 layer BaBar experiment, completed by a Layer0 very close to the IP (about 1.5 cm) to improve the vertex resolution.
Other requirements:Low material budget (<1% X0)Fine granularity (50 μm pitch)
CMOS MAPS: can provide low material budget and small pitch.
Hybrid Pixels: more mature technology, with somewhat worse material budget features.
FEE 2011-Bergamo, 23-27 May 2011
In wafer level 3D processes, multiple layers of planar devices are stacked and interconnected using inter-layer connections.
Vertical Integration (3D) CMOS Technologies
Advantages for HEP particle pixel detectors:
The analog section (and the sensor) do not share the same substrate with the noisy digital readout.
Less material in the IP: monolithic structure of the final chip enables post-process thinning.
Dead area reduction: the readout electronics can be designed with virtually no peripheral circuits.
Higher functional density more complex pixel readout chain (i.e. sparsified, triggered readout techniques).
Apsel VI and Superpix1 have been designed in the Globalfoundries-Tezzaron 130 nm 3D CMOS process.
FEE 2011-Bergamo, 23-27 May 2011
DNW MAPS
DNW MAPS and hybrid pixels in 3D Technologies
The inversely biased DNW acts as a collecting electrode.
Hybrid pixels
A readout chain is used for Q-V conversion gain decoupled from CDNMOS analog FE devices are built-in in the deep N-well. PMOS can be included in the design and placed in a separate layer charge collection efficiency close to 100%.
Back to back assembled devices from two chips, by means of bump bonding techniques. They feature:
high SNR100% fill factorno crosstalk between the digital readout electronics and the sensor
Large material budget innovative direct bonding techniques (Zyptronix or TMicro/ZyCube) In 3D design the use of two layers provides a lot of functionality in the pixel cell.
Digital section
DNW sensorAnalog section
Digital section
Analog section
1st Layer
2nd Layer
sensor
FEE 2011-Bergamo, 23-27 May 2011
In-pixel logic for a time-ordered readoutComplex in-pixel logic can be implemented without reducing the pixel collection efficiency (thanks to 3D integration) even improving the readout performance (readout could be data push or triggered).
Courtesy of F. Morsani (INFN PI)
Timestamp (TS) is broadcast to pixels and each pixel latches the current TS when fires.
Matrix readout is TS ordered A readout TS enters the
pixel and an HIT-OR-OUT is generated for columns with hits associated to that TS
A column is read only if HIT-OR-OUT=1
DATA_OUT is generated for pixels in the active columns with hits associated to that TS.
FEE 2011-Bergamo, 23-27 May 2011
Apsel VI front-end architecture
First stage: charge PA with a CFB countinously discharged by an NMOS biased in deep subthreshold region.Second stage: RC-CR shaper with a transconductor feedback network:
TIER1(botto
m)
TIER2(top)
Vbl chip wide distributed by an external voltage reference (not affected by voltage drop issues) Voltage drop effects reduction on the channel-to-channel dispersion of the DC voltage at the shaper output (Vbl)
Third stage: comparator (placed on the top tier along with the in-pixel readout logic).
FEE 2011-Bergamo, 23-27 May 2011
Charge Preamplifier
Two local feedback networks (M4,M5 and M6,M7) to increase the small signal resistance at the node C.Cp value is a trade-off between noise and bandwidth.
C
MFB is used to discharge CFB after the particle hit.
0
20
40
60
80
100
10 100 1000 104 105 106 107 108 109
Open loop ac response
Vout/Vin [dB]Vo
ut/V
in [d
B]
frequency [Hz]
DC gain=84 dB
F-3dB= 40 kHz
FEE 2011-Bergamo, 23-27 May 2011
Shaping stage
Cascode input stage and output source follower.
First order RC-CR shaping stage:
2)1()(
p
p
stst
sT
tp: peaking time
The transconductor keeps the circuit in the correct bias point and set the output waveform peaking time at the designed value.
It can be demonstrated that, in order to obtain an output waveform with the desired tp (constant at the varying of the input signal amplitude), the following equations must be satisfied:
21
2200
2
1
00
2
11
CCCfAGm
CC
fAt p
A0: open loop DC gain
f0: -3dB cutoff frequency
FEE 2011-Bergamo, 23-27 May 2011
Shaping stage
Mirrored load transconductor with source degeneration resistance.
native
MP
MP
gdsgmgmGm
1
Since C2 value has to be small (≈ 50 fF) for area occupancy reasons, Gm value must be very low (≈ 20 nS) to obtain the desired tp (≈ 300 ns) Itransc ≈ 10-9 A
Standard solution Source degeneration solution
Mirrored load transconductor:
T
DMP
MPMP
nVIgm
gmgmGm
21 Higher Itransc Wider linear range
FEE 2011-Bergamo, 23-27 May 2011
Voltage drop on analog VDD/GND linesMay be an issue with large matrices of relatively current-hungry detectors
DVd=15/20 mV (typ/max)
Voltage drop on the AVDD and AGND lines causes changes in some pixel current sources, in particular in the shaper input branch and in the transconductor.These current changes lead to a degradation of the front-end performance (i.e. charge sensitivity and peaking time).
Apsel VI features: Ianalog_cell=25 μA
128x100 pixels matrix for the next runConsidering the case of a larger matrix (i.e. 256x256 elements), supplied from both sides, we obtain the following voltage drop on AVDD and AGND:
AVDDperipheral
AVDDpixel
AGNDpixelAGNDperipheralM. Manghisoni, E. Quartieri et al.,“High Accuracy Injection Circuit for Pixel-Level
Calibration of Readout Electronics” presented at the 2010 IEEE Nuclear Science Symposium Conference, Knoxville, USA, October 30 - November 6 2010.
I=120 nA
Isib≈120 nA Itransc ≈ 2.5 nA
FEE 2011-Bergamo, 23-27 May 2011
Effects on the shaper output waveform
Voltage drop is simulated as a symmetrical voltage variation in the analog power (AVDD) and ground (AGND) lines.
AVDD=1.5 V-ΔVd, AGND=ΔVd
w/o voltage drop compensation with voltage drop compensation
-0.12
-0.1
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0 2 4 6 8 10
DVD=0
DVD=20 mV
DVD=40 mV
DVD=60 mV
Shap
er O
utpu
t [m
V]
Time [s]
-0.12
-0.1
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0 2 4 6 8 10
DVD=0
DVD=20 mV
DVD=40 mV
DVD=60 mV
Shap
er O
utpu
t [m
V]
Time [s]
ΔVD=60 mVΔVD=40 mVΔVD=20 mVΔVD=0 mV
ΔVD=0 mV
ΔVD=20 mVΔVD=40 mVΔVD=60 mV
FEE 2011-Bergamo, 23-27 May 2011
Effects on peaking time and charge sensitivity
Voltage drop is simulated as a symmetrical voltage variation in the analog power (AVDD) and ground (AGND) lines.
AVDD=1.5 V-ΔVd, AGND=ΔVd
0
50
100
150
200
250
300
350
400
0 10 20 30 40 50 60
w/o compcompensated
Ę t pk
%
Voltage drop [mV]
-20
-15
-10
-5
0
5
0 10 20 30 40 50 60
w/o comp
compensated
Ę G
Q %
Voltage drop [mV]
Cha
rge
sens
itivi
ty v
aria
tion
[%]
Peak
ing
time
varia
tion
[ns]
FEE 2011-Bergamo, 23-27 May 2011
Apsel VI performance
Apsel VICharge sensitivity 850 mV/fCPeaking time 320 nsENC 34 e-
Threshold dispersion before/after correction 103/13 e-
INL (@ 2000 e-) 2.1%Analog power consumption 33 μW/pixelDetector parasitic capacitance
300 fFImplemented structure 128x100 pixelsPixel pitch 50 μm
FEE 2011-Bergamo, 23-27 May 2011
Superpix1 3D hybrid chip front-end architecture
Lower power consumption (Icell ≈ 7μA) reduces the voltage drop effects on the channel-to-channel baseline voltage (Vbl) dispersion current mirror, also less noisy than transconductor.
TIER1(botto
m)
TIER2(top)
C2 linearly discharged by a constant current Imir linear increase of the recovery time with input signal amplitude.
Lower detector parasitic capacitance (CD≈150 fF): lower noise and power consumption
Fine tuning system in order to reduce the threshold dispersion:IDAC is set by a 4 bit current steering DAC in each channel.
DAC driven by a thermometric code decoder.
All in a 50 μm pixel pitch
FEE 2011-Bergamo, 23-27 May 2011
Superpix1 analog front-end
Superpix1Charge sensitivity 48 mV/fC
Peaking time @ 16000 injected electrons
260 ns
ENC 130 e-
Threshold dispersion before/after correction
560/65 e-
Analog power consumption
10 μW/pixel
Detector parasitic capacitance 150 fFImplemented structure 128x32
pixelsPixel pitch 50 μm
Main features
This plot shows that an optimum condition exists for the threshold correction operation (DAC output range ≈5σth):
FEE 2011-Bergamo, 23-27 May 2011
Two different approaches are being considered for the design of the readout chip in view of applications to the SVT Layer0 of the SuberB factory.
Conclusion and future plans
Future steps include the characterization of both the chips (2011-12).
Apsel VI and Superpix1 will be fabricated in the Globalfoundries-Tezzaron 130 nm 3D CMOS technology (to be submitted Q4 2011).
MAPS and hybrid pixels can capitalize on 3D CMOS processes in terms of:
immunity of the analog section (and of the sensor in MAPS) from digital signals increase of the functional density in the pixel cell
higher collection efficiency (MAPS)