A Survey and Comparison of Existing Low Power Ripple-Carry Adders

Kevin Gunn :: Survey and Comparison of Existing Low Power Ripple-Carry Adders

A Survey and Comparison of Existing Low Power Ripple-Carry Adders

CSCE 4233 – Low Power Digital Systems

Kevin Gunn

4/29/2012

1


Abstract

The adder is one of the most common and integral components used in computer

arithmetic. This fact implies that you can lower power consumption of most any circuit if

you utilize lower power adders. The purpose of this project is to study the different

optimizations of the ripple-carry adder circuit. Many different optimizations exist, but we

will focus mainly on the carry skip, carry select, and carry look-ahead adders. These

adders, at first glance, may not seem to offer anything except for an increase in

performance; however, we will look at different ways researchers have discovered to

optimize these specific circuits to achieve power, as well as area, savings. These

optimizations mainly revolve around reducing switching activity and logic levels, or

minimizing extraneous glitches and transitions in the circuit.

Introduction

Adders are an essential circuit when it comes to computer arithmetic. Just like any

other widely used circuit, there exist high-performance as well as low-power

optimizations (and everything in-between) so that designers can choose whatever suits

their specific needs. Obviously, since this is a low power class, we want to focus more on

the low-power optimizations. Low power Adders may be just another tool in the arsenal

of a circuit designer, but they are an important one since adders are used in many circuits.

One of the main things I have learned studying this material is that you take the savings

you can get, wherever you can get it - no matter how small they may be. Those small

savings add up quickly and before you know it, you have a 25% more efficient design!

2


So what I wanted to do for this project was start from the top and go down, so to

speak. Initially the thought was to build a Ripple-Carry adder, then modify it to imitate

some different common optimizations of the circuit. The modifications I chose were the

ones we covered in lecture, which was the original inspiration for this project: the carry

skip, carry select, and carry look-ahead. I also found a trove of information about a series

of different optimizations for each individual modification done by researchers around

the World. So I figured this would be a good opportunity to learn more about a niche area

of Low Power Design, while also being able to gain a better understanding of material we

covered in lecture.

Background

An adder is a digital circuit that performs binary addition operations. Adders can

be used for many things; for example: in arithmetic logic units, in processors for address

calculation, table indexing, and so forth. There are two types of adder: half adder and full

adder. A half adder has two one-bit inputs (A and B) and two one-bit outputs (S and C).

Inputs A and B are added together, and the output is the sum of the two inputs (S) and the

carry (C). The most common implementation of this circuit is simply an XOR gate and an

AND gate [Figure 1]. A full adder adds two one-bit binary numbers (A and B), but takes

it a step further by accounting for and third one-bit input, the carry-in (Cin). So

technically, the circuit adds three binary inputs (A+B+Cin), and has two binary outputs

for the sum (S) and the carry out (Cout). One important concept for this project is the

following Boolean expressions, which logically describe a Full Adder implementation:

Propagate Signal: Pi = Ai XOR Bi

3


Generate Signal: Gi = Ai AND Bi

Where the sum (S) and carry (Cout) signals are then expressed as:

S = Ai XOR Bi XOR Cin = Pi XOR Cin

Cout = Gi OR Pi AND Cin

These signals will be important to know later, as they are integral to the optimizations

studied in this project. There are many different physical implementations of the full

adder, however, but one example can be seen in [Figure 2].

A ripple-carry adder is a logical circuit that utilizes multiple full adders to add

together N-bit numbers. It is called a ripple carry since every Cout is connected to the

Cin, so each bit “ripples” out to the next full adder [Figure 3]. It is a simple

implementation, but the performance is relatively low since each full adder has to wait

for the carry bit to calculate from the previous full adder. This concept is known as gate

delay. To reduce this gate delay, research engineers have devised many different

optimizations of the ripple carry adder. Although these optimizations are not inherently

low power, they themselves can each be modified to obtain low power characteristics.

One such optimization is the carry skip adder. This optimization was first

presented in the 1950’s by Morgan and Jarvis, but has been extensively revised

throughout the years. It is amazing that principles that came about in the 1950s are

coming back to serve us yet again – that is a true testament to reuse! This optimization

takes advantage of the generation and propagation signals – they get divided into blocks

where a logic block can quickly detect if all the bits being added are different (Pi = 1). If

this signal is flagged at all positions, then the Cin signal can bypass it and transmit

through a multiplexer to the next block. This signal then propagates through each block,

4


as if it had been generated at the beginning. This implementation can be seen in [Figure

4]. This design as it stands is faster than a ripple-carry adder but actually consumes more

power. So, this is obviously not good for our purposes. Research engineers Schulte et al,

luckily for us, realized this and proposed a design for a low power carry skip adder. In

their design, the carry skip adders “delay and power dissipation are reduced by dividing

the adder into variable-sized blocks that balance the delay of inputs to the carry chain.

This grouping reduces active power by minimizing extraneous glitches and transitions,”

[1, p.1]. This optimization also utilizes optimized carry look-ahead logic (which we will

discuss next) to reduce delay. Basically, this adder architecture decreases power

consumption through a combination of reducing transistors, glitches, and logic levels.

The next optimization we looked at was the carry look-ahead adder. This

optimization was proposed by Weinberger and Smith in 1958 – another great example of

reuse! This circuit uses a look-ahead technique instead of carry-rippling through to speed

up carry propagation. Generate and propagate signals are used to “pre-process” the carry

ahead of time so that when the actual addition is performed, there is no delay from the

ripple effect. This all happens in the look-ahead carry logic unit. This implementation is

illustrated further in [Figure 5] and [Figure 6]. Again, this optimization is much faster

than the ripple carry adder but it has quite a bit more logic! The logic seen in Figure 6

gets even more and more complicated as block size increases as well. That is where our

research engineers come in, again. Dongho Kim and Tony Ambler proposed a low power

carry look-ahead adder in 2000. Their design “takes advantage of the conditional don’t

care that exists in the generation and propagation signals. Our results show that this

proposed Carry Look-ahead adder can reduce switching activity by 9-11% compared to

5


conventional CLAs,” [2, p.1]. In this paper the relationship between propagate and

generate signals is heavily discussed, and is not really within the scope of this project

report so won’t be discussed. The point is that there are carry look-ahead designs out

there that implement low-power techniques; this one reduces power through a reduction

of switching activity.

The final design we considered in this survey was the carry select adder. This

optimization utilizes redundant hardware to speedup carry calculation. The sums are

computed in parallel, with one row of logic assuming Cin = 1 and the other assuming

Cin = 0. The exact implementation of this can be seen in [Figure 7]. This method is faster

than the ripple carry circuit, however, it is not exactly low-power as it requires redundant

hardware to implement. Once again, though, research engineers have come to the rescue

with a low power implementation of the carry select adder. Woopyo Jeong and Kaushik

Roy proposed a optimization that is based on Dual Transition Skewed Logic (DTSL).

DTSL is a skewed logic style that does not require a clock signal. It utilizes “dual data

paths for data propagation where one path is used for fast propagation of rising

transitions, where the other is used for fast propagation of falling transitions,” [3, p.503].

Again, though, much of this is beyond the scope of our class and can be seen in their

report. By using this method, Jeong and Roy were able to show a 40.4% improvement in

power dissipation over static CMOS Carry Select Adders.

Theory & Application

Using the information gained through my research, I implemented basic deigns of

the ripple carry, carry skip, carry select, and carry look-ahead adders. I designed these

6


circuits using schematics files in the program Quartus II. My original intent was to

compare the Total Thermal Power Estimate of each circuit to verify the facts presented in

the background section. The input vector I used to simulate each circuit can be seen in

[Figure 8, 9, 10, and 11] along with the corresponding outputs for each circuit. The power

estimation tool I used was the Quartus II Power Play Analyzer, with the device set to

Altera Cyclone II.

Results

The functional output of each circuit that I designed can be see in [Figure 8],

[Figure 9], [Figure 10], and [Figure 11]. Each design yielded the correct output

corresponding to its input vectors. This pleased me.

The results that I got from Power Play Analyzer surprised me, at first. Every

design gave me the exact same output for Total Thermal Power Estimate: 30.65 mW. I

didn’t know exactly what to make of it, because it should have gone up for each

subsequent design (RCA < CSkipA < CSelectA < CLA). Thankfully, you clarified in

class that because the circuit is too small for some vector assignments, the design doesn’t

make enough difference to the power of a FPGA to show up on Power Play. All in all,

though, the results make a lot of sense to me now that I have taken all the facts into

consideration.

Conclusion

Overall, I feel like this project was a success. Although my original idea of doing

a project on ASIC low power design did not work out (all the code I was going to re-

7


factor was in C and I could not find a proper tool kit. Synopsys PrimeTime-PX was not

available on the lab machines as I had hoped), I feel like this was a much better topic. I

have learned quite a bit about the different Ripple Carry Adder optimizations and how

they can all be modified to low-power designs. What fascinated me the most, though, in

my research was the fact that most of these optimizations were proposed back in the

1950’s! It really is amazing how much we re-use different designs in this field.

Figures & Diagrams[Figure 1]

[Figure 2]

[Figure 3]

8


[Figure 4]

[Figure 5]

[Figure 6]

9


LOOKAHEAD CARRY UNIT LOGIC

[Figure 7]

[Figure 8] Ripple Carry Adder Output

[Figure 9] Carry Skip Adder Output

[Figure 10] Carry Select Adder Output

10


[Figure 11] Carry Look-ahead Adder Output

11


References[1] Schulte, et al. “A Low-Power Carry Skip Adder with Fast Saturation.” Proceedings of the 15th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP’04).

[2] Kim, Dongho and Ambler, Tony. “Low Power Carry Lookahead Adder by Using Dependency Between Generation and Propagation.” IEEE, 2000.

[3] Jeong, Woopyo and Kaushik, Roy. “Robust High-Performance Low-Power Carry Select Adder.” Purdue University School of Electrical and Computer Engineering. IEEE, 2001. Pages 503-506.

[4]Adder Designs. Accessed 4/28/2012. Last Updated 07/02/2004. <www.acsel-lab.com/Projects/fast_adder/adder_designs.htm>

[5] Adder (electronics). Accesssed 4/28/2012. Last updated 4/25/2012. <en.wikipedia.org/wiki/Adder_(electronics)>

12

Documents

A Survey and Comparison of Existing Low Power Ripple-Carry Adders