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1-1-1981
A study of two-dimensional effects in metal/amorphous silicon/ N/P+ silicon switchingdevices.Mark E. Turner
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A STUDY OF TWO-DIMENSIONAL
EFFECTS IN METAL/AMORPHOUS SILICON/
N/P+ SILICON SWITCHING DEVICES
by
Mark E. Turner
A Thesis
Presented to the Graduate Committee
of Lehigh University
in Candidacy for the Degree of
Master of Science
in
Electrical Engineering
Lehigh University
1981
ProQuest Number: EP76672
All rights reserved
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uest
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This thesis is accepted and approved in partial
fulfillment of the requirements for the degree of
Master of Science.
Date /7W
ProFelTsdr in Charge
CriaTrman of Department
11
ACKNOWLEDGEMENTS
I would like to express my appreciation to
Prof. J. G. Simmons who suggested the topic and pro-
vided guidance during the course of the work.
I am most grateful to Dr. L. Faraone of R.C.A.
Laboratories, Princeton, NJ, for teaching me silicon
processing techniques, helping me understand device
operation, and for many invaluable suggestions and
advice throughout this work.
A word of thanks to Ms. Jeanne Loosbrock for the
excellent typing of this thesis.
Finally, I would like to acknowledge the National
Science Foundation for its support of this research
(under grant ECS-7098364) and the Department of
Electrical Engineering for the Teaching Assistantships
awarded to me for the Spring and Fall semesters of
1980.
111
DEDICATION
For giving me and many others so much love and
hope, this thesis is dedicated to my parents.
IV
TABLE OF CONTENTS
Page
List of Symbols
Abstract 1
CHAPTER 1, INTRODUCTION 3
1.1 The Metal Insulator Semiconductor Switch 3
1.2 Historical Perspective 7
1.2.1 Recent Work by Simmons and Coworkers 10
1.3 The Metal Insulator Semiconductor Thyristor 12
1.4 The Objective and Outline of This Thesis 15
References 17
CHAPTER 2 20
2.1 The Punch-Through MISS Versus the Avalanche MISS 20
2.2 General Equations • 26
2.2.1 Voltage Equations 26
2.2.2 Current Equations 28
2.3 The Ideal Punch-Through MISS 31
2.3.1 High Impedance Characteristics 31
2.3.2 Punch-Through to Switching; The Regenerative Feedback Mechanism 34
2.3.3 The Switching Point and the Negative Resistance Region 37
2.3.4 Low Impedance ON State 39
2.3.5 Switch Off Mode 41
2.3.6 The Non-Ideal Punch-Through MISS 42
v ,
Page ii:
2.4 Two Dimensional Effects 43
2.4.1 Experiment and Theory of Two- Dimensional Effects 43
References 49
CHAPTER 3, EXPERIMENTAL TECHNIQUES 50
3.1 Fabrication Procedure 50
3.1.1 Field Oxide Growth 50
3.1.2 Amorphous Silicon Deposition 54
3.1.3 Metallization and Electrode Definition 56
3.2 Measurement Technique 58
3.2.1 Slow Voltage Ramp 58
References 62
CHAPTER 4, RESULTS AND DISCUSSION OF THE VIRGIN OFF STATE . 63
4.1 Typical Virgin OFF States 63
4.2 The Punch-Through Point 67
4.3 From Punch-Through Through Switching 73
References 79
CHAPTER 5, RESULTS AND DISCUSSION AFTER VIRGIN SWITCHING 80
5.1 Experimental Results and Preliminary Discussion 80
5.1.1 Experimental Results 80
5.1.2 Discussion 83
5.2 Properties of Amorphous Silicon 89
vi .
Page
5.2.1 Amorphous Silicon Switches 89
5.2.1.1 The Electro-thermal Model of Switching in Amorphous Silicon 90
5.2.2 Processing Effects 93
5.2.2.1 Deposition Rate Effects 93
5.2.2.2 Origin of the Virgin State 94
5.3 Conclusions 95
References 97
APPENDICES
Appendix A Pre-furnace Cleaning Procedure 98
Appendix B Shipley Photoresist (PR) Procedure 100
Appendix C Cleaning Procedure for Aluminum 102
Appendix D Supplementary Experimental Data 103
VITA 118
vii
LIST OF SYMBOLS
d. semi-insulator thickness
D ,D diffusion constants for electrons and holes n p
E band gap energy o
G open loop gain of the device
I„ holding current
I _ off state current
I switching current s b
J current through the device
J generation current g
J . electron current through the semi-insulator n ins &
+ J . electron diffusion current in the p substrate
J • hole current through the semi-insulator p ms &
J . hole injection current reaching the IS ni interface
J . . hole diffusion current in the n epitaxial P-" layer
J . recombination current m the p -n iunction
J recombination current in the neutral epi-layer rn J
k Boltzmann constant
K constant
L ,L diffusion lengths of electrons and holes n p to
M multiplication factor
N substrate doping
N , epitaxial layer doping
viii -
n. intrinsic carrier density
p (o) hole concentration at the surface rn
q electronic charge
Q , depletion charge
Qp insulator fixed charge
Q. surface inversion charge
Q. interface trapped charge
Q DC insulator charge xss b
R, load resistor
T temperature
V voltage across the device
V applied voltage a.
V, , avalanche breakdown voltage of the epitaxial layer
Vf, flat band voltage
V„ holding voltage
V. voltage across the semi-insulator
V. p n junction voltage
VpT punch-through voltage
VD voltage across the load resistor
V switching voltage
W epitaxial layer thickness
W. p n junction depletion width
W neutral epi-layer width n r J
X, depletion width
X high field region where multiplication occurs
ix
6- current gain of the p -n junction
Yjc current gain of the interface
AI • incremental change in I n ins & n ins
AI . incremental change in I .
e. permittivity of the semi-insulator
e_ permittivity of the semiconductor
a . electron conductivity of the semi-insulator n ms J
o . hole conductivity of the insulator p ms J
T generation lifetime g
T^ carrier lifetime in the p -n junction depletion region o
"MS
n
o
metal semiconductor work function difference
potential associated with n-type semiconductor
built in junction potential
<p semiconductor surface potential
x
ABSTRACT
The effects of device area and amorphous silicon
thickness on the two-terminal DC characteristics on
non-isolated metal/amorphous silicon/N/p silicon
switching devices have been studied.
Experiments show that prior to any switching
(the virgin OFF state), the amorphous silicon has a
very low conductivity and the switching voltage is
relatively high. After switching and a short stabili-
zation period, the conductivity is increased by several
orders of magnitude and the switching voltage has de-
creased. Also, it is found that devices using amor-
phous silicon as the semi-insulator are found to behave
as a compound switch, due to the fact that bulk amor-
phous silicon acts as a current controlled switch in
combination with the basic MISS characteristic.
1 2 The theory developed by Simmons,' et al., is
used with appropriate modifications to explain the
device characteristics, and qualitative reasons are
suggested to explain the change in conductivity.
References
K. A. Duncan, P. D. Tonner, J. G. Simmons, and L. Faraone. "Characteristics of Metal/Tunnel- Oxide/N/P Silicon Switching Devices. Part 1: Effects of Device Geometry and Fabrication Processes." To be published.
L. Faraone, U. K. Mishra, F. Hseuh, and J. G. Simmons. "Characteristics of Metal/Tunnel Oxide/ N/P Silicon Switching Devices. Part II: Experi- mental Observation of Two-Dimensional Effects in Isolated Structures." To be published.
CHAPTER 1
INTRODUCTION
1.1 THE METAL INSULATOR SEMICONDUCTOR SWITCH
Interest has grown in the past few years on a
relatively new bistable latching device known as the
MISS (for Metal-insulator-n/p s_ilicon switch). The
device has a very fast switching time and is compatible
with existing IC technology. A cross-sectional view
of the basic device structure is shown in Fig. 1.1a.
It is fabricated on p substrates on which an n-type
epitaxial layer has been grown. The semi-insulating
layer is then thermally grown (SiO-) or deposited (all
others) using various means. Finally, metal contacts
are made both to the semi-insulating layer and the p
substrate. The resultant "sandwich" consists of con-
tact metal/semi-insulating layer/n-p substrate.
The attractive features of the MISS device are
the following:
1. performs as a bistable switch (a function not
easily available in integrated circuits).
2. has a high switching speed, and
3
metal , . contacrAU
semi- insulator
epitaxial
layer(n)
substratefp*)
metal contact(AD
Fig. 1. la Schematic of basic MISS structure (not drawn to scale).
4
3. is easy to fabricate and is compatible with
existing IC technologies.
When the device is biased in such a way that the
p -n junction is forward biased the MISS performs the
function of an electronic switch (see Fig. 1.1b). The
I-V curve resembles that of a Shockley diode (pnpn
diode), and in direct analogy to that device, V is de-
fined as the switching voltage, I the switching cur-
rent, VR the holding voltage, and I„ the holding cur-
rent. The ratio of the 'OFF' state to 'ON' state
static impedances is typically 10 . The advantages the
MISS possesses over the pnpn diode are: (a) less high
temperature processing is required during fabrication,
and (b) the device is readily integrable; that is, it
can be fabricated using standard IC processing tech-
niques .
In fabricating the MISS device, thin silicon di-
oxide (20-100 A) for the semi-insulating layer has been
studied extensively (1-1,3-5,7-13,15-21), but the ex-
pected practical difficulties of producing tunnel oxides
on a manufacturing basis has raised interest in other
semi-insulators. Adan and Dubos (1-2) studied MISS
devices with tin-oxide as the semi-insulator. Kroger
and Wegener (1-3) studied silicon nitride, undoped
polycrystalline silicon, amorphous silicon, and other
5 ' '* '
met a!
semi- insulator
Device Voltage, V
Fig. 1.1b Schematic of the I-V curve of a MISS device defining the parameters I , V , I and V,, that characterize
, , s s H H the device.
INSET: Basic MISS structure,
6
materials for the semi-insulator, with only minor ef-
fects on the characteristic. Several applications of
the MISS device have been suggested (1-4), including
a static RAM, a photodetector and a relaxation oscilla-
tor .
1.2 HISTORICAL PERSPECTIVE
The first MISS device was reported by Yamamoto,
et al. (1-1) in 1972. Although they were uncertain of
the switching mechanism, they suggested controlled
inversion of the insulator-silicon interface layer as
playing an important role. In later work (1-5), they
measured the turn-on time of about 2 nsec and a turn-off
time of about 1 nsec. They also fabricated a simple
shift register using MISS devices as the key elements,
began life testing a device, examined the dependence
of the switching voltage on illumination, and studied
the characteristics of a three terminal device.
Kroger and Wegener (1-6) used silicon-nitride as
the semi-insulator. This began their studies of various
metals and semi-insulators. Later on (1-3), they
studied chromium, aluminum, and molybdenum for the
metal contact, and silicon dioxide, silicon oxynitride,
undoped polycrystalline silicon, amorphous germanium
and sputtered amorphous silicon for the insulator layer.
7
All the devices fabricated with these materials exhi-
bited the standard MISS switching characteristic.
Kroger and Wegener showed that the impedance of the
MISS device is controlled by the presence or absence
of an inversion layer at the insulator-semiconductor
interface. They also found the necessity of having an
insulator that is slightly conductive, i.e. a semi-
insulator .
For several semi-insulating materials, including
sputtered amorphous silicon, Kroger and Wegener ob-
served a virgin state. When the device was biased for
the first time, the switching voltage was about 20%
higher than subsequent switching events. They attri-
buted this change to permanent filling of deep traps
within the insulator or at the semiconductor surface.
Temperature-bias stressing was attempted to restore the
original virgin state switching voltage without success.
This thesis will attempt to look at this virgin state
problem more closely in a later section.
In the early work of Yamamoto, et al. (1-5) and
Kroger and Wegener (1-6), the OFF state was recognized
as corresponding to deep depletion of the semiconductor.
The inversion charge does not accumulate at the semi-
conductor-insulator interface because the holes reaching
the surface are swept away through the leaky insulator.
The ON state was recognized as corresponding to an
inversion layer at the insulator-semiconductor inter-
face which is continuously supplied with minority
carriers by the forward biased p -n junction. However,
the switching mechanism between the two states was not
very well understood.
Yamamoto, et al. (1-1), initially proposed a po-
sitive feedback mechanism based on carrier multiplica-
tion at the MIS interface. In a later work, Simmons
and El-Badry (1-7,1-8) presented two models of switching,
namely: 1) punch-through and 2) avalanche mode. In
the punch-through mode, the depletion region reaches
15 3 through the lightly doped (<10 /cm ) epitaxial layer
to the p -n junction. For higher doped material (>10 / 3
cm ), avalanching occurred before - punch-through and was
responsible for switching. Recently, Habib and Simmons
(1-9,1-10) have shown that these switching mechanisms
are special cases of a more general switching mechanism,
the Regenerative Feedback Mechanism (or RFM). By ana-
lyzing all the currents flowing in the device, the
components of the feedback loop are identified. Both
methods of switching are derived theoretically in a
rigorous manner and are shown to depend on the RFM for
switching. The difference between these two mechanisms
is the method for initiating the RFM.
9
1.2.1 Recent Work by Simmons and Coworkers
Most recently, in a series of three papers (1-11,
1-12,1-13), Simmons and coworkers have studied the
effects of tunnel oxide area, tunnel oxide thickness,
and p -n junction area on the RFM, using punch-through
devices.
In the first paper (1-11) , a study of device geo-
metry and fabrication processes was carried out. It
was found that in order to have the devices operate in
the ideal mode, i.e. V„ - VpT, the area of the device
must not be so small that current fringing dominates,
which weakens the RFM, nor so large that the RFM is
strengthened to the point that switching can occur
before punch-through and |V„|<|Vp„| (the non-ideal
mode). Furthermore, care must be"taken in design so
that the inversion voltage of the field oxide exceeds
the punch-through voltage of the device. If this is
not done, the device will switch at the threshold
voltage of the field oxide as the inversion charge
flows in from under the field oxide and causes the de-
vice to switch prematurely.
Another area of concern in design is when choosing
a starting epitaxial layer thickness in order to obtain
a desired punch-through voltage. An allowance must be
10
made for up-diffusion of the p layer due to high tem-
perature processing.
In the second paper (1-12), a systematic experi-
mental investigation was made of the effects of tunnel
oxide area and thickness and the area of the V-groove
isolated p -n junction on the I-V characteristics. It
was found that for a given oxide thickness and area, the
switching voltage and holding current of the device in-
crease with isolation area, but that the switching
current was essentially constant. For increased oxide
thickness, both the switching current and holding cur-
rent decreased.
From the experimental results, it is shown that
switching from the OFF state to the ON state is com-
pletely oxide controlled and is solely dependent on the
minority, carrier concentration at the Si-SiO~ interface.
In the third paper (1-13), a two dimensional model
is developed which satisfactorily explains the area
effects observed in the first two papers. The model
considers the effect of p -n junction area with regard
to its influence on two terminal DC characteristics, in
particular the switching voltage, the switching cur-
rent, and the holding current. The calculations based
on this model are shown to be in good agreement with the
experimental data.
11 - - •
1.3 THE METAL-INSULATOR-SEMICONDUCTOR THYRISTOR (MIST)
By adding a third (gate) terminal to the basic MISS
structure electrical control of the feedback loop is
possible. This is done with an ohmic contact to the
'n' epitaxial layer (see Fig. 1.2a). By applying an
appropriate bias, carrier injection (or extraction)
will strengthen (or weaken) the feedback mechanism,
thus decreasing (or increasing) the voltage required to
switch the device. The I-V characteristics (Fig. 1.2b)
are similar to those of a thyristor, and the device
has been named the MIST, for Metal-Insulator-Semicon-
ductor Thyristor.
Kroger and Wegener (1-14) were the first to study +
the MIST structure. By forward biasing the n -p
junction, the switching voltage was reduced.
Yamamoto, et al. (1-5), discovered a linear rela-
tionship between the gate current and switching voltage
for both positive and negative currents. For positive
current (forward biasing the p-n junction), the switch-
ing voltage decreased and for negative current (reverse
bias), the switching voltage increased.
Chik and Simmons (1-15) discussed the effects of
the gate by considering the effect on the gain of the
regenerative feedback mechanism. Later Habib and
12
CGthode(A|)
semi-insulator. gnte(AI)
diffusion (n*)
epitaxial layer( n )
substrate( p )
anode(Al)
Fig. 1.2a The basic three terminal MIST structure, (not drawn to scale)
13
U
u >
Q mi1-0
Device Voltage ,V
Fig. 1.2b MIST device I-V characteristics.
INSET: Basic structure.
(After Chik and Simmons [1- J).
14
Simmons (1-16) extended their model of the MISS (1-9,
1-10) to the MIST device. They develop closed form
expressions applicable to the MIST for both punch-
through and avalanche modes of switching. They also
show that the gate control efficiency is largest for an
avalanche MISS with a majority-carrier injecting gate.
1.4 THE OBJECTIVE AND OUTLINE OF THIS THESIS
The main objective of this thesis is to study the
effects of using amorphous silicon as the semi-insula-
tor in the MISS structure. To date tunnel-oxides have
been studied extensively, but are somewhat incompatible
with industrial fabrication procedures. Amorphous
silicon is a possible solution because film deposition
is a low temperature process and requires no special
handling during fabrication. Another motivation was
to further study the effects of semi-insulator thick-
ness and device area on the I-V characteristics of MISS
devices as studied by Simmons and coworkers (1-11,
l-]2, 1-13).
An important outcome of the study was that using
amorphous silicon is more complex than using a tunnel-
oxide as the semi-insulator. MISS devices using amor-
phous silicon are found to behave as a compound switch,
due to the fact that bulk amorphous silicon acts as a
15 • - •
current controlled switch in combination with the basic
MISS characteristic.
The presentation is organized in the following
manner:
In Chapter 2 the basic two-terminal DC theory of
the MISS device is presented,
Chapter 3 includes a description of the fabrica-
tion processes and the measurement techniques used.
In Chapter 4 the experimental results of the
virgin OFF state are presented.
In Chapter 5, the experimental results after
stabilization are presented and discussed. The pro-
perties of amorphous silicon are examined and con-
clusions concerning amorphous silicon MISS devices are
presented based on the results of■these experiments.
16
REFERENCES
1-1 T. Yamamoto and M. Morimoto. "Thin-MIS-Structure Si Negative Resistance Diode," Applied Physics Letters, 20, 269 (1972) .
1-2 Armando Adan and Karoly Dobos. "New Types of Metal-Insulator-Semiconductor-Switch," Solid State Electronics, 23, 17 (1980).
1-3 H. Kroger and H.A.R. Wegener. "Steady-State Characteristics of Two Terminal Inversion-Con- trolled Switches," Solid State Electronics, 21, 643 (1978).
1-4 A. El-Badry and J. G. Simmons. "Switching pheno- mena in metal-insulator-n/p structures: theory, experiment and applications," Radio and Electronic Engineer, 48, 215 (1978).
1-5 T. Yamamoto, K. Kawamura, H. Shimuzu. "Silicon p-n Insulator-Metal (p-n-I-M) Devices," Solid State Electronics, 19, 701 (1976).
1-6 H. Kroger and H.A.R. Wegener. "Bistable Impedance States in MIS Structures Through Controlled In- version," Applied Physics Letters, 2_3, 397 (1973).
1-7 J. G. Simmons and A. El-Badry. "Theory of_ Switch- ing Phenomena in Metal-Semi-Insulator/n-p Silicon Devices," Solid State Electronics, 20, 955 (1977).
1-8 A. El-Badry and J. G. Simmons. "Experimental + Studies of Switching in Metal Semi-insulating n-p Silicon Devices," Solid State Electronics, 20, 963 (1977).
1-9 S. E-D. Habib and J. G, Simmons. "Theory of Switching in P-N-Insulator(Tunnel)-Metal Devices Part I: Punch Through Mode," Solid State Elec- tronics, 22, 181 (1979).
1-10 S. E-D. Habib and J. G. Simmons. "Theory of p-n- Insulator(Tunnel)-Metal Devices - II. Avalanche Mode," Solid State Electronics, 23, 497 (1980).
17
1-11 K. A. Duncan, P. D. Tonnor, J. G. Simmons, and L. Faraone. "Characteristics of Metal/Tunnel Oxide/ N/P Silicon Switching Devices. Part I: Effects of Device Geometry and Fabrication Processes," to be published.
1-12 L. Faraone, U. K. Mishra, F. Hseuh, and J. G. Simmons. "Characteristics of Metal/Tunnel Oxide/ N/P Silicon Switching Devices. Part II: Experi- mental Observation of Two-Dimensional Effects in Isolated Structures," to be published.
1-13 L. Faraone, F. Hseuh, U. K. Mishra, J. G.,Simmons, Characteristics of Metal/Tunnel Oxide/N/P Silicon Switching Devices. Part III: A Simplified Model for Two-Dimensional Effects in Isolated Struc- tures," to be published.
1-14 H. Kroger and H. A. R. Wegener. "Controlled In- version Transistors," Applied Physics Letters, 27, 303 (1975).
1-15 K. D. Chik and J. G. Simmons. "Characteristics of Three-Terminal Metal-Tunnel Oxide-n/p Devices,' Solid State Electronics, 22, 589 (1979).
1-16 S. E-D. Habib and J. G. Simmons. "Theory of Metal- Insulator-Semiconductor Thyristor," IEE Proc., 127, 176, 1980.
1-17 M. .Darwish and K. Board. "Switching in MISM and MISIM structures," to be published.
1-18 Yutaka Hayashi. "Switching Phenomena in thin- insulator metal-insulator-semiconductor diodes." Applied Physics Letters 37(4), 407 (1980).
1-19 J. Buxd, A. E. Owen, G. Sarrabayrouse and J. P. Sebbaa. "Tb.e Characterisation of Metal-Thin In- sulator-n-p Silicon Switching Devices," Revue de Physique Appliqu£e, 13, 767 (1978).
1-20 J. Millan, F. Serra-Mestres, and J. Buxd. "A Criterion for Determining the Switching Voltage of Metal-thin insulator-Si(n)-Si(p ) Device," Revue de Physique Appliqu£e, 14, 921 (1979).
18
1-21 G. Sarrabayrouse, J. Buxd , A. Muhoz-Yagiie, A. E. Owen, J. P. Sebaa. "Dynamic Properties of Switch- ing in MISS Structures and Applications to Charge Transfer Devices," Inst. Phys. Conf. Ser. No. 50, Ch. 3 (1980).
1-22 G. Sarrabayrouse, J. Buxd, A. E. Owen, A. Munoz- Yagiie, J-P. Sabaa. "Inversion Controlled Switch- ing Mechanism of MISS Devices," IE Proc. 127, 119 (1980).
19
CHAPTER 2
In this chapter, the basic DC theory of the MISS
is presented.
First, the avalanche mode will be discussed in
order to differentiate it from the punch-through mode.
The major concern of the chapter will be the "ideal"
punch-through MISS. By "ideal" it is meant those de-
vices in which the surface depletion region reaches
through to the junction depletion region before switch-
ing. The positive regenerative feedback mechanism is
examined.
Finally, the effects of device area and semi-
insulator thickness on the I-V characteristics as stud-
ied by Simmons and coworkers (2-1,2-8,2-9) will be
presented.
2.1 THE PUNCH-THROUGH MISS VERSUS THE AVALANCHE MISS
Simmons and El-Badry (2-2) were the first to pro-
pose that there are two switching mechanisms for the
MISS, namely avalanche mode and punch-through mode.
20
In the avalanche mode, the electron tunnel current,
J ., along with any generation current, J , is multi- nt ° S
plied by impact ionization in the high field region,
X (see Fig. 2.1). This electron current in injected
+ . . into the p -n junction and is expressed as
J • = M(J „ + J ) (2.1) nj nt g'
where M = .. ..,„— (2.2) 1 v/vbd
where V is the voltage across the device and V, , is
the breakdown voltage of the epitaxial material. This
electron current biases the junction and when the
junction is sufficiently biased, the regenerative feed-
back mechanism (discussed in section 2.3.2) is ini-
tiated and the device switches.
The-breakdown voltage of the epitaxial material,
and thus the switching voltage of the device, is given
(2-3) as
Vs = Vbd , -60<^)3/2<^r3/4 (2.3)
where E is the band gap energy and N, is the epitaxial
layer doping.
For lightly doped epitaxial layers, the surface
depletion region extends to the p -n junction deple-
tion region at a voltage less than the avalanche
21
J n ins
qV
currcnt flow >
carrier flow <H
-»►
MJ . 4 mnS »
Fig. 2.1 The avalanche mode MISS just prior to switching.
22
breakdown voltage. This punch-through voltage is given
as
Vpt = -qVW2/2es = ^PT (2-4)
where q is the electronic charge, e is the permitti-
vity of silicon, W. is the p -n junction depletion
width, and W is the epitaxial layer thickness. W. is
expressed as
Wj = (2es((})o+V.)/qNd)% (2.5)
where V. is the p -n junction bias (<0 for forward
bias, >0 for reverse bias), <p is the built in junction
potential and is expressed as
<f0 = ^ In(-2/) , (2.6) 4 n.
l
k is Boltzmann's constant, T is temperature, N is the 3.
substrate doping and n. is the intrinsic carrier den-
sity and is expressed as (2-4)
ni = 3.98 x 1016 T3/2 exp(-7014/T) (2.7)
The energy band diagram of the punch-through MISS
near switching is given in Fig. 2.2. It can be seen
that any further voltage increase will begin lowering
the potential energy barrier of the p -n junction. This
will inject a large number of holes, which will increase
23
arrows indicate direction
of carrier flow
Fig. 2.2 The punch-through mode MISS close to the switching voltage.
24
the free hole density at the insulator-semiconductor
interface. This results in an increased voltage across
the insulator which leads to increased electron tunnel
current. These electrons complete the positive feed-
back loop by further biasing the p -n junction. The
device switches when the loop gain is equal to one. The
theory of the punch-through MISS developed by Habib
and Simmons (2-5) is discussed in more detail in the
following sections.
25
2.2 GENERAL EQUATIONS
The normal configuration of the device is shown
in the inset of Fig. 2.3 where R, is a load resistor
used to limit the current through the device. The
applied voltage, V , is given as a
V = V + VD (2.8) a R
where VR is the voltage drop across the load resistor, +
and V is the voltage across the MISS device. The p
substrate is grounded and a negative voltage is applied
to the metal contact (this forward biases the p -n
junction). The current is defined as positive for
current flowing away from the metal contacting the semi-
insulator .
2.2.1 Voltage Equations
The"voltage across the MISS (see Fig. 2.3) can be
expressed as
V = *MS + Vi + *s + Vj • (2-9)
where <2>Mq is the metal-semiconductor work function dif-
ference, V. is the voltage across the semi-insulator, <j>
is the semiconductor surface potential, and V. is the
voltage across the p -n junction.
The voltage across the semi-insulator, V., is
expressed as
26
E Fm
o 4
direction of carri cr f I ow Va(-ve)
Fig. 2.3 The MISS in the OFF state with component currents. INSET: Basic circuit configuration for the MISS.
27
d. V. = -(Q. + Q, + Q )^ (2.10) 1 vxi xd xss c.
where Q. is the surface inversion charge per unit, d.
is the semi-insulator thickness, e. is the permitti-
vity of the semi-insulator, and Q is the DC insulator
charge and includes Cv, the fixed charge, and Q. , the
interface trapped charge. Q, is the depletion charge
and is dependent on <j) in the following way
Qd = (2qNd|cJ)s|)% . (2.11)
It will be assumed that Q is small relative to xss
Q. and Q, and will be neglected. Thus Eqn. 2.10 be-
comes
d. V. = - (Q. + CO — (2.10a) l vxi xd e ■
2.2.2 Current Equations
The current through the device, J, consists of
both hole and electron current. Since all the current
must pass through the semi-insulator, it can be ex-
pressed as
J = J . + J . (2.12) n ins p ms
where J . is the current through the semi-insulator n ms b
to the conduction band of the semiconductor and J p ms
is the current through the semi-insulator to the valence
band. ' 28
From continuity considerations (see Fig. 2.3),
the currents are given as
J . =J.+J.-J+J (2.13a) n ms rj nj g rn
and J . = J . + J - J (2.13b) p ms pj g rn
where J . is the recombination current in the p -n
junction space charge region, J . is the electron dif-
fusion current in the p substrate, J . is the hole PJ
diffusion current in the 'n' epitaxial layer, J is
the generation current in the surface depletion region,
and J is the recombination in the neutral epi-layer. rn f J
The generation current in the surface depletion
region is given as
qniXd J = n X Q (2.14) g 2T V
J
where x is the generation lifetime. The depletion
width, X,, depends on the surface potential and is
given by
2e | * | Xd ' (q-R7^) ' (2'15)
The generation current contributes to both the hole and
electron currents. It is observed experimentally
(Ch. 4), however, that these currents are very small
and will be neglected from here on.
29
Since there is very little recombination in the
neutral epi-layer, that is J = 0, the hole current rn
reaching the IS interface, J ., is equal to the hole a ' pi' M
injection current, or J . - J .. Hence, eqns. 13a pi pj M
and b become
J . = J . + J . (2.13c) n ins rj nj
J • = J . - J . (2.13d) p ms pj pi
The junction recombination current is given (2-6)
qn ' q|V.|/2kT J . = - ^ W. e J , (2.16) rj 2TQ J
where T is the carrier lifetime in the junction deple-
tion region.
Taking a long base approximation, the junction
diffusion currents are given (2-6) as
q D n2 q|V.|/kT Jnj = N\ (e J - 1) (2.17a)
J an
q D -n2 q|V |/kT
rj dp
where D and D are the diffusion constants for elec- n p
trons and holes, and L and L are the electron and ' n p
hole diffusion lengths.
30
The currents J . and J . are not as easily p ins n ins J
evaluated. Equation 2.12 could also be written
V.
n ms p ins n ins p ms J d. (2.18)
where o . and a . are the electron and hole con- n ms p ms
cuctivities of the semi-insulator, respectively. For
some materials, such as thin SiO~ films, the theory
has been studied extensively, but the separation of
hole and electron tunnel currents has not been studied
experimentally. Most materials, it would seem, would
not even have constant conductivities as a function of
voltage, thus further complicating their study.
2.3 THE IDEAL PUNCH-THROUGH MISS
2.3.1 High Impedance Characteristics
When a negative voltage is applied to the metal,
with the substrate grounded, the p -n junction is for-
ward biased and the IS interface goes into depletion for
voltages above Vf, . Because the insulator is conduct-
ive, any holes that are injected to the interface
(neglecting generation and recombination in the epi-
layer) from the p -n junction do not accumulate, but
are extracted through the semi-insulator.
As the voltage increases, the device goes into
deep depletion (see Fig. 2.4). The dynamic impedance
31 '^
.< direction of earner flow
->
Fig. 2.4 Band diagram of the MISS device in the high impedance state.
32
is very high and very little current flows with an
increase in voltage. This means that the bias across
the junction and the bias across the semi-insulator are
essentially constant. Almost all of the applied bias
is dropped across the surface depletion region. Eq.
2.9 can thus be written
V = K + <j>s , (2.19)
where K = $MO + V. + V. (2.19a) MS j l v '
and is approximately constant.
The electron current through the insulator J . , b n ins
is very small, and because of the very small junction
voltage and because N >>N, the electron diffusion to ad
current, J ., is neglected and the electron continuity
equation (2.13c) reduces to
J . = J . (2.20) n ms rj
The maximum value of the surface potential occurs
when the surface depletion region extends to the junc-
tion depletion region. Combining Eq. 19 and Eq. 4,
the punch-through voltage is expressed as
Vpt = K - q Nd(Wn-W.)/2es (2.21)
33
2.3.2 Punch-Through to Switching; the Regenerative
Feedback Mechanism
Any further increase in the surface potential be-
yond VpT serves to lower the p-n junction potential
barrier. This causes a large number of holes to be
injected. This is seen experimentally as a sharp in-
crease in the measured current. A band diagram of the
MISS device between punch-through and switching is
shown in Fig. 2.5.
By combining equations 10a and 18 we get
(Qd+Qi} J . = o . ——— . (2.22) n xns n ms e.
It is seen that as the inversion charge at the surface
increases, the field in the semi-insulator increases
which consequently increases the electron current
through the semi-insulator, J . . These electrons
then flow into the p-n junction, further biasing it.
The current gain of the junction, £., is defined as
J . Q = HJ (2 23) yj J .+J . • ^.^; J nj rj
The main elements of the feedback loop have been
identified. There are two gain elements: the p n diode
and the IS interface. Since it is a positive feedback
system, or regenerative, it is called the Regenerative
34
direction of carrier flow
*■ •
Fig. 2.5 Band d lagram of the MISS device between punch-through and switching.
35
Feedback Mechanism, or RFM. For the one-dimensional
case, the gain of the p n junction in this device can
be very large, on the order of 10 since N >>N, once the J b ad
junction voltage is sufficiently high so that the in-
jected diffusion current predominates over the junc-
tion recombination current (see Eq. 2.23).
The gain of the IS interface can vary greatly. It
is defined as
J . a . n ms n ins ,0 0/ N p ms p ms
The conductivities depend solely on the properties of
the semi-insulator. For some materials, YTO may be
very small compared to one, while for others it may
be greater than one.
The total open loop gain of the device, G, has
been identified by Habib and Simmons (2-5) as
AI . G = Al
n lns (2.25)
where AI . = incremental change in electron current n ms b
through the semi-insulator
AI . = incremental change in "junction recom-
bination current.
36
In the region between punch-through and switching,
the gain of the device is less than unity and a stable
situation is reached (see Fig. 2.5). The IS interface
is only slightly inverted and the depletion region has
not collapsed, even though the currents are higher than
in the high impedance region before punch-through. The
device is still in the OFF state.
When the gain of the open loop is equal to one,
the device switches and enters the negative resistance
region of the MISS I-V characteristic. The physical
properties involved in the negative resistance behavior
are explained in the following section.
2.3.3 The Switching Point and the Negative Resistance
Region
In addition to the device gain being equal to one
at the switching point, Simmons, et al. (2-7) con-
cluded that the switching mechanism is almost completely
controlled by the characteristics of the tunnel-oxide.
For a given tunnel-oxide thickness and area, the switch-
ing current, I , is essentially constant and at the
switching point, I • , and consequently p (o), is
also essentially constant. This was found to be true
independent of the substrate parameters, as long as
N >>N,, and recombination in the neutral epilayer
was negligible.
37
In general, for semi-insulators other than tunnel-
oxides, it seems reasonable to replace "tunnel-oxide"
with the appropriate material under study.
For the region beyond switching, consider a small
incremental voltage increase, AV, beyond V , the switch-
ing voltage. Since V is the maximum voltage possible
across the device, the excess voltage will appear
across the series load resistor, R~ . The device cur-
rent will then be
I - ^ • (2.26) RL
Even with AV = 0.1 V and RL = 10 kfi, the current will
be
1 * fek4= 10^A • <2-26a>
This current is much greater than Inpp. Since the
junction voltage depends logarithmically on I, the
assumption that the excess voltage appears across R,
is valid.
The slight increase in V., however, causes a
large sudden increase in the hole injection current
reaching the IS interface. This build-up of holes
causes a redistribution of the voltage across the de-
vice. The surface depletion region starts collapsing
The change in surface potential is taken up by the
load resistor,
38
R~ , the semi-insulator and the p -n junction. Because
the semi-insulator and junction currents exhibit large
increases with small changes in V. and V., most of the
voltage drop across the device is absorbed by the
series resistor. This voltage decrease across the de-
vice combined with an incj:ea_se ^n current gives rise
to a negative resistance characteristic. The device
switches.
2.3.4 Low Impedance ON State
During switching, the surface depletion region
keeps collapsing and $ continuously decreases. It
stops when <J> reaches its strong inversion value given
as (2-3),
IN \ 4> - 2<J> = — In — . (2.27) Ys rn q n. I
Figure 2'. 6 shows the energy band diagram of the MISS
in the low impedance ON state, that is, with (j> = 2<J) .
The holding voltage, V„, which is the minimum
voltage required to deep the device in the low impedance
state is given as
vu = Kc + V. + 2<j> + V. (2.28) H MS i rn j v '
The currents in the ON state are no longer limited
by the semi-insulator. The semi-insulator is essenti-
ally transparent to electrons and holes. The current
39
E Fm
qV
1p ins
qy
-»] n ins
l
QV24>n
O < direction of carrier flow
_ > .
E
+ 1 nj
Fn T rj
ti
E c
E E
Fp*
V
Fig. 2.6 Band diagram of the MISS device in the low impedance ON state.
40
through the device is limited by the series resistor
and the p -n junction. In fact, the I-V character-
istic in the ON state is identical to that of a for-
ward biased p-n junction, with the necessary voltage
offset due to V. and d> . 1 Ys
2.3.5 Switch Off Mode
The minimum current necessary to keep the device
in the ON state is defined as the holding current, I„.
When the current falls below I„, the hole current
through the semi-insulator, J . , is greater than b ' p ins b
J ., the hole injection current reaching the IS inter-
face. This means that the inversion charge density at
the interface decreases, thus reducing the voltage
across the semi-insulator (see Eq. 10a). The reduced
inversion charge leads to a reduced electron current
through the semi-insulator (see Eq. 22). As a result,
the voltage across the p -n junction decreases and fewer
holes are injected into the epi-layer. The gain of the
device is now less than one, and the device switches
from the low impedance ON state to the high impedance
OFF state. The device goes into deep depletion and
the voltages that appeared across R_ , V., and V. are
transferred to the surface potential.
41
2.3.6 The Non-Ideal Punch-Through MISS
It has been reported (2-1) that some devices that
would normally be expected to be ideal punch-through
devices actually switch before punch-through. These
are called non-ideal punch-through MISS devices.
The explanation of the phenomenon is as follows:
Up till now, we have assumed that the insulator electron
current, J . , which supplies the "junction recombi- n ms' v^ J
nation current (see Eq. 2.20) was not sufficient to
initiate the RFM. This required punch-through to
initiate the RFM and switch the device. Now, consider
the case where J . is high enough such that it ini- n ms & b
tiates the RFM before punch-through. A small increase
in bias will cause an increase in electron current
above that needed for J . and this will initiate the
RFM and switching will occur.
It is apparent that this process is similar to the
avalanche mode of switching, but there are important
differences. In the non-ideal punch-through mode,
switching is due to J . only, and the avalanche b n ms J'
breakdown, voltage is not reached. In fact, V is less
than VpT, which was by design less than V, ,, by the
selection of the device parameters N, and VI . r d e
It was found by Duncan, et al. (2-1), that the
switching characteristics of non-isolated structures
42
was dependent on device area and semi-insulator thick-
ness. In the following section, these effects are
examined.
2.4 TWO DIMENSIONAL EFFECTS
The punch-through theory of El-badry and Simmons
(2-2) and the more rigorous regenerative feedback
mechanism theory of Habib and Simmons (2-5) are ade-
quate to explain the I-V characteristics of large 2
area (>100xl00)jm ), i.e. essentially one-dimensional,
MISS devices. However, as the semi-insulator area
becomes smaller, the MISS characteristics cannot be
explained by either of these models. The main reason
for the area dependence is that as the semi-insulator
area dimensions become comparable to the epitaxial
layer thickness current fringing plays a dominant role
in determining device behavior (2-1). These area
effects were not included in the above mentioned
theories.
2.4.1 Experiment and Theory of Two-Dimensional
Effects
To study the effect of semi-insulator area on the
device characteristics, Duncan,et al. (2-1), fabri-
cated devices of various tunnel-oxide areas with non-
isolated p -n junctions. The I-V characteristics of
these devices is shown in Fig'. 2.7.
43
o o CD
O O
en
O O ^r CD"
o o o
o o o iff CM
t (M
E
+-» o o
-^ 1—■—I—i—i—^-r-
~l 1 r f -i ■ ?y
$
4 E en
44
it CM
> C CN O
•H 4-1 > CO •i-l
T3 X) •r4 X H O ftf
'W >
co -^ en <; 0) Zl a X o o o
•H 1—1
x; 4-1
co T3 <D C rH CO cO
O CO co CD J-l rH Cd r-l
< (1)
>—' T3) •H co X a o •H
1 4J I—) co
QJ •H • a v-l — c QJ ^
3 4-1 ,-4
4-1 a i CO CN
a) M^" x: CO 4J ^ C
O cO M-l a o > c
" 3 C M Q O
•H en M 4-1 I C/} CD cO i M 4J
•H: S4-I V4 < CO aj —
> rC 4-J^
<4-l > O a -H
O T3 4-1 O , -NN
<D CD H m gptf 14-1 • H O w u K
r-. CNJ
M •H fe
(D (D c^3 c x o =J O Qj - I c
i i c
C\J
O LO
O o
o o C\J
•r—i—■—i—i- T—i 1 r-
~T T 1 1— rJ
o o
X) CD
C •■-I 4J C O u
o O CO •rH
45
It can be seen that for a given oxidation time, the
device characteristics ranged from p-n junction charac-
teristics for the largest devices, to typical ideal
punch-through characteristics for intermediate areas,
to an absence of switching action for the devices with
the smallest areas.
Mishra (2-7) studied the effect of semi-insulator
thickness in more detail than Duncan, using both iso-
lated and non-isolated structures. The I-V character-
istics are shown in Fig. 2.8. It can be seen that as
the oxidation time increases, Lrr. In and I1T all scale ' OFF S H
to smaller values, regardless of isolation area. Note
that this is also true for non-isolated devices.
Simmons and coworkers (2-8) have developed a
theoretical model which satisfactorily explains the two-
dimensional effects in isolated structures. It is
based on the premise that the effective junction area
is larger than the semi-insulator area due to current
fringing. This becomes important for smaller devices
because the fringing area decreases at a slower rate
than the device area. Current fringing is an important
consideration because it weakens the RFM, and thus plays
an important role in determining the switching and hold-
ing voltages of punch-through MISS devices as a function
of semi-insulator area.
46 '
.
CD -t-> - a
-t-* CO - Z Q m
__^_ Ji " i z tf "
u < -
i
CD i
in i
xr
00 i
CM • i
cP O
E r° O
O CM
X o CM
CD co
CD U
c E
CD
c "a " >
5 CD X < Q O
o o in ^r
o ro
o O O CM ^
o N (D in
(Vo-OL^) ;usjjno SDIASQ
CD +-> - o
+-> CO -
*z o CO __^_ ! \ '
' t t " 1
(J
i
CM i
i
o
en i
CO
I
CD i
in i
- ^r
i
CM I
o o o m -^ co
o CM
o o o
I\
(Vg.OLX) lUSJJnO .93IA3Q
47
c •r-l
U QJ V) a
w CU
o 2 > aJ
-a
>
CU CD O
cu o
-H > QJ
U OJ jr ^ l_J cu
O ao ca
■—l cu
O
i
o
CD u
"> u
CD ai a
X a) C
-a QJ <D UJ QJ 03 en
a
cu
f-< o
14-1
en u
I en C cd o a) C u
ai »-i C QJ O
CM ^— i
o I
CD i
CO i
-<-< 2 -H
yj QJ 4-1 U CO
o
> r\ z
i CD o
CD CD a 13
C CO i ■+->
in i
o > QJ
4-> ca
i
CD CJ
4-1 en
> CLI
C) n> Ptl 1 Q <_>
CM i
QJ
00
CN
60 •H
: cj Z C = 3
■r-) en cd C
I
QJ CX 4_> ca to c c 60 -H •H 3 en O QJ ,-H
-a .-i o
en m QJ a QJ •H JZ > w QJ
"X3 JC 4-J
QJ -H
QJ • 4-J
>s ca -a I-H 3 O i-> en U) -H
C/l QJ ■H (-1 J3 0)
3
i
<o --x CM CM
> e E n 3.
if) o o <D •<r CM
CD r-i CNI
NT O X X 1 — o o o <r CM
i > rH CM
r\i CD = = i u U Q
> - CD en w i
O Q
device
device
(Vg.OLX) |U3JJnO 0DIA3Q
3 X -M o a;
C\J LO X o CD C\J u
ii •^
< CD Q
O O |\
c
*E CO
~o 'x O
o o o O o o N (D if) ^r ro m -^ en CM v—
(V a-0ix) ^usjjno G3IA3Q
(M O o
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4-J
c o
00
CM
48 60 ■H fa
REFERENCES
2-1 K. A. Duncan, P. 0. Tonner, J. G. Simmons, and L. Faraone. "Characteristics of Metal/Tunnel- Oxide/ N/P Silicon Switching Devices Part I: Effects of Device Geometry and Fabrication Pro- cesses." To be published.
2-2 J. G. Simmons and A. El-Badry. "Theory o| Switch- ing Phenomena in Metal/Semi-insulator/n-p Sili- con Devices," Solid State Electronics, 20, 955 (1977). —
2-3 S. M. Sze. Physics of Semiconductor Devices. John Wiley and Sons, Inc., New York, 1969.
2-4 H. F. Wolf. "Silicon Semiconductor Data." Per- gamon Press, 1969.
2-5 S. E-D Habib and J. G. Simmons. "Theory of Switching in pn Insulator(Tunnel)-Metal Devices. Part I: Punch-Through Mode," Solid State Elec- tronics , 22, 181 (1979) .
2-6 A. S. Grove. Physics and Technology of Semi- conductor Devices. John Wiley and Sons, New York, TWT.
2-7 J. G. Simmons, L. Faraone, U. K. Mishra, F. L. Hseuh. "Determination of the Switching Criterion for Metal/Tunnel-Oxide/N/P Silicon Switching Devices." To be published.
2-8 Umesh K. Mishra. "A Study of TwoTDimensional Effects in Metal/Tunnel Oxide/N/P Silicon Switching Devices," MS Thesis, Lehigh University, 1980.
2-9 L. Faraone, Fu-Lung Hseuh, Umesh K. Mishra, and J. G. Simmons. "Characteristics of Metal/Tunnel- Oxide/N/P Silicon Switching Devices Part III: A Simplified Model for Two Dimensional Effects in Isolated Structures." To be published.
49
CHAPTER 3
EXPERIMENTAL TECHNIQUES
In this chapter, the processes used to fabricate
the MISS devices and the measurement techniques used
are discussed in detail.
A cross section view of a typical device is shown
in Figure 3.1a and a planar view in Figure 3.1b.
The devices were fabricated on n-epitaxial mate-
rial of starting thickness 7.4 ym and resistivity 10.8
fi-cm grown on a p <100> substrate of resistivity
0.005-0.01 ft-cm.
3.1 FABRICATION PROCEDURE
3.1.1 Field Oxide Growth
The wafers were given a standard RCA prefurnace
clean (3-1). The details are listed in Appendix A.
The field oxide was thermally grown in a resistance
heated single-walled quartz tube in an ambient of
wet oxygen under the following conditions:
Furnace temperature 1100 C
Water bubbler temperature 95 C
Oxygen flow rate l£ /min.
Oxidation time 40v min.
50
amorphous silicon-
K&& SiO- Zu 12^
n- epi
p*- substrate
device area
Fig. 3.1a Cross-section of a typical device b Planar view of a typical device
51
These conditions provided an oxide of approxi-
mately 5000 R. This thickness assured that the in-
version voltage under the field oxide was greater than
the punch through voltage of the device. Duncan, et
al. (3-2), have shown that the device will switch at
the inversion voltage if it is less than the punch-
through voltage since the inversion charge will flow in
from the field oxide and cause premature switching.
After the field oxide was grown, the device areas
were defined photolithographically (see Appendix B) and
the oxide was removed from these areas using buffered
HF (see Fig. 3.2).
- ft 9 The device geometries were 4x10 cm (20 ym x
20 ym), 9x10 cm (30 ym x 30 ym), 16x10 cm (40 ym x
40 ym), 36x10 cm (60 ym x 60 ym), 64x10 cm (80 ym x
80 ym), 100xl0"6cm2 (100 ym x lOOym), and 256xl0"6cm2
(160 ym x 160 ym).
Following the etching of the oxide, the wafers
were rinsed in DI water and boiled in acetone to remove
the photoresist. The wafers were then given a pre-
furnace clean (Appendix A) in preparation for the
amorphous silicon deposition.
52
SiO- Si02
n- epi
p*- substrate
Fig. 3.2 Device fabrication just after field-oxide window etch.
53
3.1.2 Amorphous Silicon Deposition
The vacuum sputter system used for the amorphous
silicon deposition consisted of a water cooled sub-
strate holder, a silicon target (also water cooled) and
a movable shutter. The circular silicon target was
five inches in diameter. The distance between the
target and substrate holder was three and a half inches.
The argon used for sputtering was at least 99.999%
pure and contained less than 3 ppm of moisture. Power
supplies were connected to the target so that both DC
and RF sputtering were available. The vacuum system
was a standard oil diffusion pump and mechanical pump
combination. A diagram of the system is shown in
Fig. 3.3.
A wafer was placed on a glass slide and then
placed on the water cooled substrate holder. The cham- - f>
ber was pumped down to a vacuum better than 5x10 mm Hg
for the amorphous silicon deposition.
Before the actual deposition, the silicon target
was DC sputtered with the shutter shielding the wafers,
at 2kV and lOy ambient of argon for two minutes in order
to clean the target.
The DC power supply was shut off and the shutter
opened. The amorphous silicon was then deposited using
RF sputtering, with an argon ambient of lOy, at 200
watts, one set of devices for, one, minute .and another
54
To RF or DC power supply
r target cooling water
^substrate holder cooling water
shutter -5'
wafer- x
Ar input
target •^holder
Si target
T 1"
I1 substrate holder
—1 1 I To vacuum
pump
Fig. 3.3 Diagram of vacuum sputter system
55
for three minutes. The deposition rate was somewhat
larger than lA/sec, so the thickness was roughly 100A
and 300A, respectively. See Fig. 3.4 for a diagram of
the device after amorphous silicon deposition.
When the vacuum sputter system was vented to at-
mosphere, a thin layer of condensation of moisture was
suspected to form on the wafers, since they were sit-
ting on the water cooled substrate holder. This caused
an adherence problem for the aluminum used for contacts .
Several procedures were tried and boiling in acetone
followed by a twenty minute bake at 200 C was found to
be adequate. Higher temperatures were avoided as it
changed the amorphous silicon properties.
3.1.3 Metallization and Electrode Definition
After baking, the wafers were loaded into a vacuum
deposition system for aluminum deposition of the cathode
electrode of the MISS device. The aluminum used for
the filament evaporation was of 99.999% purity. Before
loading the filament, the aluminum was cleaned using
the process described in Appendix C. The evaporation
- f-> was done at a pressure of 'vlO torr and resulted in an
Al thickness of %5000A\
Photoresist was then immediately applied to the wafer
in the same way as in 3.1.1. The aluminum was etched
using PAN etch at 45 C. The composition of the etch was
56
amorphous silicon
SlO; SiO-
ruepi
p*- substrate-
Fig. 3.4 Device fabrication after amorphous silicon deposition.
57
volume,
Phosphoric Acid 80%
Acetic Acid 57o
Nitric Acid 5%
DI Water 10%
After etching, the wafers were rinsed in DI water, then
boiled in acetone to remove the photoresist. Aluminum
was then evaporated onto the back of the wafer, in the
same manner as described above, in order to provide a
good ohmic contact. The complete fabrication procedure
is outlined as a flowchart in Fig. 3.5.
As a result of the high temperature processing,
it was estimated that 0.22 ym of silicon was consumed
in the oxidation and the p -n junction up-diffused
1.48 ym, so the final epitaxial layer thickness was
about 5.7 ym.
3.2 MEASUREMENT TECHNIQUE
3.2.1 Slow Voltage Ramp
The DC characteristics of the device were measured
using a very slow voltage ramp (0.0005 V/sec), provided
by an HP 3310B function generator. A load resistor of
80 kft was placed in series to limit the current in the
ON state. A diagram of the measurement setup is shown
in Fig. 3.6.
58
n epi on p+ substrate
I Standard RCA pre-furnace clean
i Field Oxide
1100°C wet O2(4Omin0=5OOOA I
Standard RCA pre-furnace clean
I Amorphous silicon sputter(1-3min)
i Boil in acetone Bake at 200°C (20mirr)
I Al depsn.(10"6torr) define final pattern
T
Fig. 3.5 Flowchart of fabrication procedure
59
i_ <j < "O
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The voltage across the device was measured using
a Keithley 616 digital electrometer in the volt mode,
with an input impedance of 10 ft, in order to avoid
shunting current through the meter caused by the high
device impedance (as high as 10 ft) in the OFF state,
which would lead to erroneous results.
The current through the device was measured also
with a Keithley 616 digital electrometer in the current
mode because of the very small currents (as low as _9
10 A). A graphical plot of the I-V characteristics
was obtained by feeding the analog outputs from the
electrometers into the input terminals of an HP7044A
X-Y recorder.
61
References
3-1 W.Kern and D. A. Poutinen, RCA Rev. 31, 187 (1970).
3-2 K. A. Duncan, P. D. Tonner, J. G. Simmons, and L. Faraone. "Characteristics of Metal/Tunnel Oxide/N/p Silicon Switching Devices Part I: Effects of Device Geometry and Fabrication Processes," to be published.
62
CHAPTER 4
RESULTS AND DISCUSSION OF THE VIRGIN OFF STATE
In this chapter the experimental DC two-terminal
I-V characteristics of the MISS prior to the first
switching event are presented. A virgin state similar
to that reported by Kroger and Wegener (4-1) was ob-
served. The variation of the OFF state currents of the
virgin state with device area and amorphous silicon
thickness will be presented and discussed. In the fol-
lowing chapter, the experimental results after device
stabilization or "forming" will be presented and the
effect of amorphous silicon properties on the device
characteristics will be discussed.
4.1 Typical Virgin OFF States
The I-V curves of typical OFF state characteris-
tics up to punch-through are shown in Fig. 4.1. It can
be seen that for all the devices, once they are biased
into depletion and the device current is interface
controlled, rather than junction limited, the current
becomes almost constant. This is the region in which
any additional applied voltage is dropped across the
deep-depletion region.
63
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64
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For the smaller devices, it can be seen that 1^,-,,-. ' OFF
has almost zero slope even though the depletion width,
X ,, goes from zero to punch-through. This is strong
evidence that generation currents are negligible. For
the larger devices, the slope is thus not due to gene-
ration. In'these devices, the bias across the junction
is higher due to the higher current density through the
junction because current fringing effects are smaller
(4-2). The increase in current is due to a decrease
in the width of the neutral region. The hole injection
current equation given in Chapter 2 (Eq. 2.17b) would
be more accurate if the short base approximation were
used. The hole injection current for a short base
diode is given as (4-3)
q D n2 qV./kT j = 2 i. fe
J - 1) 4 1 • PJ Nd Wn
As W decreases because of the increasing depletion n fa r
width (W = W X,) the device current will increase. v n e d'
For small area devices, I . - 0 and almost all of the PJ
current is junction recombination current and thus is
not affected by changes in W and is therefore bias
independent.
The off-state currents varied widely with position
across the wafer. A complete set of plots for all the
positions are included in Appendix D. These variations
66
were due to a non-constant amorphous silicon layer
thickness. This was readily observed during fabrica-
tion as gradual color changes across the wafer after
amorphous silicon deposition. This effect was mini-
mized, although not eliminated, by placing the wafer
under the center of the silicon target during the
sputtering operation (see Sec. 3.1.2).
A plot of the OFF-state current vs. area of a
typical device is shown in Fig. 4.2. It can be seen
as the device area increases, the slope of the curve
decreases. The current densities of the device in Fig.
4.2 are listed in Table 4.1. This means that as the
area decreases, the current density increases. This is
an effect due to current fringing for the smaller de-
vices .
From the preliminary results, it appears that the
samples with longer deposition time have a larger con-
ductivity. This will be considered in the next chapter
4.2 The Punch-Through Point
The punch-through voltage is defined here as the
p.oint where a sudden increase in the current begins.
From Fig. 4.1 it can be seen that there is a sharp
increase in current at %12.8V for X4 and ^13.8V for X3.
A histogram of punch-through voltages for all the de-
vices is shown in Fig. 4.3. It can be s-een that all
67
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Table 4.1 Current Density vs. Device Area
Device Set X4 Position 1,2
3 2 -5 2 Area (10 pm ) Density (10 A/cm )
0.4 12.5
0.9 10.6
1.6 9.4
3.6 8.6
6.4 8.0
10.0 6.7
Device Set X3 Position 2,2
Area (103ym2) Density (10_5A/cm2)
0.4 13.8
0.9 12.2
1.6 11.6
3.6 8.2
6.4 10.5
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the devices reach punch-through at nearly the same
voltage and is largely independent of device area, 2
except for the smallest devices (£30 x 30 p ) be-
cause of the very small currents involved.
If the devices were non-ideal punch-through de-
vices, that is, devices that switch before punch-
through, the OFF state currents would have large slopes,
which is indication of increased injection (4-2).
These devices exhibited very flat OFF states and show
little injection before punch-through. This is evi-
dence of the ideal punch-through mode.
4.3 From PT Through Switching
The OFF-state I-V curves of the virgin switching
event are shown in Fig. 4.4. It should be noted that
the current scale is now lyA/div, whereas in Fig. 4.1
the current scale is InA/div. This makes an important
difference in that the punch-through voltage information
is lost because of the very small currents at PT.
It can be seen from the figure that the switching
voltages are greater than VpT by two to seven volts,
depending on the device. The switching voltage for 2
large area devices (>60x60|-im ) is not strongly dependent 2
on device area, but for smaller devices (<60x60ym ) V^
increases with decreasing area (see Fig. 4.5).
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76
From punch-through to switching, the excess
voltage is added on to the voltage present across the
semi-insulator at PT.(This is discussed in more detail
in the following chapter.) For the larger devices the
one-dimensional model is sufficient and the effects of
current fringing can be neglected. This is evident
from Fig. 4.5. For the large area devices V„ is almost
constant. However, for the smaller devices, fringing
effects lead to a larger voltage across the semi-
insulator. A larger proportion of I . recombines in
the neutral epi-layer and reduces the current reaching
the insulator-semiconductor interface. That is, the
assumption that J is negligible in Eq. 2.13b is no
longer valid for small devices and Eq. 2.13d should
be written
•J . = J . = J . - J . 4.2 p ins pi pj rn
Thus it can be seen that in order to get p (0) to the
level required for switching, a larger V. is required
to supply the additional recombination current occur-
ring in the neutral region.
The switching current is determined solely by the
characteristics of the amorphous silicon (4-4). The
switching point for a particular semi-insulator thick-
ness is characterized by an essentially constant value
77 - - '
of minority carrier current density reaching the sili-
con semi-insulator interface. It can be seen that
devices X3 (3 min) have lower switching currents than
devices X4 (1 min), in agreement with the higher con-
ductivity of the X3 samples and Duncan (4-2).
It is experimentally observed that the switching
current of these devices does not appear to depend on
area. This randomness of I<-, suggests that the amorphous
silicon is very non-uniform, or, more likely, that
switching occurs at some "weak point" in the amorphous
silicon and thus does not depend on device area.
Also, the OFF state currents are approximately
proportional to area, but the switching currents are
not. This suggests that for low current levels, amor-
phous silicon conducts uniformly,- but at higher currents,
including switching, conduction is occurring at a
"weak point." This is confirmed by data in the next
chapter.
78
REFERENCES
4-1 H. Kroger and H. A. R. Wegener. "Steady-State Characteristics of Two Terminal Inversion-Con- trolled Switches," Solid State Electronics, 21, 643 (1978).
4-2 K. A. Duncan, P. D. Tonner, J. G. Simmons, and L. Faraone. "Characteristics of Metal/Tunnel- Oxide/N/P Silicon Switching Devices Part I: Effects of Device Geometry and Fabrication Pro- cesses." To be published.
4-3 R. S. Muller and T. I. Kamins. Device Electronics for Integrated Circuits. John Wiley and Sons, New York, 19 77.
4-4 J. G. Simmons, L. Faraone, U. K. Mishra, and F. Hseuh. "Determination of the Switching Criterion for Metal/Tunnel-Oxide/N/P Silicon Switching Devices." To be published.
79
CHAPTER 5
RESULTS AND DISCUSSION AFTER VIRGIN SWITCHING
5.1 EXPERIMENTAL RESULTS AND PRELIMINARY DISCUSSION
5.1.1 Experimental Results
After the initial switching event, the device was
connected to a curve tracer and the maximum applied
voltage was adjusted so that it was just large enough
to keep the.device switching into the ON state. The
characteristic changed as a function of time and after
several minutes the trace on the curve-tracer became
stable. The device was taken off the curve-tracer after
about five minutes and the I-V measurements were taken
again in- the manner described in Chapter 3. The results
are plotted in Fig. 5.1.
The most notable difference between the virgin
state and after stabilization is the very large increase
in conductivity of the amorphous silicon. Whereas pre-
vious to switching the current before PT were measured
in nanoamps, after stabilization the currents are in
microamps, an increase of three orders of magnitude.
There are other changes as well. The switching
voltage, V , is still greater than VpT, but by not as
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large a margin. After stabilization, V is greater
than Vp„ in a range from 0-3 V, as compared to 3-7 V
previously.
The switching currents, I , are smaller by roughly
a factor of three and are much more uniform after stabi-
lization. This suggests the current path has become
more reproducible and also more stable.
The low impedance ON state does not show the vir-
gin state effects that the OFF state characteristics
exhibit. This means that whatever is special about the
virgin state is lost during the first switching event.
Typical I-V curves are shown in Fig. 5.2. Although it
is difficult to make definite conclusions, it appears
that the holding voltage, V„ , tends to increase with
decreasing area in agreement with- Duncan (5-1), due to
increased current fringing. Also the holding current
tends to increase with increasing deposition time, in
agreement with the findings that conductivity increased
with deposition time (see Sec. 4.1 and Sec. 5.2.2).
5.1.2 Discussion
To begin the discussion of the experimental re-
sults , it will be helpful to recall that the voltage
across the device can be expressed as
V=$MC+V.+(j)+V. 5.1 MS l ^s j
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85
or v. = V - <DMO - $ - V. 5.1a 1 MS Ys j
and to study the various components of the device
voltage at several key points. Of particular interest
will be the voltage across the semi-insulator, V. .
The points of interest will be the virgin state
punch-through voltage, the virgin switching point,
V after stabilization, and the holding voltage V„.
In this discussion, the experimental voltages used in
the sample calculations are taken from device set X3,
position (2,2), 100 x 100 ym2.
For the virgin state punch-through voltage, the
currents are quite small (see Fig. 4.1). The junction
voltage will be in the range of approximately -0.2 V.
At this junction potential, <J>p_ is calculated using
eqns. 2.4-2.7 as -6.7 V. <J>MC, is a constant and will be
taken as" -0.3 V for Aluminum on 'n' type silicon (5-2).
From Fig. 4.1, it can be seen that VpT is about -13.5 V
Substituting in the values given into Eqn. 5.1a, we
get
V. = -13.5 + 0.3 + 6.7 + 0.2 =-6.3V
at punch-through.
Repeating the procedure for virgin switching, we get
V. = -17.0 + 0.3 + 7.9 + 0.5 = -8.3 V
at virgin switching.
86
Also, for V after stabilization, s
Vi = -15.0 + 0.3 + 7.0 + 0.3 = -7.4 V
at V after stabilization, s
And at the holding voltage, V„, using eqns. 2.27 and
2.28
V. = -4.0 + 0.3 + 0.5 + 0.7 = -2.5 V l
at the holding voltage, V„.
Calculations for several other devices are listed in
Table 5.1.
For the virgin state punch-through voltage, it
can be seen that the voltage across the amorphous silicon
is not small, in contrast to those found in devices
using tunnel-oxides for the semi-insulator (5-1) . At
the virgin switching point, $„„ has increased somewhat
due to the shrinking of the junction depletion region
under forward bias. If a smaller V. is chosen at punch-
through, (j)pT will decrease and thus V. will be in-
creased. In any case, V. at switching has increased
over its value of punch-through, as would be expected,
in order to carry the larger currents necessary to
switch the device.
In the case of the switching point after stabili-
zation, as expected, V. is smaller than V. at virgin
switching as a result of the large conductivity increase
of the amorphous silicon.
87
Table 5.1 V. at Points of Interest for Several Devices
-V.(V)
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88
At the holding point, and the ON state in general,
the surface is strongly inverted. For tunnel-oxide
devices, when the device switches, the voltage across
the depletion region is transferred to the load resistor
and V. (see Sec. 2.3.3). If the conduction mechanism
of the semi-insulator does not change upon switching,
the voltage across the semi-insulator in the ON state
should be greater than V. at switching in order to carry
the much larger currents. It can be seen that for
amorphous silicon this is not the case. Indeed, V.
decreases upon switching for these devices.
Simmons, et al., (5-3) have shown that the switch-
ing characteristics are controlled by the properties
of the semi-insulating material. In order to under-
stand this unexnected decrease in-V. , it will be ne-
cessary to examine the electrical properties of amor-
phous silicon. This is done in the following section.
5.2 PROPERTIES OF AMORPHOUS SILICON
5.2.1 Amorphous Silicon Switches
In the search for a bistable switching device,
other devices have shown the bistable latching character-
istic and negative resistance region that the MISS
device exhibits (5-4). These are usually bulk effect
devices using chalcogenide glasses or amorphous semi-
89
conductors. Amorphous silicon switches were first
reported by Feldman (5-5) in a parallel study of amor-
phous boron films. A typical I-V characteristic of an
amorphous silicon switch is shown in Fig. 5.3. In
later work, Feldman and co-workers observed filament
formation (5-6) during switching using liquid crystals
warmed by joule heating due to the current filament and
proposed (5-7) a simple electrothermal model of switch-
ing. Dey (5-8) has developed a more extensive electro-
thermal model. Finally, Feldman and Charles (5-9) did
extensive studies of switching times using samples with
various fabrication parameters and found the switching
times were dependent on the RC constant of the device.
5.2.1.1 The electrothermal model of switching in
amorphous silicon
The qualitative theory of Feldman and Charles
(5-7) is presented briefly here in order to gain in-
sight into the switching mechanism.
For low bias the current flows uniformly through
the volume of the material first by ohmic conduction
and the later by Schottky, Frenkel-Poole or space
charge effects. This current causes the sample to heat
up and because of the geometry of the sample, the center
of the sample becomes warmer than the edges or the metal
90
■■■■■*■■■■ ■■■■■«■■■■ iiriiniiB ■ II1I1»0M ■miaiMatii ■RIIIIBflll BMBLIIMUHBJ ■1I1IIBIII
Fig. 1
Switching in Amorphous Films
Electrodes: Titanium, -4 2
Load: 1 K, Area: 10 cm
Scale: Vertical: Ima/div.
Horiz-: lv/div.
Si (5400A) ■
Fig. 5.3 Typical I-V characteristics of an amorphous silicon films [After Feldman (5-5) ]
91
.O
Deposition rate (Ay/sec) >
FKJ. I. Resistivity vs deposition rale for amorphous Si films O: as-deposile<l,
A-. iflrr switching occurred, •: adapted from Walley (I96S).5
Fig. 5.4 Resistivity vs. deposition rate [After Dey and Fong (5-10)]
92
contacts. This hotter region has a much higher con-
ductivity due to its semiconducting nature. The fields
become larger and are concentrated in the more conduct-
ive region. A current filament is then formed and the
voltage across the material is reduced. The filament
is stable until the voltage is lowered below the hold-
ing voltage.
The important point here is that amorphous sili-
con can act as a current controlled switch and this must
be taken into account when studying the MISS device.
The next section deals with the effects of processing
on the amorphous silicon parameters.
5.2.2 Processing Effects
5.2.2.1 Deposition rate effects
Dey and Fong (5-10) studied the effect of depo-
sition rate on the resistivity of amorphous silicon
films. Their results are shown in Fig. 5.4. The in-
crease in resistivity for the lower deposition rates is
due primarily to oxygen inclusions. If the source to
substrate distance is increased, further oxidation can
occur in transit.
The resistivity of the samples prepared in this
work are on the order of 10 ficm. The high
resistivity of these samples is thus a result of
93 ,
the very low deposition rate used, %1 A/sec (see Sec.
3.1.2), resulting in a very high number of oxygen in-
clusions .
When the samples were prepared for this study,
the vacuum sputter system pressure was close to atmos-
pheric pressure for at least several days before the
amorphous silicon was deposited. Device set X4 was
sputtered onto first for one minute and then later that
day device set X3 was sputtered onto for three minutes.
However, device set X4 has a lower conductivity than
device set X3. This was probably due to oxygen out-
gassing at a higher rate during the first deposition
resulting in the lower conductivity of device set X4
even though the deposition time was shorter.
5.2.2.2 Origin of the virgin state
Also included in Fig. 5.4 in the work by Dey and
Fong (5-10) is the resistivity of the amorphous silicon
switches after "forming" or stabilization. Their amor-
phous silicon switches showed a virgin state. For the
lower deposition times (<12 A/sec) the amorphous sili-
con had a lower resistivity after stabilization. This
change in conductivity was attributed to the annealing
or restructuring effect of the filamentary current.
For the MISS devices studied here, this annealing
or restructuring of the amorphous silicon due to the
94
current filament would be a plausible explanation of
the virgin state of the devices.
Also, for these devices, if the device was
continually measured for several cycles using the slow
voltage ramp technique of Chapter 3, the device would
stay in the high current ON state for a much longer
time than if the curve-tracer were used to observe the
characteristics. This measurement method resulted in
continuing degradation of the OFF state characteristics.
This is because with the increased ON time, a higher
average localized temperatures occurred in the amorphous
silicon, furthering the restructuring of the amorphous
silicon.
5.3 CONCLUSIONS
It has been shown that non-isolated MISS devices
using amorphous silicon as the semi-insulator exhibit
characteristics in agreement with those of Duncan (5-1) .
In particular, for smaller devices, current fringing be-
comes a larger factor and must be considered in the
modelling of the device.
The effects of amorphous silicon on the MISS char-
acteristics have been studied. It has been found that
devices fabricated using amorphous silicon behave as a
compound switch, due to the fact that amorphous silicon
95 - -
acts as a current controlled switch in combination
with the basic MISS characteristic.
The virgin state and the large increase in con-
ductivity after stabilization have been proposed to be
due to forming of a high conductivity path through the
amorphous silicon after the initial switching event and
during the time the device is in the low impedance ON
state.
96
REFERENCES
5-1 K. A. Duncan, P. D. Tonner, J. G. Simmons, and L. Faraone. "Characteristics of Metal/Tunnel- Oxide/N/P Silicon Switching Devices: Part I: Effects of Device Geometry and Fabrication Processes." To be published,
5-2 S. M. Sze. Physics of Semiconductor Devices. John Wiley and Sons~ TncT, New York 1969.
5-3 J. G. Simmons, L. Faraone, U. K. Mishra, F. L. Hseuh. "Determination of the Switching Criterion for Metal/Tunnel-Oxide/N/P Silicon Switching Devices." To be published.
5-4 See, for example, Proc. 4th Int. Conf. on Amorphous and Liquid Semiconductors, published in J. Non- cryst. Sol. , 8-10 (1972) .
5-5 C. Feldman. "Amorphous Boron Films," Mt. Res. Bull. 3, 95 (1968).
5-6 C. Feldman and K. Moorjani. "Observation of filament formation in amorphous films during switching," Thin Solid Films 5, Rl (1970).
5-7 C. Feldman and H. K. Charles Jr. "Electrothermal Model of Switching in Amorphous Boron and Silicon Thin Films," Solid State Communications 15, 551 (1974).
5-8 S. K. Dey. "Electrothermal model of switching in amorphous silicon films," J. Vac. Sci. Tech- nol., 17(1) Jan./Feb. 1980.
5-9 H. K. Charles, Jr. and C. Feldman. "Switching Times in Amorphous Boron, Boron Plus Carbon, and Silicon Thin Films," Journal of Applied Physics 46(2), 819 (1975).
5-10 S. K. Dey and W. T. J. Fong. "Conduction pro- cesses and threshold switching in amorphous Si films," J. Vac. Sci. Technol. 16(2), Mar./Apr. 1979.
97
APPENDIX A
PRE-FURNACE CLEANING PROCEDURE
Note: (i) Throughout all processing, silicon wafers were
supported in Teflon wafer carriers.
(ii) All processes that involve boiling on the hot plate
were carried out in pyrex or quartz containers,
(iii) All processes that involve HF acid were carried out
in Teflon or polypropylene containers,
(iv) DI water used was > 10 Megohm-cm resistivity, and for
final rinses > 14 Megohm-era.
(v) All chemicals used (except for initial organic
solvent boils) were "Electronic" grade,
(vi) All DI water rinses,were repeated 6 times, and for
final rinses at least 8 times.
(vii) Before trichloroethylene boils, care was taken to
ensure that silicon wafers, wafer carrier and con-
tainer were dry.
I. Organic Solvent Boils (hot plate set at 500)
]_. boil in trichloroethylene (5-10 mins . )
2. boil in acetone (5-10 mins.)
3. Boil in methanol (5-10 mins.)
II. HF Etch
1. Dip in 10% HF to remove any oxide. (Note: 10 sees, is
usually sufficient; however, care must; be taken not to
98
over-etch when oxide patterns are present on the wafer.
The etching process can be monitored from the back of
the wafers and is complete when the surface becomes
hydrophobic).
(2) Rinse in DI (X6)
III. Organic Clean (hot plate set at 500)
(1) Boil in 4:1:1 solution of Di:NH.OH:H„0„ (10-15 mins). 4 11
(2) Rinse in DI (X6).
IV. Ionic Clean (hot plate set at 500)
(1) Boil in 4:1:1 solution of DI:HC1:H 0 (10-15 mins.)
(2) Rinse in DI (X6).
V. HF Etch
(1) Dip in 10% HF for 10 sees, to remove any oxide grown
during organic and ionic cleans. (Note: See previous
comments on HF etch.)
(2) Rinse in DI (X8).
(3) Blow dry in N gas as soon as possible after the final
DI rinse.
99
APPENDIX B
SHIPLEY PHOTORESIST (PR) PROCEDURE
Note: (i) Shipley PR was applied to the wafers as soon as
possible after oxidation or metallization,
(ii) For etching of oxides, buffered HF etch was kept
in polypropylene or Teflon container and wafers
were supported in Teflon carriers.
I. PR Application
(1) Place wafer front-face-up on PR spinner, switch on vacuum
and apply several drops of Shipley PR (AZ 1350J) evenly
over the whole wafer.
(2) Spin at 4000 rpm for 20 sees.
(3) Place front-face-up onto filter paper and pre-bake at
80-85°C for 20 mins.
II. PR Exposure and Development
(1) Align wafer under appropriate mask and expose under UV
lamp for 30 sees. (Note: UV lamp should be allowed to
warm up for at least 10 mins before using.)
(2) Place wafers in Teflon wafer carrier and develop for 45
sees, in Shipley developer (1:5 mixture of AZ 351 and DI
water) under conditions of continual stirring.
(3) Rinse in DI (X4).
(4) Rinse each wafer individually under DI water tap and blow .
dry in N„ gas.
100
(5) Place wafers front-face-up onto filter paper and post-bake
at 100-105°C for 20 rains.
101
APPENDIX C
CLEANING PROCEDURE FOR ALUMINIUM
The Aluminium to be used for evaporation was cut into sticks
of length (^3 cms) and cleaned by the following procedure before
being loaded into the vacuum system.
I. ORGANIC SOLVENT BOILS
(i) Boil in trichloroethylene (5-10 mins).
(ii) Boil in acetone (5-10 mins).
(iii) Boil in methanol (5-10 mins).
(iv) Rinse in DI water (X10).
II. IONIC CLEAN
Note: This cleaning procedure is used to remove native
A1„0„ from the surface and also etch a very thin layer of
aluminium from the surface so that a clean fresh aluminium
surface is obtained.
(i) Place the aluminium sticks in a very dilute solution of
HC1:H 0 :DI water for about 2 minutes,
(ii) Rinse in DI water (X10).
(iii) Blow dry in N .
102
APPENDIX D
SUPPLEMENTARY EXPERIMENTAL DATA
a. Virgin OFF-states through punch-through
b. OFF-state current vs. device area
103
8 Device set X3
7 Position 2,2
/ 100^100
6 • J60 x 60
_5 <
|
to ^4 / / /60x 60
Cu
rre
nt
// ^-^-^^ 1AO x 40
// >
_^30x30
i—j
1 / 20x?0
0 sd^ 1 1 1 1 1 1 1 . 1 1- 0 -6 -8 -10 -12 -14 • -16 -18
Device Voltage (V)
Device set X3
Position 1 2
-2
Ox 60
00x100
-6 -8 -10 -12 -14 Device Voltage (V)
104
-16 -18
Device^set X3
Position 2 1
0 -2 ■ 6 -8 -10 -12 -14 Device Voltage (V)
16
8 Device set X3 Position 1 1
'o
c a;. t 3 u
105 Device Voltage (V)
8 Device set X3 100 x 100
7 ' Position'2,3 ____--//eo x eo
6 ^^^^^^^^
_5 \ /60 x60
'O \\ —-~—~~"
c
h 3 13 u ,40x 40
u 2 / / . ■ 30x 30
> Q
^^_____^/ /;ox 20
1 //f"============== 0 //^y i t i t i 1 1 1 1.
0 -6 -8 -10 -12 -14 Device Voltage (V)
•16 -18
100x100
-4 -6 -8 -10 -12 -14 -^QgDevice Voltage (V)
8 Device set X3
Posilfon 4 1
100 *100
•4 -6 -8 -10 -12 -14 Device Voltage (V)
16 -18
8
7[
Device set X3
Position 1 2 0x100
x BO
16 -18
107 Device Voltage (V)
'o
c
b 3 3 U
y 2 >
Q 1
0
Device set X4
Position 1/2 100*100
80x80
'60x60
20* 20
0 -4 -6 -8 -10 -12 -14 • -16 -18 Device Voltage (V.)
Device set X4
Position 3.3
OO x 10O
108
6 -8 -10 -12 -14 -16 Device Voltage (V)
18
8 Device set X4
7 Position 1,4
6 ■
/60*60
_5 -
'o ^4 _
Curr
ent
U)
y 40 x40
y 2 / /30x 30
> J
1
0
) ?0 x 20
—///—i 1. . i i i i i i i
o ■4 -6 -8 -10 -12 -14 -16 -18 Device Voltage (V)
8
7
6
Device set X4
Position 2 3
100x100
80 x 80
■4 -6 -8 -10 -12 -14 -16 -^□Device Voltage (V)
18
'o AY
c
t 3 (J
u 2 > O
0
. Device set X4 Position 4,2
- /l0O x
■ f yeox ac
■ r /60x60
. |f IAOXAO
/;30x 30
//^ y/ ///^ ^20x20
i—y*^\ 1 1 1 1 , , ■ , ,
0 -6 -8 -10 -12 -14 -16 Device Voltage (V)
18
0
8 • Device set X4
7 Position 1,3 /80x80
6 /
_5
,< , O r-. 4 L———— /60 x 60
Cu
rre
nt
u 2
,
■
JAOx40
> a; Q
/" /30x30
1 ■ ''^ / 1 / • /20 x 20
0 i r. , . . 1 1 1 1
-6 -8 -10 -12 -14 Device Voltage (V)
110
■16 -18
8 • Device set X4
7 - Position 1,1
.
6 noo *'oo
_5 / »< / 80 xBO
'O I /■
___-^ i^4 -4-»
c a; 1
t 3
If /60 x60
u
- ,40x40
> / / <L>
■ r _V 30x30
Q ___—^ 1 /
If J 20x20
0 i t II i i
O -2 ■6 -8 -10 -12 -14 Device Voltage (V)
•16 -18
8 Device set X4
Position 2 1
x 100
111
6 -8 -10 -12 -14 Device Voltcge (V)
-16 -18
8|
7
6
Device set X4 Position'3.1
100x 100
-6 -8 -10 -12 -14 Device Voltage (V)
16 -18
8 Device set X4 Position 3,2
6
100 x100
-6 -8 -10 -12 -14 Device Voltage (V)
112
16 -18
'o
c <u
t 3 z> U
> O
O
Device set X3
Position 3.2 80 « 80
60x 60
40 x 40
100 x100( SnA/div)
30 x 30
?0* 20
•6 -8 -10 -12 -14 -16 -18 Device Voltage (V)
8 Device set X3 Position 3 3
-2 4 -6 -8 -10 -12 -14 Device Voltage (V)
80x80
60x60
16 -18
Device Area (10 pm )
2 3 4 5 6 2 7 , , .Device Area (103pm )
8 9 10
Device Area (10 pm ) Fig. 4.2b OFF state currents vs. device area - 3 min.
2.2
0 1 2 34 5 6 78910 Device Area (lO^pm2)
Fig. 4.2a OFF-state currents vs. device area - 1 min.
115
Device Area (10Jpm'!)
0 1 2 3 4 5 6 7 Device Area (103|jm2)
8 9 10
116
0 1 2 3 4 5 6 7 Device Area (103|jm2)
8 10
8 - •
7 Device set X3
*■—*
< ^^~~~^'1-2
h6 ^ •
t?5 (_ L o A U
+ y"^ ^^~^^
—-—'—*1,3
0)
a;
°2 / *>/
1 ■ //
0 0 1
Device Area (103(jm2) 7 8 10
117
VITA
Mark Turner was born in Newton, Massachusetts,
on December 31, 1956, to John and Beverly Turner. He
obtained a Bachelor of Science degree in Materials
Engineering from Rensselaer Polytechnic Institute,
Troy, New York, in May 1979. He has been registered
in the MS program offered by the Department of
Electrical Engineering, Lehigh University, Bethlehem,
Pennsylvania, since September 1979.
118
