IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 46, NO. 12, DECEMBER 1999 2333

A Physics-Based Dynamic ThermalImpedance Model for Vertical

Bipolar Transistors on SOI SubstratesJonathan S. Brodsky, Robert M. Fox, and David T. Zweidinger

Abstract—A physics-based compact model for the thermalimpedance of vertical bipolar transistors, fabricated with fulldielectric isolation, is presented. The model compares favorably toboth three-dimensional (3-D) ANSYS transient simulations andmeasurements. Using the software package Thermal ImpedancePre-Processor (TIPP), a multiple-pole circuit can be fitted to thethermal impedance model. The thermal equivalent circuit is usedin conjunction with a modified version of SPICE to give efficientelectrothermal simulations in the dc and transient regimes.

Index Terms—BJT, dielectric isolation, self-heating, thermalresistance.

I. INTRODUCTION

BIPOLAR junction transistors fabricated using full dielec-tric isolation (DIBJT’s) offer many advantages, such as

reduced parasitic capacitances and leakage currents, increasedpacking density and improved radiation hardness, over thosefabricated with junction isolation in bulk wafer technologies[1]–[3]. However, a major disadvantage of full dielectricisolation is an increase in self-heating. The oxide used in thetrench and buried isolation has a low thermal conductivity(approximately two orders of magnitude lower than that ofbulk silicon) and impedes the flow of heat away from thedevice, resulting in higher operating temperatures. The thermalresistance of a DIBJT can be three times larger than that ofits bulk counterpart [3].

As shown in [4], self-heating can play an important role inbipolar device/circuit operation. Methods for characterizing thesteady-state thermal responses of DIBJT’s have been devel-oped using both measurement-based extraction and complexnumerical techniques such as finite-element solutions [3], [5],[6]. Neither approach is practical for use in predictive circuitsimulation: temperature measurements are complicated and arenot predictive; finite-element solutions are predictive but canrequire large amounts of computing time. A compact physicalmodel for the thermal resistance of DIBJT’s was presented in[6]. However, this model is only valid for steady-state heatconduction and is limited by simplifying assumptions.

Manuscript received September 24, 1998; revised June 2, 1999. This workwas supported by the Semiconductor Research Corporation under Contract91-SP-087. The review of this paper was arranged by Editor T. Nakamura.

J. S. Brodsky and D. T. Zweidinger are with Texas Instruments, MixedSignal and Logic Products, Semiconductor Group, Dallas, TX 75266-0199USA.

R. M. Fox is with the Department of Electrical and Computer Engineering,University of Florida, Gainesville, FL 32611-2044 USA.

Publisher Item Identifier S 0018-9383(99)09022-X.

With the addition of dynamic thermal simulation capabilitiesin bipolar models such as VBIC [7], a predictive thermalimpedance model can be quite valuable. There has not beenan effort so far to derive a compact physical model for thedynamic thermal effects in DIBJT’s. A physical model isdesirable because it allows prediction of thermal behavior fromthe device structure and material properties alone. However,the requirements of accurate physical modeling tend to conflictwith the necessity of simplicity and efficiency in circuitsimulation. This paper details the derivation of a physics-based model for the dynamic thermal impedance of DIBJT’soperating in the forward active region. The model is physicalenough to correctly predict technology-scaling trends, but iscompact enough for use in efficient electrothermal circuitsimulation. The derivation of the thermal model is discussed inSection II; the model is compared to three-dimensional (3-D)finite-element simulations and measurements for verification,and a simple model for the effects of the emitter interconnectis derived to account for discrepancies between the thermalmodel and measurements. In Section III, the usefulness ofthe thermal impedance model is discussed. The dynamicthermal model can be used to generate a multiple-pole thermalequivalent circuit using the Thermal Impedance Pre-Processor(TIPP) software package [8], which is briefly discussed inSection IV. The resulting thermal equivalent circuit can beused in a circuit simulator to provide dc, ac and transientelectrothermal simulations. This capability has been writtendirectly into some device models, including Gummel–Poonand VBIC, such as in the modified version of SPICE presentedin [9]. Self-heating effects can also be simulated in standardSPICE using nonlinear controlled sources. The results of suchsimulations are presented in Section V.

II. THERMAL IMPEDANCE MODEL

The DIBJT device structure assumed for the derivation ofthe thermal impedance model is based on typical wafer-bondedtransistors [1], [2], [5], [10], [11], for which buried oxideand back-filled (typically CVD oxide or a combination ofCVD oxide and polysilicon) trenches define the isolated region(referred to as the tub) where the actual device is fabricated.The silicon tub is represented by a homogeneous finite mediumwith an adiabatic top surface (no heat transfer perpendicularto the surface). The interface between the buried oxide andthe substrate is assumed to be at a uniform temperature.

0018–9383/99$10.00 1999 IEEE

2334 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 46, NO. 12, DECEMBER 1999

Fig. 1. Cross section of the simplified device geometry used to define the solution domain for the DIBJT thermal impedance model. The silicon tub isrepresented by a homogeneous finite medium with an adiabatic top surface. The model parameters are defined in Table I.

Fig. 1 shows a 3-D cross section of the simplified devicegeometry assumed for the model derivation. The definitionsof the model parameters are given in Table I. The imbeddedheat source represents the base/collector space-charge region(SCR), and is modeled by a rectangular volume. The thicknessof the base/collector SCR can be estimated using the depletionapproximation. The heat generated in this region is assumedto be due to uniform power dissipation; this assumption isreasonable for the forward-active region before the onset ofhigh-current effects [12]. The heat source is displaced beneaththe surface of the wafer by a distance equal to the depth ofthe base/collector junction. The width and length of the silicontub are chosen to scale directly with the width and length ofthe emitter stripe by the relations

(1)

and

(2)

where , , and are constants that depend on thefabrication process.

The temperature rise at any point within the tub can be de-scribed by the nonhomogeneous 3-D heat conduction equation

(3a)

and the following boundary and initial conditions:

(3b)

TABLE IPARAMETERS FOR THEDIBJT THERMAL IMPEDANCE MODEL

(3c)

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TABLE IIPHYSICAL CONSTANTS FOR THEDIBJT THERMAL IMPEDANCE MODEL

(3d)

(3e)

(3f)

where is the temperature rise above the local referencetemperature , is the internal energygeneration density, is thermal conductivity, is thermaldiffusivity [ where is density and is specificheat] and is time. Typical values for the material propertiesare given in Table II.

The terms and are normalized heat-transfercoefficients that model the time-dependent heat flow throughthe trench and buried oxide, respectively. The buried ox-ide heat-transfer coefficient is derived by assuming that theheat flux through the buried oxide is predominantly one-dimensional (1-D) [13]. By equating the temperature riseand heat flux at the buried oxide/tub interface, the 1-D heatconduction equation can be solved for giving

erf(4)

The derivation of the trench heat-transfer coefficient follows asimilar analysis. The heat flux through the trench is assumed tobe 1-D and the exterior silicon surrounding the tub and trenchis treated as four independent 1-D cooling fins with increasingcross-sectional areas. With the temperature rise and heat fluxequated at both the trench/tub and trench/exterior siliconinterfaces, the 1-D heat conduction equations in the compositetrench and exterior silicon can be solved for . Theresulting expression is shown in (5), at the bottom of the page,where and are the 1-D lumped thermal conductivityand thermal diffusivity of the composite trench structure,is the thickness of the composite trench structure, is theinverse characteristic thermal length in the exterior silicon,

is the modified Bessel function of the second kind of order, and is a constant determined by the assumed thermal

spreading angles in the exterior silicon.The solution to (3) can be expressed in the form

(6)

where is the Green’s function forthe given boundary-value problem [14]. The Green’s func-tion physically represents the temperature rise at any point

in the tub at time , due to an instantaneous pointsource at point at time . To account for the heat-generation volume , , , , ,

is integrated over the base/collector SCR. Assuming a unitstep increase in power dissipation at time and expressingthe temperature rise in the tub as

(7)

yields the transient thermal impedance

(8)

where the expressions for the eigenfunctions (, , and ),eigenvalues ( , , and ) and normalization integrals ()are determined by the boundary conditions for each dimension

erf(5)

2336 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 46, NO. 12, DECEMBER 1999

Fig. 2. Plot of the steady-state thermal resistance of Harris SemiconductorDIBJT’s with W = 3 �m anddbox = 2:2 �m, showing (8) and the modelfrom [6] compared to extracted values. The measured data were acquiredusing the base-current thermometry technique [17].

[14]. The primed eigenfunctions represent the spatial integra-tion of the eigenfunctions over the volume of the base/collectorSCR [13].

A comparison of the steady-state thermal spreading resis-tance, , of DIBJT’s manufactured atHarris Semiconductor as estimated by (8) and measurementsis shown in Fig. 2. Equation (8) should be evaluated at asingle point to generate an effective temperature for the devicebeing evaluated. For symmetric devices where ,the coordinates for the surface corner of the emitter, (

, , ) are substituted into (8). Asshown in Fig. 2, the model evaluated at these coordinatesagrees well with measured values of the steady-state thermalresistance. Fig. 2 also demonstrates the improvement of (8)over the steady-state model derived in [6], which assumesthat the temperature within the silicon tub is uniform. Fig. 3shows a comparison of the transient thermal impedance of aDIBJT calculated by ANSYS [15] and predicted by (8). Thetransient thermal impedance model agrees closely, for boththe transient and the steady-state, with the 3-D finite-elementsimulation. The largest error, which is approximately 17%,occurs in steady-state and can be partially attributed to nu-merical errors associated with limitations of the finite-elementmesh.

Fig. 4 shows a comparison of the thermal impedance modelto measured transient data extracted for the Harris devices.The plots show clearly that the model given by (8) tends toexaggerate the transient response. This discrepancy can beattributed to the model’s neglect of the thermal impedanceof the emitter interconnect [16]; this hypothesis is supportedby 3-D ANSYS transient simulations. The results of thesefinite-element simulations show that the additional heat flowpath through the emitter interconnect effectively slows thetemperature rise in the device. The extent of the metallization’seffect on the dynamic temperature response is directly relatedto the effective volume of the interconnect structure, and will

Fig. 3. Plot of the transient thermal impedance of a typical advanced DIBJTwith dtub = 1:5 �m, dbox = 0:5 �m, dtrox = 0:13 �m, dpoly = 0:5 �m,L = 2 �m, andW = 0:5 �m, showing the model compared to 3-D ANSYS

simulation results.

(a)

(b)

Fig. 4. Plot of the transient thermal impedance of Harris SemiconductorDIBJT’s with W = 3 �m anddbox = 2:2 �m, showing the model, withand without the emitter interconnect thermal model, compared to extractedvalues. The thermal resistance of the emitter interconnect wasRTHmet = 33

K/mW. The measured data were acquired using the base-current thermometrytechnique [17]: (a)L = 50 �m, CTHmet = 37 nJ/K and (b)L = 210 �m,CTHmet = 124 nJ/K.

be more pronounced for devices with substantial metal leads.The effect of the emitter interconnect on the thermal response

BRODSKY et al.: MODEL FOR VERTICAL BIPOLAR TRANSISTORS ON SOI SUBSTRATES 2337

can be modeled by an additional thermal impedance given by

(9)

where . and arethe thermal resistance and thermal capacitance of the emitterinterconnect, which can be approximated using simple 1-Dlumped thermal analysis as

(10)

(11)

where is the inverse characteristic thermal length,is the width, is the thickness, and is the effectivevolume of the emitter interconnect [13]. The overall thermalimpedance of a DIBJT device structure can now be representedby the parallel combination of two thermal impedances givenby (8) and (9). The effect of accounting for the thermalimpedance of the emitter interconnect is shown in Fig. 4,where the plots show that the model now provides a moreaccurate representation of the measured transient response.

III. A PPLICATION

The DIBJT thermal impedance model is intended to beused for predictive device modeling for circuit simulation.The data presented in the previous section, to which thethermal impedance model was compared, was generated by a3-D numerical simulator and transient thermal measurements.Multidimensional numerical simulators can provide accuratetemperature information but are inefficient; 3-D thermal sim-ulations can take hours to set up and run for each devicestructure. While the empirical approach can also provideaccurate temperature information, thermal measurements arevery time-consuming and require special equipment (e.g.,thermal wafer chuck or oven, high-speed pulse generator andoscilloscope) [9]. In addition, the results of any such extractionare limited to the specific device being measured; thus, themeasurement procedure would have to be repeated for otherdevice geometries. Therefore, neither approach is practicalfor a production environment. The DIBJT thermal impedancemodel is compact and, as shown in the previous section,capable of accurately predicting device thermal behavior usingonly geometry and material data as inputs. The DIBJT thermalimpedance model can be easily integrated into SPICE-likesimulators, allowing the anticipation of self-heating effects incircuit performance and model parameter extraction withoutmeasured or simulated thermal data. The following sectionsshow how to apply the thermal impedance model for predictiveelectrothermal circuit simulation.

IV. M ULTIPLE-POLE, THERMAL EQUIVALENT CIRCUIT MODEL

A common method for including self-heating in circuitsimulators is to use controlled sources along with a thermalequivalent circuit [4], [9]. Such an approach allows eachtransistor to operate at its own temperature, which is computedin each iteration loop based on the device’s instantaneouspower dissipation. A current source proportional to the power

is connected to a thermal impedance at an added devicenode; the resulting voltage at this node corresponds to thedevice temperature rise. This temperature is used to adjust alltemperature-dependent parameters within the device model.The simulator then iterates until a self-consistent solution isfound.

Equation (8) gives an analytical model for the thermalimpedance of a DIBJT; however, most circuit simulators can-not directly represent such expressions. An efficient method forincorporating the thermal impedance into a circuit simulatoris provided by fitting a multiple-pole, RC network to thethermal impedance model. Such thermal circuit representa-tions are suitable for dc, ac, and transient simulations, whileincreasing simulation time only slightly. The TIPP softwarepackage can be used to determine the element values forsuch multiple-pole, thermal equivalent circuits. Initially, TIPPgenerates the thermal impedance using the physical model.Then, TIPP calculates the component values for an RC-ladderrepresentation of the thermal impedance model by fitting thefollowing equation:

(12)

to (8); the RC network can have up to five poles. Fitting (12)to (8) is accomplished using a heuristic algorithm that is moreefficient than nonlinear optimization. The magnitude of thecalculated thermal impedance model is scanned for the specifictimes that correspond to certain fractions of the responsemaximum. The times at which these percentages are obtainedapproximate the thermal time constants () of the response.A linear least-squares fit is then used to calculate the thermalresistance components (). The thermal capacitances arecomputed from the time constants and the thermal resistancecomponents. TIPP provides the resulting component valueswhich can then be used in a circuit simulator.

V. SIMULATION RESULTS

DC and transient electrothermal circuit simulations wereperformed, using a modified version of the Gummel–Poon BJTmodel in SPICE 2G.6 [9], to demonstrate the implementationof the thermal impedance model; the program was modified,as described in the previous section, to provide electrothermalsimulation capabilities. A BJT parameter set extracted for aHarris NPN DIBJT with an emitter area of 3 50 mwas used for all simulations. As shown in Figs. 2 and 4, thethermal impedance model provides an accurate representationof both the steady-state and transient thermal response forthis device geometry. Therefore, when the thermal impedancemodel is used in conjunction with the corresponding compactBJT model, the resulting electrothermal simulations providea reasonable prediction of the self-heating effects duringdevice/circuit operation.

The thermal impedance model for the corresponding devicestructure was represented by a three-pole thermal-equivalentcircuit (three poles provided the best compromise between

2338 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 46, NO. 12, DECEMBER 1999

Fig. 5. Plot of dc output characteristics simulated with the thermal versionof SPICE:L = 50 �m, W = 3 �m, andVBE = 0.75, 0.775, and 0.8 V.

Fig. 6. Plot of transient collector current simulated with the thermal versionof SPICE:L = 50 �m, W = 3 �m, VBE = 0:775 V, andVC is steppedfrom 1 to 5 V with 1-ns rise/fall times, 20-�s pulse width and 42-�s period.

simulation time and simulation accuracy). Fig. 5 shows thesimulated dc output characteristics for a single transistor inthe common-emitter configuration. The plots show how thecollector current increases at elevated temperatures due tothe exponential increase of the intrinsic carrier concentrationwhich results in an increase of minority carriers in the base.Fig. 6 shows the effects of self-heating on the transient col-lector current. On the rising edge of the pulse, the currentof the self-heated device tracks that of the isothermal devicesince the temperature lags the electrical response. However,the device temperature increases during the pulse duration,causing an increase in current. As the collector voltage returnsto its initial value, the collector current is higher than expectedsince the device temperature is initially higher than the valueconsistent with the lower collector voltage. The collectorcurrent slowly decreases as the device cools down during thelow side of the pulse. Both Figs. 5 and 6 clearly show that

TABLE IIICIRCUIT SIMULATION PERFORMANCE WITH AND WITHOUT SELF-HEATING

neglecting self-heating during device/circuit simulations couldcause underestimates of dc bias currents or circuit settlingtimes [4].

Table III shows the effect of including self-heating onthe simulation time. The numbers in the table reflect thetotal job times and iteration counts for the specific analyzes.AC simulations use a small-signal linearized circuit and arerelatively insensitive to the addition of the thermal network.However, the dc and transient analyzes demonstrate thatincluding self-heating does require increased simulation time,mostly due to slowed convergence.

VI. CONCLUSIONS

A physics-based thermal impedance model for DIBJT’swas developed for efficient electrothermal circuit simulation.The model was derived by solving the 3-D heat conductionequation using acceptable heuristic assumptions. The thermalimpedance model was compared to steady-state thermal resis-tance measurements and 3-D transient ANSYS simulationswith good results. The model was shown to over-predictthe transient temperature rise due to the adiabatic boundarycondition assumed at the device surface. With the addition ofa model to account for the thermal impedance of the emitterinterconnect, the model exhibited a good correlation withtransient thermal impedance measurements. Circuit simulationexamples, which were performed using a thermal version ofSPICE, were presented and demonstrated the expected devicebehavior in the presence of self-heating. Addition of thethermal-equivalent circuit increased the simulation time onlymoderately. Consequently, such an electrothermal modelingmethodology can provide an efficient tool for investigating theeffects of self-heating on DIBJT circuit operation, parameterextraction and device/circuit reliability.

REFERENCES

[1] C. Davis et al., “UHF-1: A high-speed complementary bipolar analogprocess on SOI,” inProc. IEEE BCTM,1992, pp. 260–263.

[2] R. C. Jeromeet al., “ACUTE: A high-performance analog comple-mentary polysilicon emitter bipolar technology utilizing SOI/trench fulldielectric isolation,” inProc. IEEE Int. SOI Conf.,1993, pp. 100–101.

[3] P. R. Ganciet al., “Self-heating in high-performance bipolar transistorsfabricated on SOI substrates,” inIEDM Tech. Dig.,1992, pp. 417–420.

[4] R. M. Fox, S.-G. Lee, and D. T. Zweidinger, “The effects of BJT self-heating on circuit behavior,”IEEE J. Solid-State Circuits,vol. 28, pp.678–685, June 1993.

[5] H. Nishizawa et al., “A fully SiO 2-isolated self-aligned SOI-bipolartransistor for VLSI’s,” inProc. IEEE BCTM,1991, pp. 53–58.

[6] D. T. Zweidinger, J. S. Brodsky, and R. M. Fox, “A physical thermalresistance model for vertical BJT’s on SOI,” inProc. IEEE Int. SOIConf., Oct. 1995, pp. 84–85.

[7] C. C. McAndrew et al., “VBIC95, the vertical bipolar inter-companymodel,” IEEE J. Solid-State Circuits,vol. 31, pp. 1476–1483, Oct. 1996.

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[8] J. S. Brodsky, “TIPP: Thermal impedance pre-processor version 0.5,”User’s Reference,Dept. ECE, Univ. Florida, Gainesville, Tech. Rep.,1995.

[9] D. T. Zweidinger, “Modeling of transistor self-heating for circuit simu-lation,” Ph.D. dissertation, Univ. Florida, Gainesville, Aug. 1997.

[10] S. Feindtet al., “XFCB: A high-speed complementary bipolar processon bonded SOI,” inProc. IEEE BCTM,1992, pp. 264–267.

[11] T. Nakamura and H. Nishizawa, “Recent progress in bipolar transistortechnology,”IEEE Trans. Electron Devices,vol. 42, pp. 390–398, Mar.1995.

[12] M.-Y. Chuang, “Three-dimensional distributed effects on the DC andAC performance of high-speed semiconductor devices,” Ph.D. disserta-tion, Univ. Florida, Gainesville, Aug. 1997.

[13] J. S. Brodsky, “Physics-based thermal impedance models for the sim-ulation of self-heating in semiconductor devices and circuits,” Ph.D.dissertation, Univ. Florida, Gainesville, Aug. 1997.

[14] M. N. Ozisik, Heat Conduction,2nd ed. New York: Wiley, 1993.[15] ANSYS User’s Manual, Rev. 5.2, Swanson Analysis Systems, Houston,

PA, 1995.[16] R. C. Joy and E. S. Schlig, “Thermal properties of very fast transistors,”

IEEE Trans. Electron Devices,vol. ED-17, pp. 586–594, Aug. 1970.[17] D. T. Zweidinger et al., “Thermal impedance extraction for bipolar

transistors,”IEEE Trans. Electron Devices,vol. 43, pp. 342–346, Feb.1996.

Jonathan S. Brodsky received the B.S. degreein electrical engineering from Lafayette College,Easton, PA, in 1991 and the M.S. and Ph.D. degreesin electrical engineering from the University ofFlorida, Gainesville, in 1993 and 1997, respectively.His Ph.D. research dealt with the development ofcompact thermal impedance models for advancedsemiconductor device structures.

Since 1997, he has been with Texas Instruments,Dallas, TX, in the Mixed Signal Products ESDLab. His current responsibilities include the design,

development, and implementation of ESD protection circuits for TI processtechnologies.

Robert M. Fox received the B.S. degree in physicsfrom the University of Notre Dame, Notre Dame,IN, in 1972 and the M.S. and Ph.D. degrees in elec-trical engineering from Auburn University, Auburn,AL, in 1981 and 1986, respectively.

Since 1986, he has been on the faculty of theDepartment of Electrical and Computer Engineer-ing at the University of Florida, Gainesville. Hisresearch emphasizes circuit design and modelingfor advanced IC technologies. He has worked on avariety of topics including analog circuits, cryogenic

electronics, circuit design with SOI, radiation response of semiconductors,noise modeling, and modeling of transistor self-heating. Currently, his researchinterests center on design-oriented analysis of analog IC’s, including low-voltage circuit techniques, log-domain circuit design, and transistor modeling.

David T. Zweidinger was born in Gainesville, FLin 1967. He received the B.S., M.S., and Ph.D.degrees in electrical engineering in 1990, 1993, and1997, respectively, from the University of Florida,Gainesville.

From 1997 to 1999, he worked on simulationdesign environment, statistical circuit modeling, andconvergence issues for Harris Semiconductor. Heis now with Texas Instruments, Dallas, TX, in theTISPICE group. His current responsibilities includeSPICE model enhancements (including self-heating)

and design environment enhancements.