A PCI Card for Readout A PCI Card for Readout in High Energy Physics in High Energy Physics

ExperimentsExperiments

Michele Michele FlorisFloris1,21,2, Gianluca , Gianluca UsaiUsai1,21,2, Davide Marras, Davide Marras22, André , André

DavidDavid33

2003 IEEE Nuclear Science Symposium – October 19 -25 Portland, Oregon, USA

1) Dipartimento di Fisica, Università degli studi di Cagliari, Italy.

2) INFN, Sezione di Cagliari, Italy.3) CERN, Geneva, Switzerland

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OutlineOutline

►Motivations and requirementsMotivations and requirements► ImplementationImplementation►ApplicationsApplications

NA60 DAQNA60 DAQ►Muon SpectrometerMuon Spectrometer►Quartz fiber Zero Degree CalorimeterQuartz fiber Zero Degree Calorimeter►Silicon strip Beam TrackerSilicon strip Beam Tracker►Silicon pixel Vertex TelescopeSilicon pixel Vertex Telescope

AliceAlice Muon tracking chambers Muon tracking chambers test systemtest system

FFLLEEXXIIBBIILLIITTYY

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Motivation & design Motivation & design requirementsrequirements

►NA60 Experiment DAQNA60 Experiment DAQ Fast developmentFast development

►NA60 is a running experimentNA60 is a running experiment

FlexibilityFlexibility►Readout of 4 different detectorsReadout of 4 different detectors

PartitionsPartitions Tracking MWPCs

Trigger hodoscopes

Toroidal Magnet

FewallMuon filter

ZDC and Quartz Blade

TARGET AREA

MUON SPECTROMETER~1m

MUON FILTERBEAM

TRACKER

TARGETBOX

TELESCOPE

Dipole field2.5 T

BEAMIC

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NA60 readout systemNA60 readout system

► NA60 readout is spill-bufferedNA60 readout is spill-buffered DAQ handshake with readoutDAQ handshake with readout

systemsystem

DAQ PC

MEZZANINE PCI CardDET

NA60 DAQ scheme

burst

interburst

burst

events - trigger

►PCI based system:PCI based system:Good performances / low costGood performances / low costReadout of several different detectorsReadout of several different detectors

►General purpose PCI readout cardGeneral purpose PCI readout card►Detector specific mezzanineDetector specific mezzanine

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The PCI-CFDThe PCI-CFDAltera EP20K100,BGA package• flexibility• reliability

PLX 9030 (PCI Target)

• Fast development• Bandwidth: 30 MB/s

PMC connectors (not fully compliant

IEEE 1386.1)

64 MBSDRA

M

~ 2 months from the first schematic~ 2 months from the first schematic to a working prototypeto a working prototype

Tristate buffer (JTAG input)

PLX EEPROM

1-WireUnique

ID

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USERAPPL.

PCI interface

RAMCTRL

REGs

PCI-CFDPCI-CFD

SDRAM

PLX 9030

ME

ZZ

AN

INE

Only these blocks change between different applications

CTRL

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JTAG ConfigurationJTAG Configuration

PLX

CONN

MEZZANINE

CFD and mezzanine FPGAs can be JTAG programmed via PCI

busTRISTATE

The PLX has some general purpose I/O, we used them to implement a JTAG interface The JTAG chain

can be extended to the

mezzanine, using a jumper

A tristate buffer is used to multiplex JTAG inputs

FPGAEPROM

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SoftwareSoftware► Linux software has been developedLinux software has been developed

PLX Eeprom programmingPLX Eeprom programming PCI JTAG configurationPCI JTAG configuration DriverDriver

► Sample codeSample code PCI memory is seen as an PCI memory is seen as an

““extension” of main memory!extension” of main memory!

open (/dev/cfdX, “O_RDWR”);

mmap (... ... , “REGISTERS/MEMORY”);

memcpy (in, out, size);

Interfacing with (DAQ)

software is extremely

easy!

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NA60 VME-like/FERA interfacesNA60 VME-like/FERA interfaces►Very simple mezzanineVery simple mezzanine

Level conversion ECL/NIM => TTLLevel conversion ECL/NIM => TTL Protocol itself implemented in PCI Card FPGAProtocol itself implemented in PCI Card FPGA R/O of 3 detectors implementedR/O of 3 detectors implemented 2 different protocols (RMH/FERA)2 different protocols (RMH/FERA)

BURSTBUSYTRIGGER

Protocol control signals & data

PCICard

triggerstart_read

encodedflagdata

end_of_read

GOL chip hybrid withassemblies

NA60 Pixel readoutNA60 Pixel readout► Pixel detectorPixel detector

Almost 800k channelsAlmost 800k channels Several configurable parametersSeveral configurable parameters

► Complex mezzanineComplex mezzanine Readout control – zero suppression (FPGA)Readout control – zero suppression (FPGA) Temporary data Temporary data

storage (FIFOs)storage (FIFOs)

See also N16-5 at this conference

FIFo

PCI-CFD

PILOT chip

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NA60 Pixel readout – cont’dNA60 Pixel readout – cont’d

►Serial link PCI-CFD => mez.Serial link PCI-CFD => mez. Detector & electronics configurationDetector & electronics configuration

Command register

Start register

101101110010

FIFO

Output register

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Alice Test systemAlice Test system► 1 fully equipped slat 1 fully equipped slat

chamber readoutchamber readout► AD DSP emulation AD DSP emulation

in FPGAin FPGA► Custom DAQ Custom DAQ

softwaresoftware

See also N26-35 at this conference

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ConclusionsConclusions► PCI bus offers very attractive featuresPCI bus offers very attractive features

High PerformancesHigh Performances Low costLow cost Easy interfacing with SWEasy interfacing with SW

► Using hardware cores PCI cards can be Using hardware cores PCI cards can be developed with little effort developed with little effort

► Flexibility: Flexibility: FPGAFPGA MezzaninesMezzanines Several different applications:Several different applications:

► VME-like, FERA interfacesVME-like, FERA interfaces► Custom applications: pixel readout, DSP emulationCustom applications: pixel readout, DSP emulation