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A Novel Transformer-less Uninterruptible Power Supply
A Thesis Submitted for the Degree of
Master of Science (Engineering) In Faculty of Engineering
By
S. Giridharan
Department of Electrical Engineering, Indian Institute of Science,
Bangalore 560 012
September 1996
ACKNOWLEDGEMENTS
I am grateful to Dr. V. Ramanarayanan, for giving me an opportunity to work with him on a
problem that was both challenging and practically relevant. I thank him for providing all the
necessary facilities. I have learnt much from him through lectures and discussions. I consider myself
fortunate to have worked with him.
I thank Dr. V. T. Ranganathan for the many useful discussions we had during my stay with
the Power Electronics Group.
I thank my friends and the members of the Power Electronics Group for their help and
support. I thank Mrs. Silvi Jose for extending support in financial matters during the construction of
the prototype.
ABSTRACT
Uninterruptible Power Supplies (UPS) are finding increased applications with the advent of
sophisticated electronic equipment. Low power equipment like FAX machines, Personal
Computers, etc., form the major portion of the applications. There is a need for cost-effective, light
and sleek UPS in the low power range.
In low power UPS, the presence of line frequency magnetic components makes the system
bulky and costly. In this thesis, a circuit configuration suitable for low power UPS is proposed in
which the line frequency magnetic components are eliminated. Elimination of the line frequency
magnetic components necessitates the use of a high voltage DC bus. Cost considerations keep the
battery voltage low. These factors prompt the use of a bi-directional interface between the high
voltage DC bus and the battery. The design and the development of a bi-directional interface is the
highlight of this work.
The front end of the proposed UPS is a bridge rectifier followed by a Boost converter.
Unity power factor operation is achieved by programming the current through the boost inductor to
be a rectified sinusoid. The output of the boost converter is the DC bus voltage which is controlled
by controlling the magnitude of the current through the inductor. The model of the converter and the
design of the controller to achieve unity power factor operation and DC bus voltage regulation are
presented.
The inverter is a single phase H-bridge inverter. The switching pattern used is generated by
using unipolar Sinusoidal Pulse Width Modulation (SPWM) technique. The harmonic content in
the switching pattern is presented. The switching harmonic content in the output of the inverter is
attenuated by using an appropriate passive filter at the output of the inverter.
The bi-directional interface is realised using the tapped inductor boost converter circuit. The
operation of the converter and the sequence of events in one switching period are explained. The
mathematical model of the converter is obtained by circuit averaging technique. Instantaneous flux
programming control scheme (similar to instantaneous current programming) is used to control the
converter. The model of the converter in this control scheme is derived. The design of suitable
compensators to achieve Battery charge control (when the Mains power is present) and the DC bus
voltage control (when the Battery is supplying power to the critical load) are presented.
The mathematical model of the different converters are simulated using SIMULINK, a
platform in MATLAB. The simulation results of the complete UPS, constructed by interfacing the
model of the various converters, is presented. The design strategies developed in this thesis were
used to construct a 250 VA prototype UPS. The steady state and dynamic tests were performed.
The performance evaluation results are presented. The results confirm the model and the design
methodology.
CONTENTS
1. Introduction 1
1.1 A brief review of the conventional UPS 11.2 The proposed circuit configuration for a transformerless UPS 31.3 Need for a bi-directional power converter
with very high voltage transfer ratio 41.4 Simulation results and Performance evaluation 5
2. The Front End Converter 7
2.1 Power circuit and selection of filter components 72.2 Dynamic model of the converter
in the average current controlled mode 102.3 Design of the controllers to achieve 13
2.3.1 Input power factor correction 132.3.2 Output voltage regulation
by feed back of output voltage 152.3.3 Output voltage regulation
by feed forward of input voltage 16
3. The Bi-directional Converter 19
3.1 Selection of topology for the bi-directional converter 193.2 Power circuit and the filter component selection 25
3.2.1 Ideal power circuit of the bi-directional converter 253.2.2 Operation of the converter in the two modes 273.2.3 Selection of filter components 333.2.4 Practical non-idealities and their effect 36
3.3 Dynamic model of the converter by state space averaging 39(Duty ratio programmed control)3.3.1 Buck mode 403.3.2 Boost mode 47
3.4 Dynamic model in flux programmed mode of operation 493.4.1 Model of the flux programmed control scheme 513.4.2 Model of the converter 53
3.5 Design of voltage loop controller 583.5.1 Battery charge controller 603.5.2 DC bus voltage controller 613.5.3 Seamless transfer of power flow direction 63
4. The Inverter 65
4.1 Power circuit 654.2 Switching strategy 664.3 Filter design 704.4 Model of the inverter 71
5. Simulation and Performance Evaluation Results 73
6. Conclusion 137
References 141
CHAPTER 1
INTRODUCTION
In recent years, the use of Uninterruptible Power Supplies (UPS) has become standard with
sophisticated electronic equipment. Stand alone electronic equipment like Personal Computers,
FAX machines, communication relay equipment and other office equipment that consume little
power (less than 200 Watt), comprise the major portion in the list of applications that need
uninterrupted power. Therefore, there is a great demand for UPS in the low power range. The
desirable features in such UPS are low cost, low weight, silent operation and compactness.
In the conventional UPS, the presence of low frequency matching transformers makes the
system heavy and bulky. Nearly 30% of the total cost is on account of these matching
transformers. They also contribute to around 50% of the total weight of the system. In the
industry, the present quest for a sleek, light and cheap UPS follows two courses. The first is to use
circuit topologies where the matching transformers handle power at high frequency. The other is to
eliminate the matching transformers.
In this thesis, the course of developing a UPS without matching transformers is pursued. To
complement this effort, a bi-directional switched mode power converter has been developed. The
scope of this thesis covers the design, fabrication and evaluation of the bi-directional converter. A
transformerless UPS rated for 250 VA has been built and the performance of the bi-directional
converter evaluated.
1.1 A brief review of the conventional UPS
In the present market, single phase UPS are available over a wide range of power rating.
The generalised block diagram of a conventional UPS is shown in Fig. 1.1. The typical
specifications of a UPS are
Input voltage and its tolerance
Output voltage and its tolerance
Battery voltage
Battery capacity for a given backup time
SinglePhaseMains +
SinglePhaseInverter
Fig. 1.1 Block diagram of a conventional UPS
Battery
Load+V BusDC
ControlledThyristorRectifier
The input stage of the system is a semi/fully controlled thyristor rectifier whose output is a
regulated DC voltage. The battery floats on this DC bus. In low capacity systems, the major cost is
taken up by the battery. The battery count is kept low to reduce the total cost of the system.
Consequently, in this range of systems, the battery voltage is low.
The ac to dc conversion is done by the front end thyristor rectifier. The input step- down
transformer ensures that the thyristor converter operates at a good power factor. This transformer
handles power at the line frequency (50 Hz) and is bulky. Another associated feature of the front
end converter shown in Fig. 1.1, is the presence of harmonics in the ac input current.
The UPS delivers power at the utility level ac voltage (230 Volt). It is necessary to use a
matching transformer between the output of the inverter and the load. This matching transformer
handles power at 50 Hz and is bulky. The input and output transformers, apart from being bulky and
heavy, account for around 30% of the total cost of the UPS.
In battery backed up power supplies, the efficiency of power conversion is important. The
better the efficiency, the more the backup time for a given battery. The efficiency of the front end
converter and the inverter improve with increase in the battery/DC bus voltage. The loss in the
system warrants the use of proper thermal management.
2
1.2 The proposed configuration for a transformerless UPS
The matching transformer at either end of the UPS is a direct consequence of the low
battery/DC bus voltage. Figure 1.2 shows an alternative UPS configuration. The input and the
output transformers are absent. The battery voltage is still kept low.
FrontEnd
ConverterPhaseMains
+
Bi-directionalConverter
SinglePhaseInverter
Fig 1.2 Overall Block diagram of the proposed system
Battery
Load+V BusDCSingle
In this scheme, to obtain the utility level voltage at the output (230 Volt), the DC bus voltage
has to be high. The minimum DC bus voltage required for a single phase 230 Volt ac output is 325
Volt. The circuit configuration of the inverter and the output filter is shown in Fig 1.3. The filter
provides adequate harmonic suppression at the output. Further aspects of the inverter, the switching
strategy and the design of the filter are discussed in Chapter 4.
S1
S2
S3
S4
L
C LoadVdc
Fig 1.3 The Inverter and the output filter
The front end converter has to meet the following specifications.
Input voltage and its tolerance
DC bus voltage, its load and line regulation
Input power factor
Total Harmonic content in the input current
3
An elegant circuit to realise the front end converter is given in Fig. 1.4. The circuit is a boost
converter connected to the output of the diode bridge rectifier. The necessary condition for the
operation of the boost converter is that the output voltage be greater than the input voltage.
+
SL
C To InverterSinglePhaseMains
DiodeBridge
Fig 1.4 The front end converter
The boost converter is implemented using the switch S and the filter components L and C.
The current through the inductor is programmed to be a rectified sinusoid. This makes the current
drawn from the Mains sinusoidal. Thus the harmonic content in the input current is made small.
Further, this circuit affords power factor control as well. The peak input voltage of the boost
converter is around 385 Volt for a high end mains voltage of 270Volt. The output of the boost
converter has to be, therefore, more than 385Volt. Looking from the inverter end, this increase in
the DC bus voltage improves the performance of the inverter. A convenient DC bus voltage of
400Volt is chosen.
Chapter 2 deals with the analysis, modelling, control and design of the front end converter.
1.3 Need for a bi-directional power converter with high voltage transfer ratio
The advantage of transformerless operation is achievable when the intermediate DC bus
voltage is high. However, cost considerations force the battery voltage to be low. The essence of
the above design constraints is the presence of an interface between the battery and the DC bus
(shown in Fig. 1.2 as the Bi-directional converter). The battery can be charged from the DC bus, if
this interface can handle bi-directional power flow. Typically a battery of 48 Volt is used in low
capacity UPS. The suggested DC bus voltage for transformerless operation is 400 Volt. The
bi-directional converter, therefore, has to cater for a large voltage conversion ratio ( 10).≈
4
Chpater 3 presents a variety of switched mode power converters for the purpose. A
suitable converter among them is selected based on the design needs. The analysis of operation,
modelling, selection of power circuit elements and the design of controller for the bi-directional
converter are presented.
1.4 Simulation results and Performance evaluation
The model of the UPS is put together using the subsystems developed in the chapters 2, 3
and 4. The same is the basis for the numerical simulation carried out. The commercial software
package SIMULINK is used for the purpose. A prototype UPS of 250 VA rating has been built.
Chapter 5 gives the simulation and the performance evaluation results of the UPS. The concluding
chapter summarises the work.
5
CHAPTER 2 THE FRONT END CONVERTER
This chapter presents the requirements connected with the front end converter. Issues
regarding the operation, the analysis and modelling of the converter are presented. The design of a
controller to achieve unity power factor operation and to achieve DC bus voltage regulation are
discussed in the subsequent sections of the chapter.
The front end converter, as suggested in Chapter 1, has a diode bridge rectifier followed by
a boost converter. The necessary condition for the operation of the boost converter is that the
output voltage be greater than the input voltage. The front end converter has to meet the following
specifications.
Input voltage and its tolerance
The output voltage of the converter and its line and load regulation
Input power factor
Harmonic current drawn from the mains
2.1 The Power Circuit and selection of filter components
The diode bridge rectifier followed by the boost converter circuit put together to form the
front end converter is shown Fig. 2.1. To get sinusoidal input current, the current drawn by the
boost converter has to be a rectified sinusoid. Since the current through the boost inductor is
continuous in nature, it can be programmed to follow any desired reference (which is a rectified
+ To InverterSinglePhaseMains
DiodeBridge
Fig. 2.1 The front end converter
+Vdcbus
C
L
Q
D
(Circuit implementation using practical switches)
G
+
-
sinusoid). This makes the input current drawn from the mains sinusoidal. The output voltage of the
rectifier bridge has the required waveshape and the reference current can be derived from it. This,
further, keeps the reference current in-phase with the mains voltage.
To achieve the desired current waveshape through the inductor, the average current
programmed control scheme is used . In the present case the shape of the current through the[1]
inductor has to be a rectified sinusoid. The reference waveform is taken from the output of the
bridge rectifier which has the required waveshape. The current magnitude reference used for the
average current programmed control is derived from an outer voltage loop controller. The voltage
loop controller, used to achieve DC bus voltage regulation, is driven by the error in the DC bus
voltage. The reference waveform and the current magnitude reference are multiplied to generate the
reference current for the inner current loop. The input voltage usually varies over a wide range.
When the reference current is generated from the input rectified voltage, the magnitude of the
reference current also varies. It is necessary that the magnitude of the reference current be
independent of the input voltage variations. This is achieved by feeding forward the input voltage
appropriately. The design of this control scheme is discussed in detail in Sec. 2.3. A reference
current generated from the mains rectified voltage ensures that the input current drawn is in-phase
with the mains voltage. Thus, unity power factor operation is an inherent characteristic of this
control scheme.
Selection of Filter components :
The filter components, namely, the inductor L, and the DC bus capacitor C, are designed
based on the tolerances in the input current ripple and the output voltage ripple introduced due to
the switching action of the converter. The ripple factor in the input current is expressed as a
percentage of the peak inductor current. By power invariance, the relationship between the input
and output power is given by
.....(2.1a)Vin_min
Ipeak
2= Po
INVeff BOOSTeff
8
The peak inductor current, is given byIpeak
.....(2.1b)Ipeak =
2
PoINVeff
1Vin_min BOOSTeff
where is the rated output power of the system in Watt;Po are the efficiencies of the inverter INVeff, BOOSTeff
and the boost converter; is the minimum rms. input voltage in Volt;Vin_min
The average input voltage, of the boost converter is given byVin_avg
.....(2.2)Vin_avg =2 2
π Vin_rms
where is the nominal input rms. voltage in Volt;Vin_rms
Unlike conventional switched mode power converters, this converter has an input which is
rich in harmonics. The design of the filter components is made around a nominal operating point.
The average input voltage, is taken to be the nominal input voltage of the converter.Vin_avg
For a given value of the DC bus voltage, the nominal operating duty ratio, is given by(Dnom)
.....(2.3)Dnom = 1 −Vin_avg
VDC_bus
where is the nominal DC bus voltage in Volt;VDC_bus
The value of the inductor, is chosen for a given ripple in the inductor current using the(L)equation
.....(2.4)L = Vin_avgDnom
(Ripple%) Ipeak fs
where is the allowed ripple expressed as a percentage;(Ripple%) is the switching frequency in Hertz;fs
The DC bus capacitor, conventionally, is selected based on the switching ripple allowed in
the DC bus voltage. In off-line applications, it is usual to select the filter capacitor, , based on aC
guaranteed minimum hold up time . In the present case, the hold up time for a certain drop in the[2]
9
DC bus voltage is chosen to be one half cycle (10 millisecond). The following relations help in
designing a suitable capacitor for the purpose. The average load current taken by the inverter,
from the DC bus is given byIbus_avg
.....(2.5)Ibus_avg = PoINVeff VDC_bus
The value of the capacitor, is given by(C)
.....(2.6)C = Ibus_avgThold
(Drop%) VDC_bus
where is the hold up time required in the DC bus voltage in seconds;Thold is the percentage drop allowed in the DC bus voltage;(Drop%)
2.2 Dynamic model of the converter in the average current controlled mode
The use of the front end converter with unity power factor operation is widespread and the
dynamic model and the design methods for the controller are readily available . This section[3,4]
briefly describes the modelling of the converter in the average current controlled operation. The
small signal model of the converter and the controller is shown in Fig. 2.2. This model is valid for
frequencies much below the switching frequency. Unity power factor operation and DC bus voltage
regulation are the features achieved in this control scheme. The inner loop is closed on the inductor
10
+-
G1(s)H1(s) G2(s)
H2(s)
Hff
G Iref
I*
Ifb
iL
Vdcbus
VerrAU
Fig. 2.2 Block diagram of dynamic model of the boost converter
Vc
+-
Vref
VrmsNote : The bold blocks represent
the converter model
current. The reference to the inner current loop is generated from the output of the rectifier bridge.
The control of the DC bus voltage is accomplished by providing a voltage loop compensator whose
output scales the current reference.
The gain of the converter, , from the control voltage to the inductor current G1(s) Vc IL
for frequencies much below the switching period is derived by considering the average voltage
across the inductor. It is assumed that the input voltage to the boost converter remains unchanged
for the time duration under consideration. So this model is valid for frequencies which are very
much higher than the frequency of the input voltage and which are very much below the switching
frequency. (The switching frequency is at least 1000 times the fundamental frequency of the rectifier
output). The average voltage across the inductor, is given byVL
.....(2.7)VL = d Vin + (1 − d) (Vin − VDC_bus)
where is the duty ratio of the controlled switch Q;d
is the input voltage to the boost converter;Vin(same as the output of the rectifier)
is the DC bus voltage;VDC_bus
The rate at which this voltage changes for small changes in the duty ratio is derived by
differentiating Eq. (2.7) and is given by
.....(2.8)V∼
L(s) = VDC_bus d∼
(s)
where is the complex frequency at which the duty ratio changes;s
The small signal relationship between the inductor voltage, and current, is given byV∼
L(s) I∼
L(s)
.....(2.9)V∼
L(s) = sL I∼
L(s)
By equating Eq. (2.8) and (2.9), the small signal relationship between the duty ratio and
inductor current is readily derived as
.....(2.10)I∼
L(s)
d∼
(s)=
VDC_bussL
11
The duty ratio, , is derived practically by comparing a control voltage, , with a rampd Vc
function whose frequency is . The gain of the Pulse Width Modulator (PWM) is expressed as thefs
ratio of the control voltage to the duty ratio. Once again, this model is valid for frequencies very
much below the switching frequency. The expression for the PWM gain is given by
.....(2.11)d∼
(s)V∼
c(s)= 1
Vpk
where is the peak to peak magnitude of the carrier waveform;Vpk
The gain of the boost converter, , from the duty ratio to the inductor current followsG1(s)
from Eq. (2.10) and Eq. (2.11) and is given by
.....(2.12)G1(s) =I∼
L(s)
V∼
c(s)= K1
s
where K1 =VDC_busL Vpk
The asymptotic bode plot of the control transfer function, , of Eq. (2.12) is shown inG1(s)
Fig. 2.3.
-20dB/decadeGain
Phase-90
Fig. 2.3 Bode plot of G1(s)
-20dB/decadeGain
Phase-90
Fig. 2.4 Bode plot of G2(s)
The gain, in the block diagram of Fig. 2.2 corresponds to the filter capacitor and theG2(s)
load resistor. This is simple first order lag whose asymptotic bode plot is shown in Fig.2.4. This
model of the boost converter is used to design the current loop controller, and the voltageH1(s)loop controller, .H2(s)
12
2.3 Design of controllers
2.3.1 Current loop controller design
The open loop transfer function of the current loop from the control voltage, to theV∼
c(s)inductor current, is given by Eq. (2.12). The desired response in the inductor current is that itI
∼L(s)
tracks the reference current waveform. The reference current itself is time varying. This demands a
large, preferably infinite, velocity error constant to obtain zero steady state velocity error. The
velocity error constant, is given byKV
.....(2.13)KV =s→0
Lt [s G1(s)]
In the present case, the velocity error constant is seen to be for the current loop. TheK1
steady state velocity error is given by
.....(2.14)e(∞) = 1KV
= 1K1
The steady state velocity error is dependent on the circuit parameters and the output
voltage. Zero steady state velocity error can be achieved by adding an integrating compensation in
the block. Along with the controller, the open loop transfer function is given byH1(s)
.....(2.15)G1(s).H1(s) = 1s
K1s
⇒ KV =s→0
Lt K1s
= ∞
⇒ e(∞) = 1KV
= 0
The steady state error is now independent of the output voltage and the circuit parameter
variations. The asymptotic bode plot of the open loop system transfer function with integral
compensation is shown in Fig. 2.5. (The plot without compensation is shown in dotted lines).
13
-40dB/decadeGain
Phase-90
-180
Fig. 2.5 Bode plot of G1(s).H1(s)
-40dB/decade
Gain
Phase-90
-180
Fig. 2.6 Bode plot of G1(s).H1(s)
-20dB/decade
m
The integral compensation, (though improves the performance by reducing the steady state
velocity error to zero), reduces
the bandwidth of the system drastically and
the phase margin to zero
The effect of reduction in bandwidth is higher distortion in the current waveform (because
higher harmonics in the reference waveform are not forced in the inductor current faithfully).
Obviously, a phase margin close to zero is not desirable. It is therefore necessary to improveΦm
the phase angle of the loop gain. To increase the phase margin and to make the crossover slope as
-20dB/decade, a single zero can be introduced anywhere before the gain crossover frequency. But,
in practice, realising a single zero is not possible. The next closer approximation, which is a lead
compensator, is used. The general transfer function of a lead compensator is given by
.....(2.16)L(s) = 1+s/z1+s/p
where indicates the pole and zero locations;p = α.z, α > 1
The asymptotic bode plot of the open loop system with the current controller is shown in
Fig. 2.6. The relative position of the pole and the zero can be found out from the phase margin and
the bandwidth requirements . The following relations help in designing the location of the pole[5]and zero.
.....(2.17)α = 1+sin(Φm)1−sin(Φm)
14
.....(2.18)ωc = α .zFor example, to get a phase margin of , , the pole should be placed one55o α = 10
decade above the zero.
To adjust the bandwidth of the current loop, a gain is introduced in the transfer functionK2
of the current controller. The bandwidth of the current loop is chosen such that the reference
waveform is tracked with good accuracy. This calls for an analysis of the harmonic content in the
reference waveform. The reference waveform is a rectified sinusoid with considerable harmonic
content upto the 10th harmonic, whose break up is
Average DC value 63.7%
Second harmonic 42.4%
Fourth harmonic 8.5%
Sixth harmonic 3.6%
Eigth harmonic 2.0%
Tenth harmonic 1.3% + Higher harmonics
Since the switching frequency is very high compared to the fundamental, (at least 1000
times) the bandwidth can be chosen to be around one tenth the switching frequency which can
faithfully reproduce sufficient order of harmonics in the current waveform. The final transfer function
of the current loop compensator, , is given byH1(s)
.....(2.19)H1(s) = K2 1
s
1+s/z1+s/p
The open loop transfer function of the current loop, , is then given byG1(s).H1(s)
.....(2.20)G1(s).H1(s) =
K1s
K2 1
s
1+s/z1+s/p
2.3.2 Output voltage regulation by feedback of output voltage
Output voltage regulation is achieved by multiplying the current reference given to the
current loop by a voltage error, , that is generated by the voltage loop compensator, .Verr H2(s)
(Fig. 2.2). The Arithmetic Unit (AU) of Fig. 2.2 is an analog multiplying/dividing block. The voltage
15
loop compensator is designed based on the amount of distortion introduced in the reference current
waveform due to the 100 Hz component that comes out in Verr. The voltage loop compensator is a
first order lag which attenuates the 100 Hz component in the feedback voltage within specified
limits. The pole of the first order lag is set below 100 Hz and the gain of the controller is adjusted
suitably to limit the 100 Hz component. For example, the pole of the controller can be placed at 10
Hz and the gain of the controller at 100 Hz is calculated for a specified harmonic distortion
introduced in the reference current waveform. The transfer function of the voltage loop
compensator, , is given byH2(s)
.....(2.21)H2(s) = K31+s.ωp
where is the gain of the compensator;K3
is the location of the pole;ωp(<< 100Hz)
Since the gain of the voltage loop controller at 100 Hz is very low, the overall bandwidth of
the system is low. Due to this the response of the DC bus voltage to load variations and source
variations is slow. (However, the bi-directional converter has a larger bandwidth as compared to
the front end converter and prevents the DC bus voltage from falling below its set voltage (as
covered in Chapter 3). This keeps the input voltage to the inverter constant within a specified lower
limit).
2.3.3 Output voltage regulation by feed forward of input voltage
The reference current to the current loop, Iref (Fig. 2.2), is generated from the output of the
bridge rectifier. This is multiplied by the voltage error to get the actual reference, . The mainsI∗
voltage can vary over a wide range as per the input voltage tolerance specification. Due to this, the
reference current, also changes. This in turn alters and hence the output voltage. Thus it isIref I∗
seen that there is a variation in the output voltage or the error voltage (which is proportional to the
output voltage under steady state) due to variations in the input mains voltage. (In the practical case,
the input voltage may vary as widely as 170 Volts to 270 Volt). The value of the current reference,
, is given byIref
16
.....(2.22)Iref = Vin G
where is the output of the bridge rectifier;Vin is the gain of the current reference generator;G
The closed loop transfer function from the reference, , to the actual current, isI∗ (s) iL(s)given by the expression
.....(2.23)iL(s)I∗ (s)
= F(s) = G1(s).H1(s)1 + G1(s).H1(s)
.....(2.24)⇒ iL(s) = F(s) I∗ (s)
.....(2.25)⇒ iL(s) = F(s) Verr G Vin
The power taken in from the mains is given by
.....(2.26)Pin(s) = Vin(s) iL(s) = F(s) Verr(s) G Vin2
The power given to the DC bus is given by
.....(2.27)Po(s) = VDC_bus(s) Io = VDC_bus(s) sC Vripple
where is the ripple in the DC bus;Vripple is the value of the DC bus capacitor;C
From Eq. (2.26) and (2.27), by power invariance,
.....(2.28)VDC_bus(s)
Verr(s)= F(s) G
sC VrippleVin
2
From Eq. (2.28), it is seen that the output voltage is dependent on the square of the
magnitude of the input voltage for a given error voltage, . This dependency of the outputVerrvoltage can be eliminated by dividing the reference current by the rms. value of the input voltage.
This is done by the feed forward block, , and the arithmetic unit, AU, shown in Fig. 2.2. TheHff(s)
block, , converts the input voltage into an equivalent DC voltage for the purpose of feedHff(s)
forward. is realised with a simple second order low pass filter. It provides adequateHff(s)
17
attenuation to the 100 Hz ac. A corner frequency of 10 Hz is chosen which is adequate for this
purpose.
The features of the front end converter were presented in this chapter. The model of the
converter in the average current controlled operation was derived. A suitable controller with the
following features was designed.
Inductor current programmed to be a rectified sinusoid
Output voltage regulation by feed back of the DC bus voltage
Output voltage regulation by feed forward of the input voltage
The design rules presented in this chapter were used to design the front end converter built
as a part of the 250 VA prototype UPS. A special purpose integrated circuit, UC 3854, from M/s
Unitrode Corporation was used to implement the controller .[4]
18
CHAPTER 3
THE BI-DIRECTIONAL CONVERTER
The need for a Bi-directional interface was discussed, in Chapter 1, Sec. 1.3. The[11]essential features of the interface converter are
High Input-To-Output Voltage Ratio
Bi-Directional Power Flow Capability
The high voltage transfer ratio constraint imposed on the converter is on account of the high
DC bus voltage (400 Volt) and low battery voltage (48 Volt). In this chapter, a variety of switched
mode power converters than can serve the purpose are suggested. A suitable choice is made based
on the practical limitations in operating conditions. The two modes of operation of the chosen
bi-directional converter and the various time intervals involved during power conversion are
explained in detail. The mathematical model of the converter is derived by the State Space
Averaging method. The low frequency small signal control transfer functions are derived around the
nominal operating point. Flux programmed control of switched mode power converters, a control
method similar to the instantaneous current programmed control, is presented. The model of the
converter in the flux programmed control is derived from the averaged state space model. The
design of the battery charge controller and the DC bus voltage controller are discussed. The two
controllers act on a priority basis which is resolved in the last section of the chapter.
3.1 Selection of topology
In this section, three converter topologies that meet the required specifications of the
bi-directional converter are discussed. The advantages and the practical problems associated with
each converter are mentioned and a choice is made based on the practical operating conditions, the
cost and size factor.
(a) Buck Converter :-
A Buck Converter can serve as a bi-directional converter if the switches used are capable
of carrying current in either directions. The circuit configuration of the buck converter and the circuit
implementation with switches suitable for bi-directional power flow are shown in Fig. 3.1.
S L
Battery
+Vdc +Vbatt
Q1
Q2
L
Fig 3.1 (a) A Bi-directional Buck Converter
Fig 3.1 (b) Circuit Implementation of Fig 3.1 (a)
DC bus
DC bus Battery
The converter shown in Fig. 3.1 operates in the 'Buck' mode when the input mains is
present, that is, when the DC bus is supplied from the front end converter. During this period the
battery is charged. It operates in the 'Boost' mode when the DC bus is supplied from the battery.
The ideal input-to-output voltage ratio (from the DC bus voltage ( ) to the battery voltageVDC_bus( )) under steady state operation is derived by applying volt-second balance on the inductor.VbattThe ideal voltage transfer ratio is given by
.....(3.1)Vbatt
VDC_bus= d
where is the duty ratio of the switch Q1d
From Eq. (3.1), it is seen that, in the Boost mode when the Battery is near deep discharge
level ( 40 Volt), the operating duty ratio of the switch Q1 is 0.1 (for 400Vbatt ≈ VDC_bus =
Volt). The circuit of Fig. 3.1(b) shows the ideal form of the Buck converter. The DC bus capacitor
(which is also the output capacitor of the front end converter) and the battery side filter circuit also
form a part of the practical circuit. To evaluate the steady state performance of the converter, these
filter components have to be taken into account along with their non-idealities. The circuit of Fig.
3.1(b) including the filter capacitors on either side along with the non-idealities (in the inductor and
the switches) is shown in Fig. 3.2.
20
+
Q1
+
RL
L
Resr1
C1R1R2
Resr2
C2
Vce1
Q2Vce2
BatteryDC bus
Fig 3.2 The Bidirectional Buck Converter with filter capacitorsand Non-idealities
Two modes of operation of the converter are identified as the 'Buck' and the 'Boost' modes.
The assumptions made are
The DC bus voltage remains constant in the Buck mode
The Battery voltage remains constant in the Boost mode
These assumptions eliminate the ESR of capacitor C2 in the Buck mode model and the ESR
of capacitor C1 in the Boost mode model. The steady state voltage transfer ratio from the DC bus
to the battery (Buck mode) is given by
.....(3.2)VbattVbus
= d1 − δVce1 − δVce2
(1−d)d
1+α
where α = RL/R1δVce1 = Vce1/VbusδVce2 = Vce2/Vbus
The steady state voltage transfer ratio from the Battery voltage to the DC bus voltage
(Boost mode operation) is given by
.....(3.3)VbusVbatt
= 1d
1 − (1−d)δVce1 − dδVce21+ α
d2
where α = RL/R2
21
δVce1 = Vce1/VbattδVce2 = Vce2/Vbatt
It is to be noted that the steady state voltage transfer ratio is affected only by the series
non-idealities, namely, the switch drops and the winding resistances . From Eqs. (3.2) and[6,7]
(3.3), the operating duty ratio of the switch Q1 can be calculated to be less than 0.1. The
operation of the switches in the converter at a very low duty ratio demands the use of faster
switches. Such operation results in peaky currents and the associated switching loss increases.
Further, operation at very low duty ratio implies power transfer through the switches only for a small
fraction of the switching cycle. This warrants the use of large filter components.
(b) Isolated Flyback Converter :-
An isolated flyback converter can serve as a bi-directional converter if the switches
used are capable of carrying current in either directions. The circuit configuration and the circuit
implementation of the isolated flyback bi-directional converter is shown in Fig. 3.3.
S
S'
DC bus
Batteryo
o
DC bus
Batteryo
o
Q1
Q2
Fig. 3.3 (a) Circuit configuration of Isolated flyback converter
Fig. 3.3 (b) Circuit implementation of Fig. 3.3 (a)
1:n
1:n
22
The converter shown in Fig. 3.3 charges the battery when the power to the DC bus comes
from the front end converter and supplies power to the DC bus in the absence of the input mains.
The ideal voltage transfer ratio (from the DC bus voltage ( ) to the battery voltage (VDC_bus Vbatt
)) of the converter is given by
.....(3.4)Vbatt
VDC_bus= n d
1−d
where is the turns ratio of the inductorn (< 1) is the operating duty ratio of Q1d
From Eq. (3.4), it is seen that in the isolated flyback converter, by varying the turns ratio of
the inductor, the operating duty ratio of the switches can be chosen to any desired value. This
enables switching at a higher frequency (even with slow switches) and hence reduced filter
component size and values. In the practical converter, the effect of the non-idealities is to reduce
the voltage transfer ratio (as in the case of the buck converter). In the flyback converter, the turns
ratio can be adjusted suitably to compensate for the reduction in the transfer ratio and still operate
the converter at the desired duty ratio. However, the size of the inductor used in the isolated
flyback converter is larger than that used in the buck converter. The filter capacitors used are also
larger than those used in the buck converter because the input and the output currents are
discontinuous.
(c) Boost converter with tapped inductor :-
The advantage in the buck converter is that the filter components are small. The
advantage in the flyback converter is that the operating duty ratio can be adjusted to be higher than
in the buck converter by adjusting the turns ratio of the inductor. These features can be merged to
get a converter whose operation is similar to the two converters in certain aspects. The resulting
converter is a tapped inductor boost converter. The circuit configuration and the circuit
implementation of the tapped inductor boost converter are shown in Fig. 3.4.
23
n:1L
S
S BatteryDC bus
n:1 L
BatteryDC bus
Q1
Q2
Fig. 3.4 (a) The bidirectional tapped inductor boost converter
Fig. 3.4 (b) Circuit implementation of Fig. 3.4 (a)
o o
o o
The steady state voltage transfer ratio of the converter from the DC bus voltage, VDC_busto the Battery voltage ( ) is given by Vbatt
.....(3.5)VbattVbus
= d1 + n(1−d)
where is the operating duty ratio of Q1d
is the turns ratio of the tapped inductorn
From Eq. (3.5) it is seen that the operating duty ratio of the switches can be chosen to any
desired value by altering the tap selection in the inductor. Larger the value of n, smaller is the ratio
of battery voltage to the DC bus voltage. Large values of n, result in larger ripple in the input and
output current waveforms. The selection of the inductor turns ratio is a compromise between the
least operating duty ratio that the switches can handle and the size of the filter components. In the
present case, the inductor tap is selected based on a nominal operating duty ratio of Q1 and the
filter components are calculated for this operating duty ratio.
24
Of the three converters presented in this section, the buck converter suffers from the
limitation in operating duty ratio. The flyback and the tapped inductor boost converter are well
suited for the application. The tapped inductor boost converter is selected for the present UPS,
based on the advantage that the size and the cost of the filter components used are comparatively
less.
3.2 Power Circuit and filter component selection :-
In this section, the ideal power circuit of the bi-directional converter (chosen in Sec. 3.1), is
presented. Two modes of operation of the converter, namely, the Buck mode and the Boost mode
are identified. The various intervals involved during the operation of the converter in the two modes
are explained in detail. The voltage transfer ratio of the ideal converter is derived based on the
volt-second balance on the inductor. The criteria for the selection of tap level in the inductor is
discussed. The filter components are selected based on the ripple allowed in the inductor current
and the two voltages (DC bus and battery). The practical non-idealities that are present are added
to the steady state model of the converter. The effect of these non-idealities on the voltage transfer
ratio is discussed.
3.2.1 The ideal power circuit of the bi-directional converter :-
The ideal power circuit of the bi-directional converter is shown in Fig. 3.5. The figure
shows two ideal voltage sources (namely, VDCbus and Vbatt), at the input and the output of the
converter.
oo
+_ +_
Fig. 3.5 The ideal power circuit of the bi-directional converter
VDCbus Vbatt
n:1
L1Q1
Q2L2
25
The switches are implemented using MOSFETs and Diodes. The practical circuit of the
bi-directional converter is shown in Fig. 3.6. As mentioned in Chapter 1, two modes of operation
of the converter are defined. When the power flow is from the DC bus to the battery, the battery
gets charged. This mode of operation is defined as the Buck mode. When the input Mains supply
is absent, the battery supplies power to the DC bus through the bi-directional converter. This mode
of operation is defined as the Boost mode. The circuits shown in Fig. 3.5 and Fig. 3.6 do not
indicate the presence of the filter capacitors or the battery choke which form a part of the practical
circuit. These components do not affect the steady state performance of the converter. They are
included in the dynamic model of the converter, which is presented in Sec. 3.3.
o o
+_ +_ VbattVDCbusQ1
Q2
n:1
L1
Fig. 3.6 The practical power circuit
L2
During the Buck mode operation, the input voltage to the converter (the same as the DC
bus voltage) is modelled as a constant voltage source. The battery is also indicated as a voltage
source. The battery takes some current during charging, which is modelled as a resistance across
26
o o
+_
o
+_
o
VDCbus
VbattL2
n:1
1:n
L2
Q1Q2
Q1Q2Vbatt
VDCbus
Fig. 3.7(a) The bi-directional converter in the BUCK mode
Fig. 3.7(b) The bi-directional converter in the BOOST mode
L1
L1
the battery. The equivalent circuit of the bi-directional converter during the Buck mode operation
is shown in Fig. 3.7(a). During the Boost mode operation, the battery is modelled as a constant
voltage source. In the Boost mode operation, the current taken by the inverter is supplied by the
bi-directional converter. This load is modelled as a resistance across the DC bus. The equivalent
circuit of the bi-directional converter during the Boost mode operation is shown in Fig. 3.7(b).
3.2.2 Operation of the converter in the two modes :-
(a) Buck mode :-
In the Buck mode, the power transfer is from the DC bus to the Battery. As mentioned
earlier, during this mode of operation, the DC bus is modelled as a constant voltage source. Two
intervals are identified within a switching period. It is assumed that the Battery voltage, Vbatt, does
not change within one switching period (TS).
In the first interval, the switch Q1 (Fig. 3.8(a)) is ON. During this interval, the voltage
across the inductor, L, is given by
.....(3.7)VLon = VDC_bus − Vbatt
where is the voltage across the inductor L during the ON time of Q1VLon is the DC bus voltageVDC_bus
is the Battery voltageVbatt
In the end of the first interval, the switch Q1 is turned OFF. Due to this, the current through
the inductor is interrupted. This results in a large voltage across the inductor. When the voltage
across the L2 winding of the inductor exceeds the Battery voltage, the freewheeling diode, D2
(across Q2) gets forward biased. The L1 winding of the inductor is open in the second interval. In
order to maintain the Ampere-Turns constant, the current through the L2 winding of the inductor
increases during the second interval (when the effective number of turns is less). The current paths
in the two intervals are highlighted in Fig. 3.8(a & b). The voltage across the L2 winding of the
inductor, is given byVL2off .....(3.8)VL2off = − Vbatt
27
From Eq. (3.8), the voltage across the inductor L, during the second interval, ( ) isVLoff
found out by using the turns ratio of the inductor and is given by
.....(3.9)VLoff = − Vbatt(1 + n)
where is the voltage across the inductor L when Q1 is offVLoff
is the turns ratio of the two windings in the inductorn =N1N2
is the number of turns in the L1 winding of the inductorN1 is the number of turns in the L2 winding of the inductorN2
o o o o
+_+_Q1
Q2Q1
Q2
n:1n:1
(a) (b)
Fig. 3.8 The current paths in the two intervals
Vbatt Vbatt
iL1 iL2
(Buck mode)
28
iL1
iL2
Fig. 3.9 Current through the two windings of the inductor
Q1ON
D2 ON
(Buck mode)
j1
j2
j2 = j1(1+n)
In the beginning of the next switching period, the switch Q1 is turned ON. This forces the
voltage across the inductor L as defined in Eq. (3.7). This voltage reverse biases the diode D2
which was freewheeling the current through L2 winding of the inductor. The current waveform
through the two windings of the inductor are shown in Fig. 3.9.
The duty ratio of operation of the converter is defined as(d)
.....(3.10)d = TonTs
where is the time for which the controlled switch is ON within one cycleTon is the switching periodTs
In the present converter, the controlled switch can be taken to be either Q1 or Q2. Q1 is
taken as the controlled switch and Q2 is turned ON whenever Q1 is OFF. (This is applicable even
in the Boost mode operation). The average voltage across the inductor over one cycle VL_avg
is given by
.....(3.11)VL_avg = d VLon Ts + (1 − d) VLoff Ts
where are defined in Eqs. (3.10), (3.9) and (3.7)d, VLoff, VLon
Under steady state, the average voltage across the inductor is zero. By substituting for
and in terms of the input and output voltages of the converter, the volt-secondVLon, VLoff d
balancing equation is given by
VDC_bus − Vbatt
d +
−Vbatt (1 − d)(1 + n) = 0
.....(3.12)⇒Vbatt
VDC_bus= d
1 + n(1−d)
Eq. (3.12) gives the steady state voltage transfer ratio from the DC bus voltage to the
Battery voltage.
29
(b) Boost mode :-
In the Boost mode, the power transfer is from the Battery to the DC bus. As mentioned
earlier, during this mode of operation, the Battery is modelled as a constant voltage source. As in
the Buck mode, two intervals are identified within a switching period. It is assumed that the DC bus
voltage, VDCbus, does not change within one switching period.
In the first interval, the switch Q2 (Fig. 3.10(a)) is ON. During this interval, the voltage
across L2 winding of the inductor, is given by
.....(3.13)VL2on = Vbatt
where is the voltage across L2 winding of the inductor when Q2 is ONVL2on
From Eq. (3.13), the voltage across the inductor L, during the first interval (Q2 is ON) is calculated
using the turns ratio of the inductor and is given by
.....(3.14)VLon = Vbatt (1 + n)
where is the voltage across the inductor when Q2 is ONVLon
In the end of the first interval, the switch Q2 is turned OFF. Due to this, the current through
the inductor is interrupted. This results in a large voltage across the inductor. When the voltage
30
Fig. 3.10 The current paths in the two intervals(Boost mode)
o
+_
o
1:n
L2Q1
Q2
VDCbus
L1o
+_
o
1:n
L2Q1
Q2
VDCbus
L1
(a) (b)
iL2 iL1
across the inductor L exceeds the DC bus voltage, the freewheeling diode D1 (across Q1) gets
forward biased. In order to maintain the Ampere-Turns constant, the current through the inductor
decreases during the second interval (when the effective number of turns is more). The current
paths in the two intervals are highlighted in Fig. 3.10(a & b). The voltage across the inductor, L,
during the second interval is given by
.....(3.15)VLoff = Vbatt − VDC_bus
where is the voltage across the inductor when Q2 is OFFVLoff
In the beginning of the next switching period, the switch Q2 is turned ON. This forces the
voltage across the inductor L as defined in Eq. (3.14). This voltage reverse biases the diode D1
which was freewheeling the current through the inductor. The current waveform through the two
windings of the inductor, in the Boost mode operation are shown in Fig. 3.11.
iL1
iL2
Fig. 3.11 Current through the two windings of the inductor
Q2ON D1 ON
(Boost mode)
j1
j2 j2 = j1(1+n)
The duty ratio of the converter is defined as in Eq. (3.10). The controlled switch is taken as
D1 (across Q1) as mentioned earlier. The average voltage across the inductor L, over one
switching period, VL_avg
.....(3.16)VL_avg = VLon (1 − d) Ts + VLoff d Ts
31
where are defined as in Eq. (3.10), (3.14) & (3.15)d ,VLon , VLoff
The average voltage across the inductor over one cycle is zero. By substituting for , d VLon and into Eq. (3.16), the volt-second balancing equation is given byVLoff
Vbatt (1 − d) (1 + n) + Vbatt − VDC_bus
d = 0
.....(3.17)⇒VDC_bus
Vbatt= 1 + n(1−d)
d
Eq. (3.17) gives the steady state voltage transfer ratio of the converter from the battery
voltage to the DC bus voltage. It is seen that, when the controlled switch is chosen to be the same
in the two modes of operation, the voltage transfer ratios turn out to be the same (Eq. (3.17) and
(3.12)). The variation of the gain of the converter from battery voltage to the DC bus voltage with
change in the duty ratio is shown in Fig. (3.12).
Fig. 3.12 Plot of Duty ratio VsGain
Gai
n
(for n = 2)
0 0.2 0.4 0.6 0.8 10
0.2
0.4
0.6
0.8
1
Duty ratio
The tap in the inductor causes the gain of the converter to reduce for a given duty ratio.
Higher the value of n, lesser the gain. The value of n is chosen based on the desired operating duty
ratio. The minimum gain required is 0.1 (when the DC bus voltage is 400 Volt and the battery
voltage is 40 Volt). For this gain and the desired operating duty ratio, the value of n is chosen by
using the relation of Eq. (3.12).
Note :- (1) One extreme case is n = 0. In this case, the converter reduces to a simple
buck converter where the plot of Duty ratio Vs Gain is linear.
32
(2) Higher the value of n, larger is the current step in the inductor
current waveform. (Fig. (3.9) & (3.11)).
3.2.3 Selection of filter components :-
The complete bi-directional power converter should include the DC bus capacitor and the
filter circuit for the battery. The circuit of Fig. 3.6 shows the basic converter. In practice, to realise
the two voltage sources, capacitors are used. The battery is connected to the low voltage end of
the converter through a battery choke. The bi-directional converter including these filter elements is
shown in Fig. 3.13.
As in conventional switched mode power converters, the inductor is chosen for a specified
ripple in the current through it and the capacitors are chosen based on the tolerable ripple in the
voltage across them.
+
o o
+
Fig. 3.13 The complete bi-directional converter
Battery
Battery choke
C2
C1R1 R2
Q1Q2
n:1
L1 L2
(showing the filter capacitors and the Battery choke)
L3
The converter has to handle maximum power in the Boost mode (that is, when the battery
supplies power to the DC bus). The maximum power output of the bi-directional converter,
is evaluated from the output power rating of the UPS. This is given by the relation,Pout_max
.....(3.18)Pout_max = PoINVeff
where is the rated output power of the UPSPo is the inverter efficiencyINVeff
33
The average output current, from the converter in the Boost mode, is then given byIo_avg
.....(3.19)Io_avg =Pout_maxVDC_bus
The peak value of the inductor current, (through the two windings, when Q1 is ON oriL_peak
D1 is freewheeling), is given by (refer Fig. (3.9) & (3.11))
.....(3.20)iL_peak =Io_avgdnom
+ ∆I2
where is the nominal operating duty ratiodnom
is the ripple in the inductor current∆I
The ripple in the inductor current is chosen to be a percentage of the inductor current∆I
during the interval (when both the windings of the inductor are carrying current). The inductordTs
current during is given by the first part in Eq. (3.20) (i.e., ). The value of thedTs Io_avg/dnom
inductor is chosen using the relation,
L ∆IdTs
= VDC_bus − Vbatt
.....(3.21)⇒ L =VDC_bus − Vbatt
∆Id Ts
The value of the inductance calculated using Eq. (3.21), along with the value of n chosen in
the previous section is used to design the inductor.
The minimum value of the DC bus capacitor (C1 of Fig. 3.13) required, is determined by
the tolerable ripple in the DC bus voltage. The DC bus capacitor has to supply the load current
(modelled as R1 in Fig. 3.13) for an interval (that is, when Q2 is ON or D2 is(1 − d)Tsfreewheeling). The capacitor is selected using the relation,
C1 ∆V1(1−d)Ts
= Io_avg
34
.....(3.22)⇒ C1 =Io_avg∆V1
(1 − d) Ts
where is the ripple allowed in the DC bus voltage ∆V1
(expressed as a percentage of the DC bus voltage)
Eq. (3.22) specifies the minimum value of C1 to be used. This equation does not consider
the ripple due to the Equivalent Series Resistance (ESR) of the capacitor. However, the DC bus
capacitor was chosen based on the hold up time requirement in Chapter 2. The design based on the
hold up time requirement suggests a higher value of C1 as compared to the value suggested by Eq.
(3.22). (This is because, C1 was selected to supply the continuous load current (same as )Io_avg
to the inverter for a few half-cycles). So, the value suggested in Chapter 2 is used.
The low voltage end capacitor (C2 in Fig. 3.13) is used along with the battery choke to limit
the battery current ripple. The capacitor C2 is selected to supply the maximum current through L2
winding of the inductor for a duration of . The ripple allowed in the capacitor voltage is(1 − d)Tschosen to be a percentage of the battery voltage. The peak current through the L2 winding of the
inductor is found using the relation,
.....(3.23)iL2_pk = iL_peak (1 + n)
where is defined in Eq. (3.20)iL_peak
The value of the average current through L2 winding of the inductor, during theIL2_avginterval is given by(1 − d)Ts
.....(3.24)IL2_avg = iL2_pk − ∆I2 (1+n)
where is defined in Eq. (3.20)∆I
The value of the capacitor C2 is chosen using the expression,
C2 ∆V2(1−d)Ts
= IL2_avg
35
.....(3.25)⇒ C2 =IL2_avg
∆V2(1 − d) Ts
where is the ripple allowed in the voltage across C2∆V2
(expressed as a percentage of the battery voltage)
The battery choke (L3 in Fig. 3.13) is chosen by assuming that the battery voltage is
constant. The maximum voltage that appears across L3 is given byVL3_max
.....(3.26)VL3_max = ∆V22
The value of L3 is chosen using the relation
L3∆Ibatt
(1−d)Ts= VL3_max
.....(3.27)⇒ L3 =VL3_max
∆Ibatt(1 − d)Ts
where is the ripple allowed in the battery current∆Ibatt(expressed as a percentage of the maximum battery current
in the Boost mode)
Note :- The maximum battery current in the Boost mode operation is given by
Ibatt =Po_maxCONVeff
where is given by Eq. (3.18)Po_max
is the efficiency of the bi-directional converterCONVeff
36
o o
+_ +_
VbattVDCbus
Q1Q2
n:1
L1 L2
RL1 RL2
Vce1
Vce2
Fig. 3.14 The bi-directional converter indicating the seriesnon-idealities
3.2.4 Practical non-idealities and their effect :-
The steady state model used so far, assumes that all the switches and filter elements are
ideal. For steady state analysis, the non-idealities to be considered are
ON state drop in the switches
Winding resistance of the inductor
The other non-idealities like switching delays and the ESR of the capacitors do not affect the
steady state gain of the converter . The circuit of the bi-directional converter with the series[6]non-idealities included is shown in Fig. 3.14.
The voltage across the inductor L when Q1 is ON in the Buck mode (or D1 is freewheeling in the
Boost mode) is given by
VLon = VDC_bus − Vce1 − iL1RL1 − iL2RL2 − Vbatt .....(3.28)
And the voltage across the L2 winding of the inductor when Q2 is ON in the Boost mode (or D2 is
freewheeling in the Buck mode) is given by
.....(3.29)VL2off = − iL2RL2 − Vce2 − Vbatt
The voltage across the inductor L during the period is derived by using Eq. (3.29) and the(1 − d)Tsturns ratio of the inductor and is given by
.....(3.30)VLoff = VL2off(1 + n)
Using the expressions for the voltage across the inductor in the two intervals, and applying
volt-second balance on the inductor over one switching period, the steady state gain of the
converter is derived as follows
VDC_bus − Vce1 − iL1RL1 − iL2RL2 − Vbatt
d
.....(3.31)+
− iL2RL2 − Vce2 − Vbatt (1 − d)(1 + n) = 0
37
where iL2 =Vbatt
R2
iL1 =Vbatt
R2d
1+n(1−d)
Substituting the expressions for the currents and simplifying Eq. (3.31) yields,
.....(3.32)Vbatt
VDC_bus= d
1+n(1−d)
1 − δVce1 − δVce2(1+n)(1−d)
d
1 + α1
d1+n(1−d)
2+ α2
where and δVce1 =Vce1
VDC_busδVce2 =
Vce2VDC_bus
and α1 =RL1R2
α2 =RL2R2
From Eq. (3.32), it is seen that the steady state gain of the converter reduces due to these
non-idealities. However, in the Buck mode operation, a lesser gain is always desired. In the Boost
mode operation, the values of and are expressed in terms of and . The steadyiL1 iL2 Vbatt R1
state gain of the converter, taking into account the series non-idealities, is derived (as in the Buck
mode) as
.....(3.33)VDC_bus
Vbatt= 1+n(1−d)
d
1 − εVce1
d1+n(1−d)
− εVce2
1 + β1 + β21+n(1−d)
d
2
where and εVce1 =Vce1Vbatt
εVce2 =Vce2Vbatt
and β1 =RL1R1
β2 =RL2R1
Eq. (3.33) shows that the effect of the non-idealities is to reduce the gain of the converter in
the Boost mode operation. The value of n is chosen appropriately to compensate for the reduction
in gain.
38
3.3 Dynamic model of the converter by state-space averaging :-
In this section, the dynamic performance of the bi-directional converter is[1,6, 7]presented. The behaviour of the bi-directional converter for small disturbances around the nominal
operating point is studied. This method of study (of the converter's small signal behaviour) is valid
only for low frequency disturbances. This constraint arises because the dynamic model of the
converter is derived by averaging the behaviour of the converter over one switching period. The
sequence of events involved in the circuit averaging technique is listed below[1,6]
The two modes of operation (namely, the Buck and the Boost modes) are treated separately
The structure of the converter in the various intervals within one switching period are identified
The switches are replaced by ideal transformers
The structure of the circuit in the various intervals are made identical by replacing the ideal
transformers by controlled voltage and current sources
The equivalent circuits of the various intervals are then averaged (This averaging method
imposes the low frequency validity restriction of the model)
Perturbations are allowed in the states of the system, the controlled voltage and current
sources and the control input (duty ratio of switch Q1 (Fig.3.6))
The second order disturbances are neglected for simplicity of analysis (This imposes the small
signal restriction in the validity of the model)
The steady state and the perturbation model are separated
The steady state performance and the response of the converter to perturbations (low
frequency & small signal) are derived by reducing the steady state and the perturbation
models. The equivalent circuits are reduced to simple LC circuits excited by voltage and
current sources.
The control transfer functions (which are used in the design of controllers) are derived from
the reduced equivalent circuits
Choice of the states in the converter :-
In the modelling of switched mode power converters, usually, the inductor current and the
output voltage of the converter are taken as the states of the system. In the present case, the
39
inductor current (in both the windings) is discontinuous in nature (Fig. 3.9 & 3.11). For the sake of
analysis, the flux, , in the magnetic circuit is taken as a state of the system. The other state of the[Φ]
system is the output voltage of the converter in the two modes (namely, the battery end voltage in
the Buck mode and the DC bus voltage in the Boost mode).
3.3.1 Dynamic model of the converter in the BUCK mode :-
The ideal circuit of the bi-directional converter is shown in Fig. 3.15. The equivalent circuit
model of the converter in the first interval, when Q1 is ON, is shown in Fig. 3.16(a). And the
equivalent circuit model of the converter in the second interval, when Q2 is ON, is shown in Fig.
3.16(b). The circuit model of the converter in the two intervals when the switches are replaced by
ideal transformers is shown in Fig. 3.17.
+
oo
VDCbus
Vbattn:1
L1 L2Q1
Q2
Fig. 3.15 The ideal circuit of the Bi-directional converter
C2R2
(Buck mode)
+ +VDCbus
VbattL
VDCbus
VbattL2
C2R2
C2R2
(a) (b)
Fig. 3.16 The circuit structure in the two intervals
Note :-
and L2 = L
(1+n)2N2 = N
(1+n)
where is the total number of turns in the two windingsN is the number of turns in the L2 winding of the inductorN2
40
+
+
Fig. 3.17(a) Equivalent circuit when Q1 is ON
Fig. 3.17(b) Equivalent cirucit when Q2 is ON
Note : The switches in Fig. 3.16 are replacedby ideal transformers
C2R2
Vbatt
VDCbus
L
L
C2R2VDCbus
1:N/L N/L:1
1:0 N(1+n)/L:1
The ideal transformers are then replaced by controlled sources. The equivalent circuit of the
converter in the first interval (Q1 is ON) with the ideal transformer (Fig. 3.17(a)) replaced by
controlled current and voltage sources is shown in Fig. 3.18(a). And the equivalent circuit of the
converter in the second interval (Q2 is ON) with similar replacement is shown in Fig. 3.18(b).
++--
+--
++--
+--
Fig. 3.18 Equivalent circuit showing controlled sources
(a)
(b)
L Vbatt
VDCbus
VDCbus
C2R2
R2C2
j1e1 e2
j2
j3 j4e3 e4
L
The values of the voltage and the current sources of Fig. 3.18 are given by
41
j1 = j2 = NΦL
; j3 = 0 and j4 = N(1+n)ΦL
e1 = VDC_bus ; e2 = Vbatt
e3 = 0 and e4 = (1 + n)Vbatt
The two circuits shown in Fig. 3.18 are averaged to get an equivalent low frequency circuit.
In the averaging process the elements of each circuit get multiplied by their corresponding duty ratio.
[For example, the current source j1 is valid for a duty ratio of d, and the source j2 is valid for a duty
ratio of (1-d). The average current source is then given by ].javg = j1.d + j2.(1 − d)
The averaged low frequency model of the converter is shown in Fig. 3.19.
++--
+--
L
VDCbus
Vbatt
R2C2
Fig. 3.19 The averaged low frequency equivalent circuit
j5e5 e6
j6
The values of the voltage and the current sources of Fig. 3.19 are given by
j5 = d.NΦL
and j6 = k.NΦL
e5 = d.VDC_bus and e6 = k.Vbatt
where k = 1 + n(1 − d)
In the circuit of Fig. 3.19, perturbations are possible in all the sources and the control input (the duty
ratio, d). The perturbations allowed are as follows.
VDC_bus = VDC_bus + v∼ DC_bus
Vbatt = Vbatt + v∼ battandΦ = ΦΦ + Φ∼
d = D + d∼
42
The expressions defining the sources in the equivalent circuit model of Fig. 3.19 are
non-linear. The presence of non-linear expressions for the sources introduces second order
perturbation terms. If the perturbations allowed are limited to infinitesimal values, then these
non-linear perturbation terms (second order terms) can be neglected. Since the perturbations
allowed are infinitesimal, the resulting model is a small signal model. The perturbed, low frequency,
small signal equivalent circuit model of the converter is shown in Fig. 3.20.
++--
+--
+--
+--
+--
+--
+--
Fig. 3.20 The low frequency small signal equivalent circuit modelof the converter
L
C2R2
e7
e8
e9
e10
e11
e12
e13
e14
Vbatt+vbatt
j7 j8
j9
j10 j11 j12
The values of the voltage and the current sources of Fig. 3.20 are given by
j7 = D.NL
.ΦΦ ; j8 = D.NL
.Φ∼ ; j9 = ΦΦ .NL
.d∼
j10 = K.NL
.ΦΦ ; j11 = K.NL
.Φ∼ ; j12 = ΦΦ .NL
.k∼
e7 = VDC_bus ; e8 = v∼ DC_bus
e9 = D.VDC_bus ; e10 = D.v∼ DC_bus
e11 = VDC_bus .d∼
; e12 = K.Vbatt
e13 = Vbatt.k∼
; e14 = K.v∼ batt
In the absence of perturbations, the circuit of Fig. 3.20 reduces to the steady state
equivalent circuit. The steady state part of the equivalent circuit is shown in Fig. 3.21.
43
++--
+--
e7j7 j10
e9 e12
L
R2C2
Fig. 3.21 The steady state equivalent circuit
Vbatt
The controlled sources of Fig. 3.21 can be replaced by equivalent ideal transformers (which
is the reverse process of what was done earlier). The DC model of the converter is shown in Fig.
3.22. The voltage source, e7, the capacitor C2 and the load resistor R2 are shifted to the other side
of the transformer to reduce the equivalent circuit to a simple RLC circuit excited by a constant
voltage source. The reduced circuit is shown in Fig. 3.23.
+
+
L
C2R2
R2 . K2
C2 / K2
L
D .
1:D K:1
e7
e7
Fig. 3.22 Circuit (of Fig. 3.21) with ideal transformers
Fig. 3.23 The DC model of the converter in the Buck mode
Vbatt
K . Vbatt
From Fig. 3.23, the steady state results of the converter are directly written as
and .....(3.34)Vbatt = DK
. VDC_bus
.....(3.35)ΦΦ = LN
. D
K2.
VDC_busR2
44
Around the steady state operating point, the perturbation model of the converter can be
derived from Fig. 3.20 by dropping the steady state quantities. The perturbation model of the
converter is shown in Fig. 3.24.
++--
+--
+--
+--
+--
L
e8j8 j9 j13 j12
e10
e11
e12
e14
C2R2
v batt
Fig. 3.24 The perturbed equivalent circuit
The two new sources introduced in Fig. 3.24 are obtained by reducing and are given byk∼
e14 = − n. Vbatt . d∼
and j13 = − n .NL
.Φ . d∼
The controlled sources of Fig. 3.24 can be replaced by equivalent ideal transformers (similar
to what was done for the DC model). The AC model of the converter is shown in Fig. 3.25. The
voltage source, e8, the current sources j8, j9, j11 and j12 , the capacitor C2 and the load resistor
R2 are shifted to the other side of the corresponding transformers and the equivalent circuit is
45
+
+ -
+--
++--
- + + -
L
e8 j9e11 e14
j13
C2R2
1:D K:1
Fig. 3.25 Circuit (of Fig. 3.24) with ideal transformers
Fig. 3.26 The AC model of the converter in the Buck mode
L
R2 . K2
C2 / K2
P1
W1P2
K . vbatt
vbatt
reduced to a simple RLC circuit excited by a voltage source and a current source. The reduced
circuit is shown in Fig. 3.26.
The reduced circuit of Fig. 3.26 has simple voltage and current sources exciting an RLC circuit.
The values of the sources (by reduction) are given by
P1 =(1+n)
KVDC_bus
1 − s LD n
R2K2 (1+n)
. d
∼
P2 = D . v∼ DC_bus
W1 =(1+n)
K3
VDC_busR2
.d∼
From the AC model equivalent circuit of Fig. 3.26, the small signal, low frequency control
transfer functions from the duty ratio (the control input) to the states of the system are derived. The
control transfer functions are used in Sec. 3.4 and 3.5 for the design of the controller. The control
transfer functions are derived as follows.K . v∼ batt
P1= 1
1 + s L
R2 .K2+ s2 L .C2
K2
⇒ v∼ battd∼ =
(1+n) VDC_bus
K2
1 − s L nD
R2K2 (1+n)
1 + s L
R2 .K2+ s2 . L.C2
K2
.....(3.36)
Φ∼
P1=
LN
1
R2 .K2
1 + s .R2 . C2
1 + s L
R2 . K2+ s2 . L. C2
K2
⇒ Φ∼
d∼ =
VDC_bus . L
N.(1+n+n.D)
R2 .K3
1 + s .C2 . R2(1+n)
(1+n+n.D)
1 + s L
R2 .K2+ S2. L.C2
K2
.....(3.37)
46
Eqs. (3.36) & (3.37) give the small signal low frequency transfer functions of the
bi-directional converter in the Buck mode operation with duty ratio programmed control. Eq.
(3.36) gives the transfer function from duty ratio to output voltage (battery voltage in the Buck
mode) and Eq. (3.37) gives the transfer function from duty ratio to the flux in the core.
3.3.2 Dynamic model of the converter in the BOOST mode :-
The dynamic model of the bi-directional converter in the Boost mode is derived using the
same guidelines as in the Buck mode. The ideal circuit of the bi-directional converter in the Boost
mode operation is shown in Fig.3.27. The DC and the AC equivalent circuits of the perturbed
model are shown in Fig. 3.28. The governing control transfer functions are presented here. The
steady state performance equations are also presented for the sake of completeness.
47
+
oo
1:n
Q2
Q1
C1R1Vbatt
VDCbus
L2 L1
Fig. 3.27 The ideal circuit of the converter in the Boost mode
+
+
+ -
+--
L
C1 / D
2R1 . D2
Vbatt . K
VDCbus . D
Fig. 3.28(a) The DC model of the converter in the Boost mode
L
C1 / D2
2R1 . D
P1
P2
W1
vDC_bus
Fig. 3.28(b) The AC model of the converter in the Boost mode
The expressions for the voltage and the current sources indicated in Fig. 3.28 as P1, P2 and W1
are given by
P1 = K . v∼ batt
P2 = VDC_bus + n.Vbatt
− s . N ΦΦ
D . d
∼
W1 =
Vbatt . (1+n)
R1. D3
. d
∼
The expressions of the state variables in the steady state (obtained from Fig. 3.28(a), DC
model) are
.....(3.38)VDC_bus = KD
. Vbatt
.....(3.39)ΦΦ = LN
. K
D2.Vbatt
R1
where K = 1 + n. (1 − D)
Note :- The duty ratio of the converter in the Boost mode is defined the same way as in the Buck
mode. The controlled switch in either mode is Q1.
Eqs. (3.38) & (3.39) give the steady state performance expressions for the ideal
bi-directional converter operating in the Boost mode. The small signal low frequency control
transfer functions of the converter from duty ratio to the state variables (from Fig. 3.28(b), AC
model) are given by
v∼ DC_bus
d∼ = − Vbatt .
(1+n)
D2
.
1 − s . L. K
R1. D2 . (1+n)
1 + s . L
R1 . D2+ s2 . LC1
D2
.....(3.40)
48
Φ∼
d∼ = − Vbatt .
LN
.
1+ n+ K
R1. D3
.
1 + s . R1.C1.(1+n)
(1+n+K)
1 + s . L
R1 . D2+ s2 . L. C1
D2
.....(3.41)
Note :- The negative signs that are present in the two control transfer functions indicate that both the
state variables decrease with increase in duty ratio. This is a consequence of defining the duty ratio
of the converter with respect to the ON time of switch Q1 in either mode of operation.
The control transfer functions derived in this section is used in the design of the controller.
The inner variable, namely the flux in the core, is controlled by instantaneous programming. This
method is similar to instantaneous current programming method. The operation of the inner flux loop
is explained in Sec. 3.4. The model of the converter in the instantaneous flux programmed control is
derived. This model is used for the design of the two voltage loop compensators. The analysis of
the transfer functions in the duty ratio programmed control and flux programmed control is done in
Sec. 3.5.
3.4 Dynamic model of the converter in the flux programmed mode of operation :-
In this section, the method of control employed in the bi-directional converter is explained.
The structure of the controller is studied. The operation of instantaneous flux programmed control is
presented. The steady state and the dynamic performance of the control scheme is presented. The
dynamic model of the converter in the flux programmed control is different from the duty ratio
programmed control. The dynamic model of the converter in the new control scheme is presented.
This model is used to design the voltage loop compensators.
The block diagram of the converter along with the controller structure is shown in Fig. 3.29.
A generalised power converter is shown. The instantaneous programming of the inner state
variable, namely the flux in the magnetic core, is explained below.
49
Power converter
Flux
VDCbus
Vbatt
H1(s)
H2(s)
+
+
+
- -
-
Clock
PriorityResolver
SR
Q
Fig. 3.29 The block diagram of the converter & the controller
v
DC_busref
battref
v
The flux programmed control scheme is similar to the instantaneous current programmed
control . The model derived in Sec. 3.3 assumes that the control input to the converter is the[1]duty ratio of the controlled switch. The duty ratio is derived by comparing the control voltage (that
is, the output of the controller) with a fixed frequency ramp. In constant frequency flux programmed
control, the turn ON instants of the controlled switch are clocked periodically. The turn OFF
instants are determined by the time at which the flux in the magnetic core reaches a threshold value
determined by the control signal (that is, the output of the controller). In the present case, the
threshold value is the output of the Priority resolver (Fig. 3.29). The figure shows a clock which
sets a flip-flop once in a switching period. The instantaneous value of the flux in the magnetic core
(which is one of the outputs available from the converter model) is compared with the flux reference
(or the control voltage) generated by the Priority resolver. When the flux in the core exceeds the
50
Set(of flip flop)
Reset(of flip flop)
Flux inthe core
Instantaneous
Reference
Fig. 3.30 The sequence of events
flux reference, the flip-flop is reset. The timing diagram showing the sequence of events in the
system is presented in Fig. 3.30.
The advantages of this instantaneous flux programming scheme are
Protection from overloads
Ease of parallel operation of converters
Elimination of flux from the list of state variables of the system (This is explained later in this
section)
These advantages come at the cost of a disadvantage. The local feedback of flux in the
control scheme introduces sub-harmonic instability when the operating duty ratio of the controlled
switch exceeds 0.5. ( Similar to the sub-harmonic instability in instantaneous current programming).
This is explained in . Since the operating duty ratio of the controlled switch is chosen to be[1,6]0.25 in the present case, the problem of sub-harmonic instability does not arise. Hence it is not
explained in this thesis.
3.4.1 Model of the flux programmed control scheme :-[1,6]
The small signal model of the converter has already been developed based on the duty ratio
programmed control in Sec. 3.3. These results can be used for the design of the controller,
provided the flux programmed control is related to an equivalent duty ratio programmed control
scheme. The essence of the situation is to express the operating duty ratio in terms of the average
value of flux, the reference flux and the input and output voltages of the converter. The
instantaneous flux waveform and the reference waveform are shown in Fig. 3.31.
51
Mag
nit
ud
e
t0
d.Ts (1-d).Ts
Reference
Instantaneous
m1
Fig. 3.31 Time Vs flux
Average
The relationship between the instantaneous and the reference flux waveform is given by the
expression,
.....(3.42)Φ + m1 .d .Ts
2= Φ∗
where is the average fluxΦ is the flux referenceΦ∗
is the positive slope of the instantaneous flux waveformm1 is one switching cycle periodTs
The DC and the small signal relations are found by allowing perturbations around a nominal
operating point. The perturbed variables are given by
Φ = ΦΦ + Φ∼
d = D + d∼
m1 = M1 + m∼ 1
Φ∗ = ΦΦ ∗∗ + Φ∼ ∗
Applying these perturbations to the variables in Eq. (3.42), the DC and the AC solutions of the flux
programming (Duty ratio expressed in terms of the other quantities) are given by
.....(3.43)D = (ΦΦ ∗∗ − ΦΦ ) . 2M1 . Ts
.....(3.44)d∼
= 2M1 .Ts
(Φ∼ ∗ − Φ∼ ) − DM1
.m∼ 1
52
Note :- The model of the flux programmed control is different in the two modes of operation
because, the source and the output voltages in the two modes are different. So, the value of M1
that is applicable in the two modes (though the same) are expressed in different forms. Due to this,
the two modes of operation have to be dealt with separately.
3.4.2 Model of the converter :-
The DC and the AC model control scheme (given in Eq. (3.43) and Eq. (3.44)) are
substituted in the averaged state space model of the converter to obtain the dynamic model of the
converter operating in the flux programmed control scheme. The averaged state space model for
the two modes of operation is given below. The low frequency small signal averaged state space
model of the converter for the Buck mode operation can be written directly from the equivalent
circuit of the perturbed model presented in Fig. (3.24). The state space model (Buck mode) is
given by the following equation.
dΦ∼
dtdv∼ batt
dt
=
0 − KN
K .NL.C2
− 1R2 . C2
.
Φ∼
v∼ batt
+
DN0
. v∼ DC_bus
.....(3.45)+
VDC_busN
. 1 + D . n
K
−n. D .VDC_bus
K2 .R2 .C2
. d∼
The corresponding equation for the Boost mode operation can be written from the
equivalent circuit of its perturbed model . The state space model (Boost mode) is given by the
following equation.
dΦ∼
dtdv∼ DC_bus
dt
=
0 − DN
D .NL.C1
− 1R1 . C1
.
Φ∼
v∼ DC_bus
+
KN0
. v∼ batt
.....(3.46)+
−Vbatt
N.
1+nD
K . Vbatt
D2 .R2 .C2
. d
∼
53
Buck mode operation :-
The slope m1 is given by
.....(3.47)m1 =VDC_bus − Vbatt
N
and in the buck mode. Allowing perturbations asVbatt = VDC_bus . dk
mentioned earlier, after simplification, the expressions for are given byM1 and m∼ 1
M1 =VDC_bus
N K. (1 + n) . (1 − D) ; m∼ 1 =
v∼ DC_bus − v∼ battN
.....(3.48)
Substituting Eq. (3.43) and Eq. (3.48) into Eq. (3.44), the small signal expression for duty
ratio in terms of the other quantities is obtained (for the Buck mode). This expression is given by
d∼
= 2 N KVDC_bus (1+n) (1−d) Ts
. (Φ∼ ∗ − Φ∼ ) −D .K .
v∼ DC_bus − v∼ batt
VDC_bus (1+n) (1−d)
.....(3.49)
Substituting for from Eq. (3.49) into Eq. (3.45), the control variable is eliminated fromd∼
d∼
the expression and the flux reference is introduced as the new control variable. The new stateΦ∼ ∗
space model of the converter in the flux programmed control scheme (in Buck mode) is then given
by (after simplification)
.....(3.50)
dΦ∼
dtdv∼ batt
dt
= A.
Φ∼
v∼ batt
+ b .v∼ DC_bus + f. Φ∼ ∗
where A =
α1 α2α3 α4
54
where α1 = − 2(1−D)Ts
α2 = − KN
1 − D
K (1−D)
α3 = KNLC2
1 + 2nD L
K2 R2 (1+n) (1−d )Ts
α4 = − 1R2C2
1 + nD2
K(1+n) (1−d)
f =
2(1−D) Ts
− 2 nN DKR2C2 (1+n) (1−d) Ts
From Eq. (3.50) the small signal transfer functions from the control variable to the stateΦ∼ ∗
variables can be found using the expressionx(s)
.....(3.51)x(s)
Φ∼ ∗(s)= (s I − A)−1 . f
After simplification, the approximate transfer functions are given by
.....(3.52)Φ∼ (s)Φ∼ ∗(s)
= 1 + n+ n. D
1+ n .
1 + s .
R2C2 (1+n)(1 + n+ n. D)
(1+ s .R2 C2) 1 + s .
(1−D)2 fs
.....(3.53)v∼ batt(s)
Φ∼ ∗(s)= K .N . R2
L.
1 − s . nL D
K2 R2 (1+n)
(1+ s .R2 C2) 1 + s .
(1−D)2 fs
These transfer functions are used in the design of the battery charge controller, in Fig.H1(s)
3.29. The design of this charge controller is presented in Sec. 3.5.
55
Boost mode operation :-
The reference flux in the Boost mode is opposite to that in the Buck mode. So, the sign of
the reference and the actual flux change in the Boost mode. The DC and the AC solutions given in
Eq. (3.43) and Eq. (3.44) become
.....(3.54)D = − (ΦΦ ∗ − ΦΦ ) . 2M1 . Ts
.....(3.55)d∼
= − 2M1 .Ts
. (Φ∼ ∗ − Φ∼ ) − DM1
.m∼ 1
The slope m1 (Fig. 3.31) is given by Eq. (3.47). Since the role of the DC bus voltage and the
Battery voltage in the Boost mode operation, the slope m1 is expressed in a different form as,
.....(3.56)m1 =Vbatt
N. kd
Allowing perturbations as before, the expressions for are given byM1 and m∼ 1
.....(3.57)M1 =Vbatt
N. (1+n) (1−D)
D
.....(3.58)m∼ 1 =v∼ DC_bus − v∼ batt
N
Substituting Eq. (3.57), Eq. (3.58) and Eq. (3.54) into Eq. (3.55) gives the small signal
expression for duty ratio in terms of the other quantities. This expression is given by
d∼
= − 2N DVbatt (1+n) (1−d)Ts
. (Φ∼ ∗ − Φ∼ ) −D 2 .
v∼ DC_bus − v∼ batt
Vbatt (1+n) (1−d)
.....(3.59)
As in the case of the Buck mode operation, the expression for is substituted in Eq. (3.46).d∼
This eliminates the duty ratio as a control variable and introduces the flux reference as the newΦ∼ ∗
control variable. This gives the small signal state space model (similar to Eq. 3.50). Using Eq.
56
(3.51), the two control transfer functions are obtained. The control transfer functions from the flux
reference to the state variables are given below.
.....(3.60)Φ∼ (s)Φ∼ ∗(s)
= 1 + n+ K
1+ n .
1+ s .
R1C1 (1+n)(1 + n+ K)
(1 + s . R1C1) 1+ s .
(1−D)2 fs
v∼ DC_bus(s)
Φ∼ ∗(s)= − N .R1 . D
L.
1− s . KL
R1 .D2 . (1+n)
(1+ s . R1C1)1+ s .
(1−D)2 fs
.....(3.61)
These transfer functions are used in the design of the DC bus voltage controller, ofH2(s)
Fig. (3.29). The design of this controller is presented in Sec. 3.5.
Note :-
It is observed that under flux programmed control, the poles in the low frequency small
signal control transfer functions (which were complex conjugate pair as seen from Eq. (3.36),
(3.37), (3.40) and (3.41)) break into real poles. However, the RHP zero remains undisturbed in all
the transfer functions. The bode plot of the transfer functions (duty ratio programmed control and
flux programmed control) are analysed in Sec. 3.5 where the design of the voltage loop controller is
done with the help of these bode plots.
For control purposes, the transfer function (of Eq. 3.61) with the sign dropped is used,
since, the boost mode of operation enters into the picture when power flows backward from the
battery to the DC bus. This is equivalent to a change of convention in the direction of flux (and its
reference).
57
3.5 Design of Voltage loop controller :-
In this section, the design of the voltage loop controller, (Fig. 3.29) isH1(s) and H2(s)
explained. Each compensator generates a flux reference for the inner flux loop. The battery charge
controller, , generates a flux reference which is proportional to the error in the low endH1(s)voltage (same as battery voltage under steady state) with respect to the reference voltage, .Vbattref The DC bus voltage controller, , generates a flux reference which is proportional to the errorH2(s)in the DC bus voltage with respect to the reference voltage, . Out of these two fluxVDC_busref
references generated by the voltage loop controller, higher priority should be given to the reference
generated by the DC bus voltage controller. This is resolved in the Priority Resolver (Fig. 3.29).
For the design of voltage loop controller, the model of the converter in flux programmed
control (which was derived in Sec. 3.4) is used. The important expressions are given by Eq. (3.52),
(3.53), (3.60) and (3.61). These expressions give the low frequency small signal control transfer
functions from the flux reference to the state variables in the two modes of operation. The
asymptotic bode plot of these transfer functions (both duty ratio programmed control and flux
programmed control) are given in Fig. 3.32. (These control transfer functions are identified by the
names given in the Figures).
log (f)
log (f)
log (f)
log (f)
Gai
n (d
B)
Ph
ase
-90o
0
Fig. 3.32(a) Bode plot of Eq. (3.36) Fig. 3.32(b) Bode plot of Eq. (3.52)(Buck mode, duty ratio control) (Buck mode, flux control)
(From control variable to average flux in the core)
G1(s) G5(s)
58
log (f)
log (f)
log (f)
log (f)
Gai
n (d
B)
Ph
ase
-90o
0
Fig. 3.32(c) Bode plot of Eq. (3.37) Fig. 3.32(d) Bode plot of Eq. (3.53)(Buck mode, duty ratio control) (Buck mode, flux control)
(From control variable to output (Battery) voltage)
-180
-270
o
o
G2(s) G6(s)
log (f)
log (f)
log (f)
log (f)
Gai
n (d
B)
Ph
ase
o
0
Fig. 3.32(e) Bode plot of Eq. (3.40) Fig. 3.32(f) Bode plot of Eq. (3.60)(Boost mode, duty ratio control) (Boost mode, flux control)
(From control variable to average flux in the core)
-180
-270o
G3(s) G7(s)
log (f)
log (f)
log (f)
log (f)
Gai
n (d
B)
Ph
ase
-180o
0
Fig. 3.32(g) Bode plot of Eq. (3.41) Fig. 3.32(h) Bode plot of Eq. (3.61)(Boost mode, duty ratio control) (Boost mode, flux control)
(From control variable to output (DC bus) voltage)
0
-90
o
o
-270o
G4(s) G8(s)(sign is dropped)
59
3.5.1 Battery charge controller :-
The block diagram of the model of the converter along with the battery charge controller is
shown in Fig. 3.33. The primary function of the battery charge controller is to regulate the battery
voltage. When the battery voltage is very low, the charging current taken by the battery (if the
terminal voltage is kept constant) is large. To avoid this, the current allowed during charging is
limited to 10% of the Ampere-hour rating of the battery (20% in the case of quick charging). So,
the battery is charged with constant current till the terminal voltage rises to the battery reference
voltage. After this the voltage across the terminals is maintained constant. The current limit is
implemented by limiting the flux in the core when the converter is operating in the Buck mode. This
is done by limiting the flux reference given to the inner loop (Fig. 3.33).
Fig. 3.33 Block diagram of the converter and the controller(Buck mode)
G6(s)H1(s)+
- PriorityResolver
Vbattvbattref (Fig. 3.32(d))
flux ref1
The asymptotic bode plot of is shown in Fig. 3.32(d). The expression for isG6(s) G6(s)given by Eq. (3.53). To obtain zero steady state error in the battery voltage, , a PI controllerVbatt is used. By adjusting the gain, of the PI controller, the bandwidth of the battery voltage loop isK1adjusted. The transfer function of the PI controller, is given byH1(s)
.....(3.62)H1(s) = K1 .
1 + s
ωpi
sωpi
The open loop gain of the converter (in the flux programmed mode of operation) and the battery
charge controller put together is given by
G6(s) . H1(s) = K1 .
1+ s
ωpi
sωpi
. K . N .R2L
.
1− s . nLD
K2 R2 (1+n)
(1+ s .R2C2) 1+ s .
(1−D)2 fs
60
The asymptotic bode plot of the open loop transfer function is given in Fig. 3.34. The zero of the PI
controller is set before the first pole of the control transfer function . For a desired[5] G6(s)
bandwidth (or response time), the gain of the PI controller is selected by setting
.....(3.63)G6(s) . H1(s) @ s= ωdesired
= 1
log (f)
log (f)-90
o
0
-180
-270
o
o
G6(s)
log (f)
log (f)
-90o
0
-180
-270
o
o
G6(s).H1(s)
Gai
n (d
B)
Ph
ase
H1(s)
Fig. 3.34 Bode plot of G6(s) . H1(s)
(a) G6(s) and H1(s) (b) G6(s).H1(s)
Note :- The arrows indicate the variation of bandwidth with variation in the gain of the PI(↔)
controller.
3.5.2 DC bus voltage controller :-
The block diagram of the model of the converter along with the DC bus voltage controller is
shown in Fig. 3.35. The function of the DC bus voltage controller is to regulate the DC bus voltage.
Fig. 3.35 Block diagram of the converter and the controller(Boost mode)
G8(s)H2(s)+
- PriorityResolver
VDCbusvDC_busref (Fig. 3.32(h))
From H1(s)
flux ref2
61
The asymptotic bode plot of is shown in Fig. 3.32(h). The expression for is givenG8(s)by Eq. (3.61). To obtain zero steady state error in the DC bus voltage, , a PI controllerVDC_busis used. By adjusting the gain, of the PI controller, the bandwidth of the battery voltage loop isK2adjusted. The transfer function of the PI controller, is given byH2(s)
.....(3.64)H2(s) = K2 .
1 + s
ωpi
sωpi
The open loop gain of the converter (in the flux programmed mode of operation) and the DC bus
voltage controller put together is given by
G8(s) . H2(s) = − K2 .
1 + s
ωpi
sωpi
. N . R1 .DL
.
1− s . K L
R1 .D2 . (1+n)
(1+ s .R1 C1)1+ s .
(1−D)2 fs
The asymptotic bode plot of the open loop transfer function is given in Fig. 3.36. The zero of the PI
controller is set before the first pole of the control transfer function . For a desired bandwidthG8(s)
(or response time), the gain of the PI controller is selected by setting
.....(3.65)G8(s) . H2(s) @ s= ωdesired
= 1
62
log (f)
log (f)
0
G8(s)
log (f)
log (f)
0
0
-90
o
G8(s).H2(s)H2(s)
Fig. 3.36 Bode plot of G8(s) . H2(s)
(a) G8(s) and H2(s) (b) G8(s).H2(s)
o
o-180
-270o
Phase
Gain(dB)
Note :- The arrows indicate the variation of bandwidth with variation in the gain of the PI(↔)
controller.
3.5.3 Seamless transfer of power flow direction :-
The control of the two end voltages, namely , is done by the twoVDC_bus and Vbattcontrollers . These two controllers generate flux references for the inner loop.H2(s) and H1(s)
The polarity of the two references are opposite. This is because, to regulate the two end voltages
the required direction of power flow is different. This is reflected in the control transfer function for
the Boost mode as a negative sign (Eq. (3.41) and (3.61)). Specifically, the value of flux_ref1 (Fig.
3.33) is positive and the value of flux_ref2 (Fig. 3.35) is negative. (The polarity will change if the
controlled switch were Q2 instead of Q1).
Out of the two references generated, flux_ref2 is given higher priority since the DC bus
voltage is more critical than the battery voltage. The priority resolver (Fig. 3.29) does the job of
selecting the lesser of the two references thereby giving higher priority to the DC bus voltage
controller. The block diagram of the priority resolver is shown in Fig. 3.37. The mathematical
model of the priority resolver is given by its output expression, which is
.....(3.66)flux_ref = min (flux_ref1 , flux_ref2)
63
flux_ref1
flux_ref2flux_ref
Fig. 3.37 The block diagram of the priority resolver
PriorityResolver
(Note :- If the controlled switch were Q2, then the priority resolver should select the greater of the
two references to accomplish the job).
This chapter presented the bi-directional (interface) converter. The available converters that
can serve the purpose were listed. A choice based on the practical operating conditions, cost and
size was made. The mathematical model of the converter was derived by circuit averaging. The
controller structure was explained. The model of the converter in the flux programmed control
mode was derived. Two voltage loop compensators were designed to control the DC bus voltage
and the battery voltage. A priority resolver was introduced in the controller structure to select the
flux reference based on the operating condition. These design rules were used to construct the
bi-directional converter built as a part of the 250 VA prototype.
64
CHAPTER 4
THE INVERTER
This chapter presents the features of the inverter. The operation of a single phase inverter,
the switching strategy used (in the prototype UPS) and the mathematical model of the inverter are
discussed. The design of an output filter to attenuate the switching harmonics is discussed in detail.
The inverter is operated in open loop. The features of the inverter are,
Transformerless operation (Operation from a high DC bus voltage)
Sinusoidal output waveform
4.1 Power circuit
The inverter operates from a high voltage DC bus and does not employ any step up
transformer at its output, as discussed in chapter 1. The relationship between the DC bus voltage
and the inverter output voltage when Sine triangle Pulse Width ModulationVDC_bus
Vout
(SPWM) technique (explained in Sec. 4.2, ) is employed is given by[8]
.....(4.1)Vout =ma VDC_bus
2
where is the amplitude modulation index (defined in Eq. (4.2));ma
is the DC bus voltage;VDC_bus
The power circuit of the single phase inverter, which is a circuit implementation of the
configuration shown in Fig. 1.3, is shown in Fig. 4.1.
L
C LoadVdc
Fig. 4.1 The Inverter power circuit
Q1
Q2 Q3
Q4
ab
The switches are implemented using MOSFETs. Several Pulse Width Modulation (PWM)
techniques are available to get sinusoidal output from the inverter. The output pattern from the
inverter, employing such modulation techniques, contains the fundamental frequency and harmonics
in the vicinity of the switching frequency and/or its multiples. The harmonics can be attenuated
within desired limits by using passive filters implemented using LC networks (Fig. 4.1). The
switching frequency of the inverter (the frequency of the carrier wave) is selected based on the
audible noise considerations. (Silent operation is desired in most systems). A switching frequency
of kHz, apart from the fundamental frequency which is the same as the line frequency, has the firstfs
harmonic around (or its multiples depending on the PWM technique adopted). A switchingfs
frequency of 20 kHz is chosen so that the first harmonic above the fundamental frequency is above
the audible range. In Sec. 4.2, the switching strategy used (in the prototype inverter) is presented
and the harmonic content in the output pattern is evaluated. In Sec. 4.3, design of a suitable filter
based on the harmonic content in the inverter output pattern is presented.
4.2 Switching strategy
The inverter used in the proposed system employs unipolar sinusoidal pulse width
modulation technique (SPWM). In this technique, two sinusoidal signals which are out of phase by
180o with respect to each other are compared with a triangular signal. This gives two different
66
0 1 2 3 4 5 6
-1
-0.8
-0.6
-0.4
-0.2
0
0 . 2
0 . 4
0 . 6
0 . 8
1
F ig . 4 . 2 ( a ) Re fe rence S igna l s used f o r PWM pa t t e rn gene ra t i on
patterns corresponding to the two sinusoidal signals. These patterns are used to switch the left and
the right arms of the inverter. The reference sinusoidal and triangular signals and the patterns
generated by comparing the reference signals are shown in Fig. 4.2.
0 1 2 3 4 5 6- 0 . 2
0
0 .2
0 .4
0 .6
0 .8
1
F i g . 4 . 2 ( b ) S w i t c h i n g p a t t e r n 1
0 1 2 3 4 5 6- 0 . 2
0
0 .2
0 .4
0 .6
0 .8
1
F i g . 4 . 2 ( c ) S w i t c h i n g P a t t e r n 2
67
0 1 2 3 4 5 6
-1
- 0 . 8
- 0 . 6
- 0 . 4
- 0 . 2
0
0 . 2
0 . 4
0 . 6
0 . 8
1
F ig . 4 .2 (d ) I nve r te r ou tpu t pa t te rn
Fig. (4.2a) shows the two sinusoidal reference waveform and the triangular carrier
waveform. The amplitude modulation index and the frequency modulation index of thema mf
PWM technique are defined as
.....(4.2)ma =VspVtp
where is the peak-to-peak value of the sinusoidal wave;Vsp
is the peak-to-peak value of the triangular wave;Vtp
.....(4.3)mf =ftriangle
fsin
where is the frequency of the triangle wave;ftriangle is the frequency of the sinusoidal wave;fsin
The patterns of Fig. (4.2 b & c) are derived from the reference waveform and the triangular
waveform with the following logic:
then and Q1 is ON .....(4.4a)Vsin1 > Vtriangle patt1 = 1
68
then and Q2 is ON .....(4.4b)Vsin1 < Vtriangle patt1 = 0
then and Q3 is ON .....(4.4c)Vsin2 > Vtriangle patt2 = 1
then and Q4 is ON .....(4.4d)Vsin2 < Vtriangle patt2 = 0
Eq. (4.4a) & (4.4b) result in left arm switching pattern of Fig. 4.2(b) and Eq. (4.4c) &
(4.4d) result in right arm switching pattern of Fig. (4.2c). Fig. (4.2d) shows the output pattern from
the inverter as observed between points a and b. It is seen that when both the upper or the lower
switches are turned on simultaneously, the output current circulates in a loop through a MOSFET
and a freewheeling diode. During this interval the current drawn from the DC bus is zero. Since the
output pattern from the inverter switches either between and or between and0 +VDC_bus 0
in the two half cycles of the reference waves, this technique is called the unipolar pulse−VDC_buswidth modulation technique.
0.2
0.4
0.6
0.8
1.0
1 mf 2mf
(2mf-1) (2mf+1)
3mf
VonVdc
Fig. (4.3) Harmonic content in the unipolar SPWM pattern
The harmonic spectrum of the output voltage waveform (of Fig. 4.2d) is shown in Fig. (4.3)
for an even frequency modulation index . The left and the right arm switching patterns aremf
displaced by 180o of the fundamental frequency (of the sinusoidal wave) with respect to each other.
This results in the cancellation of the switching frequency component and components around it
when is even. (If the switching frequency is very large compared to the fundamental frequency,mf
then the harmonics around the switching frequency are negligible). Similarly, the harmonics around
thrice the switching frequency also cancel out. The peak of the output voltage at the fundamental
frequency (of the sinusoidal wave) is given by
.....(4.5)V01 = ma VDC_bus
69
The total harmonic distortion (THD) in the inverter output voltage, expressed as a[8]percentage of the fundamental magnitude, is around 40%. The output filter has to reduce the THD
in the output voltage within the specified limits (taken as in the present case).≤ 4%
4.3 Filter design
The output filter is constructed using a passive LC network (Fig. 4.1). The design of the
inductor and the capacitor is done based on the harmonic content in the inverter output and the load
current requirement. The transfer function of the LC network and the load shown in Fig. 4.1 is
given by
.....(4.6)Vo(s)
Vinv(s)= 1
1 + sLR
+ s2LC
where is the voltage across the load;Vo(s)
is the output voltage from the inverter;Vinv(s)
The filter has a complex pole pair at the resonant frequency of the LC network beyond
which there is an attenuation of -40 dB/decade with increase in frequency. The switching harmonics
and its multiples are assumed to be present around the switching frequency for the design of the
filter. The required attenuation on the output voltage pattern, is given byattnreqd
.....(4.7)attnreqd =THDpresentTHDdesired
In the present case, the required attenuation is around 10 (from 40% to 4%) . The corner
frequency of the filter, is selected using the relationfLC
attnreqd = k2fsfLC
.....(4.8)⇒ fLC =2fs k
attnreqdwhere is the order of the filter (2 in the present case)k
Note :- accounts for the harmonics present around twice the switching 2fsfrequency in the unipolar SPWM technique;
70
The characteristic impedance, of the output filter is equated to the load resistance R.L/C
This ensures that the per unit voltage drop in the inductor is the same as the per unit current drain in
the capacitor. The of the filter network and the load is given byQ
.....(4.9)Q = RL/C
In the present case, is chosen as 1. (If better open loop regulation is desired, then a ofQ Q
2 or more may be selected). From Eqs. (4.8) & (4.9), the value of L and C is designed for a given
switching frequency and output power (or the load resistance).
4.4 Model of the inverter
The inverter is operated in open loop. The corner frequency of the output filter is at least
one order of magnitude above the fundamental frequency . Hence the attenuation offs >> fsin
the fundamental component due to the presence of the filter is neglected. The control transfer
function of the inverter from the control signal, (which in this case is the sinusoidal reference,Vc(s)
) , to the output voltage is given byVsin(s)
.....(4.10)Vo(s)Vsin(s)
= G 1
1 + sLR
+ s2LC
where is the gain of the inverter;G =VDC_busVtriangle
12
is the rms. value of the output voltage;Vo(s)
This transfer function is of importance if closed loop control of the output voltage is desired.
For frequencies much below the corner frequency of the filter, the inverter is modelled as a simple
gain element with gain .G
Issues regarding the inverter used in the prototype UPS were discussed in this chapter. The
design relations presented here were used to design the output filter which was used in the inverter
built as a part of the 250 VA prototype UPS.
71
CHAPTER 5
SIMULATION AND PERFORMANCE EVALUATION RESULTS
A prototype UPS rated for 250 VA was built, as mentioned in Chapter 1, to evaluate the
performance of the design. The design of power circuit elements and the implementation of
controllers for the different converters were based on the design rules derived in Chapters 2, 3 and
4. The same design rules were used to construct the simulation model which was simulated using
SIMULINK, a platform in MATLAB. The specifications of the prototype UPS is summarised
below.
Input voltage (nominal) : 230 Volt
Input voltage tolerance : 170 - 270 Volt
Battery voltage (nominal) : 48 Volt
(56.4 Volt float)
Battery capacity : 9 Ah (10 hour rating)
Back up time : 30 minute (approximate)
Output voltage : 230 Volt
Total harmonic distortion (THD)
in the output voltage waveform : ≤ 5%
Output power : 250 VA
Front End
ConverterInverter
Bi-directional
Converter
Source 1(Mains)
Load
Source 2 (Battery)
Fig. 5.1 Arrangement of the various converters to form the 250 VA UPS
This chapter presents the dynamic results of the simulation model and the steady state and
dynamic results for the performance evaluation tests carried out on the prototype UPS. The
arrangement of the various converters in the 250 VA prototype UPS is shown in Fig. 5.1. The
steady state test results of the system along with the test setup used are discussed below.
(1) Bi-directional converter :-
The load regulation test on the bi-directional converter is performed without the front end
converter and the inverter. The load is applied directly on the DC bus. The results of the test are
given in Table 5.3 (page 106). The test setup for the load regulation test on the bi-directional
converter is shown in Fig. 5.2 (Test setup1). The steady state current waveforms in the two
windings of the tapped inductor are given in pages 103 & 104.
Bi-directionalConverter
Fig. 5.2 Test setup1
Load
+Battery
+VDCbus
(2) Bi-directional converter + Inverter :-
The load regulation test on the bi-directional converter and the inverter put together, is
performed without the front end converter. The load is applied at the output of the inverter. The
results of the test are given in Table 5.4 (page 107). The test setup for the load regulation test on
the bi-directional converter & the inverter is shown in Fig. 5.3 (Test setup2).
74
Bi-directionalConverter
Fig. 5.3 Test setup2
LoadInverter
Battery+
+VDCbus
(3) Front end converter :-
The load and the source regulation tests on the front end converter are performed without
the bi-directional converter and the inverter. The load is applied directly on the DC bus. The
results of the test are given in Table 5.2 (page 105). The test setup for the load and source
regulation tests on the front end converter is shown in Fig. 5.4 (Test setup3).
Front EndConverter Load
SinglePhaseMains
Fig. 5.4 Test setup3
(4) Front end converter + Bi-directional converter + Inverter :-
The load and the source regulation tests are done, on all the three converters put together,
to evaluate the performance of the UPS when the Mains supplies power. The load is applied at the
output of the inverter. The results of the tests are given in Table 5.5 (pages 108 & 109). The test
75
Bi-directionalConverter
Fig. 5.5 Test setup4
LoadInverter
Battery
+
+
Front endConverter
SinglePhaseMains
The Battery is chargingduring this test
setup for the load & source regulation tests on the overall system is shown in Fig. 5.5 (Test setup4).
The battery is charging during this test.
The steady state results of the prototype system are presented in graphical form for easy
interpretation, in the pages 110, 111 & 112.
Dynamic performance results ( from Simulation and from the Prototype system) :-
The block diagram of the dynamic performance evaluation test setup is given Fig. 5.6. The
organisation of the dynamic performance results presented in the following pages, is summarised in
Table 5.1. The switch conditions are indicated for the various tests.
50% Loads
Inverter
Sw1
SinglePhaseSource
Front EndConverter
BidirectionalConverter
+
+ Sw3
Sw2
Fig. 5.6 Block diagram of the prototype test set up
Battery
Vi
Note :- An up-arrow " " indicates the turn ON of a switch and a down-arrow " " indicates the turn↑ ↓OFF of a switch.
Table 5.1. Organisation of the dynamic test and simulation results
Sl.No. Test
Test Condition
SwitchConditions
Results inthe page
Sw1 Sw2 Sw3
Simulation Results
S1 Step change in load (on the inverter) from Noload to 50% of the rated load
Vi = 230Volt
1 ↑ 0 79 & 80
S2 Step change in load (on the inverter) from50% to 100% of the rated load
Vi = 230Volt
1 1 ↑ 81 & 82
S3 Step change in load (on the inverter) from100% to 50% of the rated load
Vi = 230Volt
1 1 ↓ 83 & 84
S4 Step change in load (on the inverter) from50% of the rated load to No load
Vi = 230Volt
1 ↓ 0 85 & 86
S5 Mains failure with 50% load on the inverter ----- ↓ 1 0 87 & 88
76
S6 Mains coming back with 50% load on theinverter
----- ↑ 1 0 89 & 90
S7 Mains failure with 100% load on the inverter ----- ↓ 1 1 91 & 92
S8 Mains coming back with 100% load on theinverter
----- ↑ 1 1 93 & 94
S9 Step change in load (on the inverter) from Noload to 50% of the rated load
Vi = 0 0 ↑ 0 95 & 96
S10 Step change in load (on the inverter) from50% to 100% of the rated load
Vi = 0 0 1 ↑ 97 & 98
S11 Step change in load (on the inverter) from100% to 50% of the rated load
Vi = 0 0 1 ↓ 99 & 100
S12 Step change in load (on the inverter) from50% of the rated load to No load
Vi = 0 0 ↓ 0 101 & 102
Performance Evaluation test Results
T1 Step change in load (on the inverter) from Noload to 50% of the rated load
Vi = 230Volt
1 ↑ 0 113 & 114
T2 Step change in load (on the inverter) from50% to 100% of the rated load
Vi = 230Volt
1 1 ↑ 115
T3 Step change in load (on the inverter) from100% to 50% of the rated load
Vi = 230Volt
1 1 ↓ 116
T4 Step change in load (on the inverter) from50% of the rated load to No load
Vi = 230Volt
1 ↓ 0 117 & 118
T5 Mains failure with 50% load on the inverter ----- ↓ 1 0 119 & 120
T6 Mains coming back with 50% load on theinverter
----- ↑ 1 0 121 & 122
T7 Mains failure with 100% load on the inverter ----- ↓ 1 1 123 & 124
T8 Mains coming back with 100% load on theinverter
----- ↑ 1 1 125 & 126
T9 Step change in load (on the inverter) from Noload to 50% of the rated load
Vi = 0 0 ↑ 0 127 & 128
T10a Step change in load (on the inverter) from50% to 100% of the rated load
Vi = 0 0 1 ↑ 129 & 130
T11 Step change in load (on the inverter) from100% to 50% of the rated load
Vi = 0 0 1 ↓ 131 & 132
T12 Step change in load (on the inverter) from50% of the rated load to No load
Vi = 0 0 ↓ 0 133 & 134
T10b Step change in load (on the inverter) from50% to 100% of the rated load
Vi = 0 0 1 ↑ 135
77
Note :- (1) The variables that are presented in all the dynamic test results are :
(a) Mains input current
(b) DC bus voltage
(c) Battery current
(d) Output voltage
(2) Items T10a and T10b present the results of two tests with the same operating
conditions. Practically the load switches Sw2 and Sw3 (Fig. 5.1) were not synchronised with the
output voltage of the inverter. The response of the output filter in the inverter depends on the point
of switching of these switches. This causes the output voltage waveform to dip, during a step
increase in the load when the output voltage is not zero. The two results show two different point on
wave switching conditions.
(3) In the simulation results, the current through the inductor in the front end converter
(referred as the Boost inductor current in the following pages) is presented instead of the Mains
input current. In the experimental results, the Mains input current is shown.
(4) The battery current in the simulation results, (whenever the battery is supplying
power to the load) has a 100Hz component and follows a pattern close to a rectified sinusoid
(example : item T10a, page 130). But in the performance evaluation results, the battery current is
steady, containing the switching ripple alone (example : item T2, page 115). This is because the
bandwidth of the DC bus voltage controller in the simulation model was higher than the bandwidth in
the prototype.
78
Plots showing the Boost inductor current and the DC bus voltage waveforms during a stepchange in load (on the inverter) from 10% to 50% of the rated load. The Mains supply is presentand the battery is getting charged.
79
Plots showing the Battery current and the Output voltage waveforms during a step change inload (on the inverter) from 10% to 50% of the rated load. The inverter loaded from 10% of therated load, is an approximation to No load.
80
Plots showing the Boost inductor current and the DC bus voltage waveforms during a stepchange in load (on the inverter) from 50% to 100% of the rated load. The Mains supply is presentand the battery is getting charged.
81
Plots showing the Battery current and the Output voltage waveforms during a step change inload (on the inverter) from 50% to 100% of the rated load.
82
Plots showing the Boost inductor current and the DC bus voltage waveforms during a stepchange in the load (on the inverter) from 100% to 50% of the rated load. The Mains supply ispresent and the battery is getting charged.
83
Plots showing the Battery current and the Output voltage waveforms during a step change inthe load (on the inverter) from 100% to 50% of the rated load.
84
Plots showing the Boost inductor current and the DC bus voltage waveforms during a stepchange in the load (on the inverter) from 50% of the rated load to No load. The Mains supply ispresent and the battery is getting charged.
85
Plots showing the Battery current and the Output voltage waveforms during a step change inthe load (on the inverter) from 50% of the rated load to No load.
86
Plots showing the Boost inductor current and the DC bus voltage waveforms during Mainssupply failure. The load on the inverter is 50% of the rated load.
87
Plots showing the Battery current and the Output voltage waveforms during Mains failure. The load on the inverter is 50% of the rated load.
88
Plots showing the Boost inductor current and the DC bus voltage waveforms when theMains supply comes back. The load on the inverter is 50% of the rated load.
89
Plots showing the Battery current and the Output voltage waveforms when the Mains supplycomes back. The load on the inverter is 50% of the rated load.
90
Plots showing the Boost inductor current and the DC bus voltage waveforms during Mainssupply failure. The load on the inverter is 100% of the rated load.
91
Plots showing the Battery current and the Output voltage waveforms during Mains supplyfailure. The load on the inverter is 100% of the rated load.
92
Plots showing the Boost inductor current and the DC bus voltage waveforms when theMains supply comes back. The load on the inverter is 100% of the rated load.
93
Plots showing the Battery current and the Output voltage waveforms when the Mains supplycomes back. The load on the inverter is 100% of the rated load.
94
Plots showing the DC bus voltage and the Output voltage waveforms during a step changein load (on the inverter) from 10% to 50% of the rated load. The Mains supply is absent and thepower is supplied by the Battery.
95
Plot showing the Battery current waveform during a step change in load (on the inverter)from 10% to 50% of the rated load. The 10% of the rated load on the inverter is an approximationto No load.
96
Plots showing the DC bus voltage and the Output voltage waveforms during a step changein load (on the inverter) from 50% to 100% of the rated load. The Mains supply is absent and thepower is supplied by the Battery.
97
Plot showing the Battery current waveform during a step change in load (on the inverter)from 50% to 100% of the rated load.
98
Plots showing the Boost inductor current and the DC bus voltage waveforms during a stepchange in the load (on the inverter) from 100% to 50% of the rated load. The Mains supply isabsent and the power is supplied by the Battery.
99
Plots showing the Battery current and the Output voltage waveforms during a step change inthe load (on the inverter) from 100% to 50% of the rated load.
100
Plots showing the Boost inductor current and the DC bus voltage waveforms during a stepchange in the load (on the inverter) from 50% of the rated load to No load. The Mains supply isabsent and the power is supplied by the Battery.
101
Plots showing the Battery current and the Output voltage waveforms during a step change inthe load (on the inverter) from 50% of the rated load to No load.
102
Current waveform through the two windings of the tapped inductor in the bi-directionalconverter, when the converter is operating on No load.
103
104
Table 5.2 Load and Source regulation test results of the front end converter
Input Voltage(Volt)
Input current(Ampere)
OutputVoltage
(Volt)
OutputCurrent(Ampere)
Efficiency %
170200220240270
<0.05- do -- do -- do -- do -
399.2399.2399.3399.5399.5
No
Load-----
170200220240270
0.30.30.30.250.2
397.6397.7397.9398.0398.2
0.10.10.10.10.1
77.9866.2860.2566.3373.74
170200220240270
0.630.550.50.50.45
396.1396.3396.4396.6397.0
0.20.20.20.20.2
73.9672.0572.0766.1065.34
170200220240270
0.880.750.70.650.6
394.6394.9395.2395.5395.7
0.30.30.30.30.3
81.7681.6179.5578.5975.72
170200220240270
1.251.060.980.910.85
393.0393.3393.6393.8394.1
0.450.450.450.450.45
83.2283.4882.1581.1477.27
170200220240270
1.621.361.251.151.05
391.0391.6392.0392.5392.8
0.60.60.60.60.6
85.1886.3885.5285.3283.13
170200220240270
2.021.681.521.421.38
389.0389.7390.2390.7391.0
0.750.750.750.750.75
84.9586.9887.5185.9878.7
105
Table 5.3 Load regulation test results of the Bidirectional Converter
BatteryVoltage (Volt)
BatteryCurrent(Ampere)
DC busVoltage (Volt)
Load Current(Ampere)
Output Power(Watt)
Efficiency%
46.5 0.18 381 0 NO LOAD -----
46.3 0.85 380 0.07 26.6 67.7
46.17 1.1 380 0.1 38 74.82
45.97 1.5 379 0.15 56.85 82.44
45.77 2 379 0.2 75.8 82.8
45.56 2.55 379 0.25 94.75 81.56
45.29 3.1 379 0.3 113.7 80.98
43.8 3.75 379 0.35 132.65 80.76
43.6 4.4 379 0.4 151.6 79.02
43.4 5.05 379 0.45 170.55 77.82
43.7 5.6 379 0.5 189.5 77.6
45.2 5.95 378 0.55 207.9 77.3
44.3 6.75 378 0.6 226.8 75.84
43.65 7.6 378 0.65 245.7 74.06
43.25 8.4 377 0.7 263.9 73.51
42.7 8.75 376 0.73 272.6 72.96
106
Tab
le 5
.4 L
oad
regu
latio
n te
st r
esul
ts o
f th
e U
PS
with
the
batte
ry s
uppl
ying
pow
er
Bat
tery
Vol
tage
(Vol
t)
Bat
tery
Cur
rent
(Am
pere
)
DC
bus
Vol
tage
(Vol
t)
DC
bus
Cur
rent
(Am
pere
)
Out
put
Vot
lage
(Vol
t)
Out
put
Cur
rent
(Am
pere
)
Out
put
Pow
er(W
att)
Eff
icie
ncy
ofB
idir
. Con
v.(%
)
Eff
icie
ncy
ofIn
vert
er(%
)
Eff
icie
ncy
from
Bat
tery
to L
oad
(%)
48.3
0.45
381
0.02
230
0N
o L
oad
----
---
---
----
-
48.2
81.
0538
10.
123
00.
1526
.475
.16
69.3
52
47.4
1.6
381
0.17
223
0.26
50.2
82.9
79.8
666
.2
46.9
12.
2538
10.
2321
90.
3975
83.0
285
.59
71.0
6
46.8
3.2
380
0.32
218
0.58
108.
481
.289
.14
72.3
8
46.1
73.
8538
00.
3821
60.
6412
580
.17
87.7
270
.32
46.2
64.
838
00.
4621
80.
7515
3.6
78.7
287
.87
69.2
45.8
5.65
380
0.53
214
0.86
175.
577
.83
87.1
467
.8
45.8
6.55
380
0.6
212
0.96
200
7687
.71
66.7
45.2
7.6
378
0.68
211
1.08
225
74.3
88.1
865
.52
44.8
38.
737
50.
7620
71.
2125
073
.187
.71
64.1
1
107
Tab
le 5
.5 L
oad
and
sour
ce r
egul
atio
n te
st r
esul
ts w
ith th
e M
ains
sup
plyi
ng P
ower
No
load
pow
er ta
ken
from
the
Mai
ns w
hen
the
inve
rter i
s sw
itche
d O
FF a
nd th
e ba
ttery
is c
harg
ed th
roug
h th
ebi
dire
ctio
nal c
onve
rter
=53
.9 V
A(B
atte
ry v
olta
ge =
55.
01 V
olt)
(Bat
tery
cur
rent
= -0
.35
Am
pere
)
Inpu
tV
olta
ge(V
olt)
Inpu
tC
urre
nt(A
mpe
re)
DC
bus
Vol
tage
(Vol
t)
DC
bus
Cur
rent
(Am
pere
)
Out
put
Vol
tage
(Vol
t)
Out
put
Pow
er
(Wat
t)
Eff
icie
ncy
ofF
ront
End
Con
v. (%
)
Eff
icie
ncy
ofIn
vert
er(%
)
Eff
icie
ncy
from
Mai
nsto
Loa
d (%
)
230
0.16
402
0.01
240
No
Loa
d--
---
----
---
---
170
200
230
270
0.32
50.
30.
275
0.27
5
399
399
399
399
0.08
0.08
0.08
0.08
234
233
233
233
25.3
25.3
25.3
25.3
57.8
53.2
50.5
42.9
8
79.2
679
.26
79.2
679
.26
45.8
42.2
40.0
34.1
170
200
230
270
0.49
0.43
0.40
0.36
398
398
398
399
0.14
50.
145
0.14
50.
145
229
229
230
230
50.1
50.1
50.1
50.2
69.3
67.1
62.7
59.5
86.8
86.8
86.8
86.8
60.2
58.2
54.4
51.6
170
200
230
270
0.67
50.
590.
540.
49
396
396
396
397
0.21
0.21
50.
215
0.21
5
226
226
227
228
75.6
75.6
75.6
76.2
72.5
72.2
68.6
64.5
90.9
88.8
88.8
89.3
65.9
64.1
60.9
57.6
170
200
230
270
0.87
50.
790.
675
0.6
396
396
397
396
0.28
50.
285
0.28
50.
285
224
225
225
226
100.
910
1.0
101.
610
1.8
75.9
71.4
72.9
69.7
89.4
89.5
89.8
90.2
67.9
63.9
65.5
62.5
108
Inpu
tV
olta
ge(V
olt)
Inpu
tC
urre
nt(A
mpe
re)
DC
bus
Vol
tage
(Vol
t)
DC
bus
Cur
rent
(Am
pere
)
Out
put
Vol
tage
(Vol
t)
Out
put
Pow
er
(Wat
t)
Eff
icie
ncy
ofF
ront
End
Con
v. (%
)
Eff
icie
ncy
ofIn
vert
er(%
)
Eff
icie
ncy
from
Mai
nsto
Loa
d (%
)
170
200
230
270
1.07
50.
910.
820.
72
395
395
395
396
0.35
0.35
0.35
0.35
220
220
220
220
1125
.212
5.1
125.
212
5.2
75.6
76.0
73.3
71.3
90.6
90.5
90.6
90.5
68.5
68.8
66.4
64.5
170
200
230
270
1.27
51.
100.
975
0.87
394
395
395
395
0.41
0.41
0.41
0.41
219
220
220
221
149.
115
0.0
150.
215
0.4
74.5
73.6
72.2
68.9
92.3
92.6
92.7
92.9
68.8
68.2
66.9
64.0
170
200
230
270
1.47
51.
271.
13 1.0
394
394
394
395
0.47
50.
475
0.47
50.
480
216
216
216
217
175.
317
5.5
176.
117
6.4
74.6
73.7
72.0
70.2
93.7
93.8
94.1
93.0
69.9
69.1
67.8
65.3
170
200
230
270
1.65
1.42
1.25
1.10
392
394
394
394
0.53
50.
535
0.53
50.
535
213
214
214
215
199
200
200
202
74.8
74.2
73.3
70.9
7
94.9
94.9
94.9
95.8
71.0
70.4
69.4
68.0
170
200
230
270
1.93
1.65
1.50
1.34
393
394
394
394
0.59
50.
595
0.59
50.
595
213
213
213
213
226
226
226
227
71.3
71.0
67.9
64.8
96.9
96.6
96.6
96.8
69.1
68.6
65.6
62.7
170
200
230
270
2.08
1.85
1.67
51.
475
393
393
393
393
0.66
0.65
0.66
0.66
209
209
209
210
250
250
250
253
73.3
69.0
67.3
65.1
96.4
97.9
96.4
97.5
70.7
67.6
64.9
63.5
109
The first plot summarises the steady state performance of the front end converter. (Anominal input voltage of 230 Volt was maintained throughout the test). The second plot gives thesteady state performance of the bi-directional converter.
110
The two plots summarise the performance of the overall system when the Mains supply ispresent. (A nominal input voltage of 230 Volt was maintained). It is to be noted that the Battery isgetting charged during this test.
111
The two plots summarise the performance of the overall system when the Mains supply isabsent and the battery supplies power to the system.
112
Plots showing the Battery current and the DC bus voltage waveforms during a step changein the load (on the inverter) from No load to 50% of the rated load.
113
Plots showing the Mains input current and the Output voltage waveforms during a stepchange in load (on the inverter) from 50% of the rated load to No load. The battery is gettingcharged.
114
Plots showing the Mains input current and the Output voltage waveforms during a stepchange in load (on the inverter) from 50% to 100% of the rated load. The battery is getting chargedduring this period.
115
Plots showing the Mains input current and the Output voltage waveforms during a stepchange in load (on the inverter) from 100% to 50% of the rated load. The battery is getting chargedduring this period.
116
Plots showing the Battery current and the DC bus voltage waveforms during a step changein the load (on the inverter) from 50% of the rated load to No load.
117
Plots showing the Mains input current and the Output voltage waveforms during a stepchange in load (on the inverter) from No load to 50% of the rated load. The battery is gettingcharged.
118
Plots showing the Mains input current and the Output voltage waveforms during Mainsfailure with 50% load on the inverter.
119
Plots showing the Battery current and the DC bus voltage waveforms during Mains failure.The load on the inverter is 50% of the rated load.
120
Plots showing the Mains input current and the Output voltage waveforms when the Mainssupply comes back. The load on the inverter is 50% of the rated load.
121
Plots showing the Battery current and the DC bus voltage waveforms when the Mainssupply comes back. The load on the inverter is 50% of the rated load.
122
Plots showing the Mains input current and the Output voltage waveforms during Mainssupply failure with 100% load on the inverter.
123
Plots showing the Battery current and the DC bus voltage waveforms during Mains failure.The load on the inverter is 100% of the rated load.
124
Plots showing the Mains input current and the Output voltage waveforms when the Mainssupply comes back. The load on the inverter is 100% of the rated load.
125
Plots showing the Battery current and the DC bus voltage waveforms when the Mainscomes back. The load on the inverter is 100% of the rated load.
126
Plots showing the Battery current and the Output voltage waveforms during a step change in the load (on the inverter) from No load to 50% of the rated load. The battery is supplying power.
127
Plots showing the Battery current and the DC bus voltage waveforms during a step change in the load (on the inverter) from No load to 50% of the rated load. The battery is supplying power.
128
Plots showing the Battery current and the Output voltage waveforms during a step change inload (on the inverter) from 50% to 100% of the rated load. The Mains supply is absent and thepower is supplied by the Battery.
129
Plots showing the Battery current and the DC bus voltage waveforms during a step changein load (on the inverter) from 50% to 100% of the rated load. The Mains supply is absent and thepower is supplied by the Battery.
130
Plots showing the Battery current and the Output voltage waveforms during a step change inload (on the inverter) from 100% to 50% of the rated load. The Mains supply is absent and theBattery is supplying power.
131
Plots showing the Battery current and the DC bus voltage waveforms during a step changein load (on the inverter) from 100% to 50% of the rated load. The Mains supply is absent and thebattery is supplying power.
132
Plots showing the Battery current and the Output voltage waveforms during a step change in the load (on the inverter) from 50% of the rated load to No load. The battery is supplying power.
133
Plots showing the Battery current and the DC bus voltage waveforms during a step change in the load (on the inverter) from 50% of the rated load to No load. The battery is supplying power.
134
Plots showing the Battery current and the Output voltage waveforms during a step change inthe load (on the inverter) from 50% to 100% of the rated load. The Mains supply is absent and thepower is supplied by the Battery.
135
CHAPTER 6 CONCLUSION
The primary motivation for this work is the development of a light weight, low cost, compact
Uninterruptible Power Supply (UPS) suited for low power loads. The desired features suggested
that the line frequency magnetic components, which account for 30% of the cost and 50% of the
weight and volume in the conventional systems, be eliminated from the circuit.
.
The thesis covered the design and the development of a transfermerless UPS. A circuit
configuration was proposed for a transformerless UPS. The various converters in the UPS were
studied separately. The design of the power circuit and the control laws governing the operation of
the converters were discussed in the various chapters. The main features of the developed UPS are
Transformerless design
Unity power factor at the input
Low harmonic distortion in the input current
Less battery component count
Sinusoidal output voltage waveform
The transformerless operation forced the use of a high voltage DC bus. Cost considerations
kept the battery voltage low. This prompted the necessity of an interface between the high voltage
DC bus and the battery. This interface must be capable of handling power flow in either direction to
enable battery charging.
The front end converter was implemented using a bridge rectifier and a boost circuit. The
current through the inductor in the boost circuit was programmed to be a rectified sinusoid. This
made the current drawn from the Mains sinusoidal. The front end converter supplies power to the
DC bus. The DC bus voltage was regulated by controlling the magnitude of the current through the
inductor. The shape of the current reference was taken from the output of the rectifier. Since the
input voltage to the UPS can vary, the current reference generated varied. This affects the DC bus
voltage regulation. This problem was overcome by feeding forward the magnitude information of
the input mains voltage appropriately.
Three converters that can potentially serve the purpose of the bi-directional interface were
presented. A suitable converter among them was chosen based on the practical operating
considerations and the cost & size of the filter components. The principle of operation and the
sequence of events involved in the process of power conversion was understood. The mathematical
model of the converter was derived by the circuit averaging technique. Instantaneous flux
programming technique, a control method similar to the instantaneous current programming
technique was used to control the converter. The operation and the mathematical model of the
converter in the instantaneous flux programmed control scheme was presented. The objective of the
controller is to regulate the battery charge and the DC bus voltage. This was achieved by using
suitable compensators.
The inverter operates directly from the high voltage DC bus. The switching strategy used to
get a sinusoidal output voltage waveform was presented. The harmonic content in the switching
pattern was analysed. This information was used to design the output filter. The model of the
inverter was presented.
The theoretical design methods developed in the thesis were verified by constructing a
prototype UPS with the following specifications.
Input voltage : 230 Volt
Input voltage tolerance : 170 - 270 Volt
Input power factor : Unity
Battery voltage : 48 Volt
Output power : 250 VA
Output voltage : 230 Volt
THD in the output waveform : 4%≤
138
The performance of the front end converter and the bi-directional converter were evaluated
separately. The results matched with the design specifications. The different converters were
assembled to construct the UPS. Steady state loading tests were performed to evaluate the
regulation of the output voltage. Step load tests were performed to evaluate the dynamic
performance of the UPS. These results are presented in Chapter 5.
The UPS developed is well suited for the low power range of systems. Additional features
like protection and annunciation can be added to make a product out of the design that is presented
in this thesis.
139
REFERENCES
1. R. D. Middlebrook and S. Cuk, "Advances in Switched Mode Power Conversion - Volume I, II and III", Teslaco, 1983.
2. "Voltage Regulator HANDBOOK", National Semiconductor Corporation.
3. Jasvinder Singh Khoral, "Power Factor Correction of Switching Power Supplies with UC3854", M.E. project report, Electrical Engineering, Indian Institute of Science.
4. "Product & Applications Handbook 1993 - 94", Unitrode Integrated Circuits Manual.
5. "SIEMENS' , Introduction to Electronic Control Engineering", Wiley Eastern Ltd.
6. V. Ramanarayanan, "Switched Mode Power Conversion", Class Notes, Dept. ofElectrical Engineering, Indian Institute of Science.
7. Abraham I. Pressman, "Switching Power Supply Design", McGraw Hill, 1992.
8. N. Mohan, Undeland and Robbins, "Power Electronics : Converters, Applicationsand Design", John Wiley and Sons, New York.
9. "Small-signal modelling of PWM switched mode power converters",R.D. Middlebrook, Proc of the IEEE, Vol. 76, No. 4, April 1988.
10. Dixon L.H., "High power factor pre-regulator for off line switching power supplies",Unitrode power supply design seminar manual, SEM 60, 1988.
11. "A Bi-directional power converter for non-isolated high ratio DC-DC power conversion", V. Ramanarayanan & S. Giridharan, Symposium on Power systemInstrumentation and Control, CPRI, Bangalore. (accepted for presentation)
141
