Diamond & Related Materials 40 (2013) 51–55

Contents lists available at ScienceDirect

Diamond & Related Materials

j ourna l homepage: www.e lsev ie r .com/ locate /d iamond

A novel structure to improve DIBL in fully-depletedsilicon-on-diamond substrate

Arash DaghighiFaculty of Engineering, Shahrekord University, Shahrekord, Iran

E-mail address: daghighi-a@eng.sku.ac.ir.

0925-9635/$ – see front matter © 2013 Elsevier B.V. All rihttp://dx.doi.org/10.1016/j.diamond.2013.10.010

a b s t r a c t

a r t i c l e i n f o

Article history:Received 1 July 2013Received in revised form 9 October 2013Accepted 11 October 2013Available online 23 October 2013

Keywords:Silicon-on-insulatorDrain induced barrier loweringSilicon-on-diamondFully depletedHydrodynamic modelMOSFET

In this paper, a novel silicon-on-diamond (SOD)MOSFET structure is proposed. The new structure eliminates thedegraded drain induced barrier lowering (DIBL) inherently observed in SOD devices. A second insulating layerover the buried diamond layer is integrated which partially covers the diamond layer. An expression for thetotal body capacitance through the insulating layers is obtained. Using analytical model, the second insulatinglayer dimensions are computed. In order to evaluate the impact of second insulating layer on the devicecharacteristics, hydrodynamic numeric analysis is performed. Device simulation results verified the analyticalmodel in DIBL improvement. Maximum lattice temperature of the new structure is well below SOI device and5% higher in comparison with SOD substrate. The device simulation results demonstrate short channel effectsimprovement and suppressed self-heating effects.

© 2013 Elsevier B.V. All rights reserved.

1. Introduction

Silicon-on-insulator (SOI) metal-oxide-semiconductor-field-effect-transistor (MOSFET) is built on a silicon layer overlaid on an insulationlayer of silicon dioxide formed in a silicon substrate. The buried oxide(BOX) is created using several methods [1]: 1) Implanting oxygenonto a silicon wafer and then heating the wafer to oxidize the silicon,thereby creating a uniform buried layer of silicon dioxide (SIMOX)and 2) Thermal oxidation of an initial substrate, then implanting byhydrogen, wafer bonding, splitting and annealing (Smart-Cut). BulkMOSFETs are fabricated on the top first micrometers of the siliconwafer having a thickness of several hundred micrometers. Majority ofthe parasitic components in BulkMOSFETs are caused by the interactionbetween the transistor and the substrate.

If a SOI substrate is used, the full dielectric isolation of the devicesprevents the occurrence of majority of the parasitic effects that can beseen in the Bulk MOSFET. In SOI devices, because of existence of buriedoxide layer, higher performance is obtained and a latch up path is ruledout. In addition to those mentioned, there are many more advantagespresented by SOI over Bulk MOSFET: the junction capacitance is lower,hence the device speed increases; Full isolation of neighboring devicesprevents “cross talk”; junction area is smaller, thus the leakage currentis lower; better short channel effects are observed and fabrication ofSOI devices can have fewer number of process steps. Therefore, SOICMOS offers functionality improvement over Bulk CMOS and it isconsidered to be the technology of choice for system-on-chip (SoC)

ghts reserved.

applications which requires integration of analog, digital, mixed-signaland RF circuits, all in one chip [2].

However, the performance of SOI MOSFET is considerably differentdue to the existence of buried oxide layer underneath the silicon filmor device layer. The presence of the BOX layer causes self-heating. Thisis due to the significantly smaller thermal conductivity of silicon dioxide(κ=1.4W/K-m) compared to that of bulk silicon at room temperature(κ = 140 W/K-m). The poor thermal conductivity of the BOX layerresults in the self-heating of the transistor and could cause severaleffects like degraded drive current due to the mobility reduction [3]and accelerated aging [4]. The self-heating effects become moresignificant as the density of the devices fabricated on a single siliconchip is increased to fulfill the ITRS requirements [5].

Silicon-on-diamond (SOD) substrate can be used as an alternative tostandard SOI technology to eliminate the self-heating effects. Inherentelectrical insulating properties together with excellent thermalconductivity of diamond (κ=2000W/K-m)make it a superb substitutefor the BOX layer in SOI technology. Thus, the generated heat in theactive silicon region of a SOD MOSFET spreads away from the junctioninto the underlying silicon substrate, die package and the heat sink.This allows operation at much higher power levels comparing withSOI MOSFET for the same junction temperature. Various experimentalmeasurements demonstrate that SOD can sustain more than 10 timeshigher power density than that of SOI [6].

On the other hand, integration of diamond as an insulator in fully-depleted SOI MOSFET suffers from an increase in short channel effects(SCE) comparing with SOI [7]. An important parameter to monitor SCEis the drain induced barrier lowering (DIBL). DIBL is defined as thethreshold voltage variation between low and high drain voltages

52 A. Daghighi / Diamond & Related Materials 40 (2013) 51–55

(ΔVth/ΔVDS). The insulating diamond or diamond-like carbon film has alarger dielectric permittivity (εDiamond = 5.7) than the silicon dioxide(εSiO2 = 3.9). Fig. 1 shows the fringing electric field inside the buriedinsulators of silicon dioxide in SOI and diamond in SOD devices biasedin saturation region. As can be seen from Fig. 1A and B, the value ofelectric field vectors (E

*) which starts from the drain and ends at the

body are smaller in diamond than that of silicon dioxide. In the presenceof a dielectric with dielectric constant εDiamond, the electric field is:

E*

Diamond ¼ εBOXεDiamond

!� E

*

BOX

ð1Þ

where E*

BOX is the electric field inside the buried silicon dioxide. Theelectric field in diamond insulating layer is smaller than the BOX layer.Therefore, when diamond with dielectric constant greater than silicondioxide is used, the capacitance increases:

CDiamond ¼ εDiamond

εBOX

� �� CBOX: ð2Þ

As a result, the drain-body fringing field capacitance insideinsulating diamondfilm is larger than the silicon dioxide. Consequently,the drain influences the body at greater rate resulting in degraded DIBLin SOD MOSFET than that in SOI MOSFET.

BOX thinning can be used as a method to improve DIBL in FullyDepleted (FD) SOD MOSFET. For example, using this method for a20 nm channel length device, the DIBL value of an Ultra-Thin Body(UTB) SOD MOSFET and UTB SOI MOSFET would be equal if the

Fig. 1. Electric field inside the buried insulators, VGS=VDS=0.8V, L=22nm (A) Silicon-on-insulator FD MOSFET, (B) Silicon-on-diamond FD MOSFET.

equivalent insulating layer thickness reduces to 30 nm [7]. However,there is trade-offs between DIBL and parasitic source-substrate anddrain-substrate capacitances. In order to lower DIBL, the insulatinglayer thickness can be reduced. Therefore, the source-substrate anddrain-substrate capacitances increase. This adversely influences thedevice switching speed and transistor working frequency.

In this paper, a novel structure is proposed to improve DIBL in FullyDepleted Silicon-on-Diamond substrate without affecting the parasiticsource-substrate and drain-substrate capacitances. In other words, adouble insulating layer over the diamond layer is added which partiallycovers the first layer. It is shown that field penetration, hence DIBL,improves in the proposed structure. The paper is organized as follows:the novel device structure and the simulation model are explained inSection 2, device simulation results are discussed in Section 3, followedby conclusion in Section 4.

2. Device design and simulation model

Addition of a thin second insulating layer e.g. silicon dioxide, over thediamond layer in SOD substrate reduces the drain-body fringingcapacitance.While the second layer enhancesDIBL [8], self-heating effectspronounce as a result of low thermal conductivity of the silicon dioxide.

The double insulating fully-depleted device structure is shown inFig. 2. As can be seen, the second insulating layer is over and partiallycovers the first insulating layer [9]. In the novel device, thefirst insultinglayer is diamond or diamond-like carbon and the second insulting layerhas dielectric constant smaller than the diamond in order to reduce thefringing capacitance. The buried oxide and insulating layer parasiticcapacitances are shown in Fig. 3. In a fully-depleted SOI MOSFET, thedevice body is influenced by CBS1, CBD1 and CBOX1 through the buriedoxide layer as shown in Fig. 3A. CBD1 and CBS1 can be several timesgreater than CBOX1. Therefore, the lateral coupling mainly influencesthe device body [10]. As a result, in SOD substrate where the diamondhas larger electrical relative permittivity than silicon dioxide, the devicebody is largely controlled by the drain/source region. Fig. 3B shows thedevice body capacitances through the insulting layers of the noveldevice structure. In order to compute the total capacitance on the devicebody through the buried insulating layers, the parallel connection of theCBD and CBS capacitances is considered:

CBD ¼ CBD1 þ CBD2 þCBOX2 � ð2CBD3 þ CBOX1Þ

2ðCBOX1 þ CBOX2 þ 2CBD3ÞCBS ¼ CBS1 þ CBS2 þ

CBOX2 � ð2CBS3 þ CBOX1Þ2ðCBOX1 þ CBOX2 þ 2CBS3Þ

:ð3Þ

Fig. 2. The novel fully-depleted silicon-on-diamond device structure.

Fig. 3. Device body capacitances through the buried insulating layers, (A) Fully-depletedSOD substrate, (B) Novel device.

53A. Daghighi / Diamond & Related Materials 40 (2013) 51–55

In order to compute the coplanar plate and perpendicular platecapacitances, the equation below is used:

C ¼ ε0 � εrθ

� ln 1þ ld

� �ð4Þ

where εr is the insulating layer electrical permittivity, θ defines theplates angle in radians, l and d are the plates' length and distance fromthe common origin, respectively. θ is 2π for the case of coplanar platecapacitance.

Fig. 4 shows the total body capacitance through the insulating layersfor two different values of second insulating layer thickness as thewidthof second insulating layer varies. As can be seen, the total bodycapacitance has a decreasing trend as LBI increases and it starts from amaximum where LBI almost equals the effective channel length (Leff).

Fig. 4. Total body capacitive coupling through the buried insulating layers versus secondinsulating layer width.

This is the region where CBD2 and CBS2 dominate in Eq. (3). For thecase of tBI=10 nm, the decreasing total capacitance never reaches theSOI and SOD body capacitances through the insulting layer and it'salways greater than SOD body capacitance. Even for large LBI wherethe last part of Eq. (3) which includes CBOX1, CBOX2, CBD3 and CBS3dominates, the body capacitance of the new structure is higher thanthat of the SOD body capacitance. Therefore, there is no secondinsulating layer width at tBI = 10 nm for which the new structurecapacitance reaches the SOD body capacitance.

However, the total body capacitance through the insulating layers ofthe new structure crosses the SOD body capacitance for LBI=30nmanddecreases further as LBI increases at tBI = 80 nm. The dielectricpermittivity of the second insulating material is smaller than thediamond. For enough large LBI, the capacitance approaches the SOIbody capacitance through the insulating layer. In this region, CBD1 andCBS1 are the capacitances that dominate in Eq. (3). Therefore, the novelstructure shown in Fig. 2 presents enhanced body capacitive couplingthan SOD for tBI=80nm and LBI greater than 30nm. The improvementin capacitive coupling gets close to that of SOI for large enough LBI.

In order to cover the non-ideal effects such as fringing field capac-itances and incorporate advanced physical models, numeric methodsfor the simulation of semiconductor devices are used. DESSIS is a multi-dimensional electro-thermal device simulator for numeric analysis ofsilicon-on-insulator devices [11]. In the hydrodynamicmodel, the carriertemperatures are not equal to the lattice temperature. Therefore, thehydrodynamic transportmodel is simulated to provide amore physicallyaccurate model than conventional transport equation. However, itoverestimates the carrier velocity along the channel. Energy relaxationtime is a model parameter that calibrates the carrier velocity. DESSISdefault value for electron relaxation time is 0.3 pS. The hydrodynamictransport model is therefore calibrated to reduce the overestimate ofelectron velocity in a 22nm FD SOI MOSFET [12].

3. Device simulation results

In order to further investigate the impact of the second insulator onthe device characteristics and compare the results with the analyticalmodel, calibrated hydrodynamic numeric simulation is performed.Three device structures are compared based on their performance onself-heating effects and DIBL value: 1) SOI MOSFET, 2) SOD MOSFET,and 3) Novel SOD MOSFET. Table 1 summarizes the device dimensionsand parameters used for model analysis and device simulations. In thenovel SOD structure, thefirst insulating layer is diamond and the secondinsulating layer is silicon dioxide with variable width LBI.

Fig. 5 shows the drain-source current versus drain-source voltage.SOI MOSEFT has the lower Ion compared with the SOD MOSFET due tothe higher threshold voltage as a result of larger CBOX1. The thresholdvoltage is the lowest for the novel device at LBI = 20 nm, and Vth isalmost equal for the SOD and the novel device at LBI = 100 nm. Thethreshold voltage, hence drive current, is influenced by the body factor

Table 1Device parameter values used for analysis and simulations.

Parameter Value

Equivalent gate oxide thickness 0.8 nmSilicon film thickness 7 nmFirst insulating layer thickness 100 nmSecond insulating layer thickness 80nmSecond insulating layer width 20 nm~ 120 nmOxide gate spacer width 10nmSilicon oxide relative dielectric constant 3.9Diamond insulating layer relative dielectric constant 5.7Substrate doping 1015 cm−3

Silicon body doping 1.5 × 1019 cm−3

Gaussian source/drain peak doping 1020 cm−3

Polysilicon gate doping concentration 5 × 1020 cm−3

Fig. 5. Drain current per micron width of the device versus drain-source voltage.

54 A. Daghighi / Diamond & Related Materials 40 (2013) 51–55

which is a function of total body capacitance through the insulatinglayers [13]. The body factor of the novel device can be written as:

β∝CBD þ CBS ð5Þ

where CBD and CBS are defined by Eq. (3). As can be seen from Eq. (5)and suggested from Fig. 4, the sensitivity of the charge couplingbetween the front gate and the back gate (the substrate and the buriedinsulating layer in SOI MOSFET create a second gate as back gate) isdominated by the perpendicular electrode capacitances CBD2 and CBS2for small LBI values and is controlled by the coplanar plate capacitancesCBD1 and CBS1 for larger LBI values. The above discussion can further beexplained using Fig. 6. Constant-current threshold voltage extractionis used and threshold voltage is defined as the gate voltage for whichthe drain current is 1 μA/μm [14,15]. As can be seen, the linear andsaturation threshold voltages show the same trend as LBI increases.Due to the increased body factor as suggested by Eq. (5), the noveldevice threshold voltage is smaller than the SODMOSFET for LBIb30nm.The threshold voltage approaches that of SOI MOSFET for LBIN45nm asCBD+CBS is dominated by CBD1+CBS1.

Fig. 6 shows the DIBL value as LBI varies. DIBL is defined asthreshold voltage variation when drain voltage sweeps from0.05 V to 0.8 V. As can be seen, DIBL in SOD MOSFET is larger thanthat of SOI MOSFET due essentially to higher CBD1 + CBS1 + CBOX1.In the novel structure, the DIBL is larger than that of SOD whereCBD2 and CBS2 dominate for LBI b 30 nm. As LBI increases further, thebody factor in Eq. (5) gets smaller and mostly dominates by CBD1

and CBS1. For LBIN90nm, the DIBL is identical to that of SOI MOSFET.As a result, for enough large second insulator width, there is no DIBLdegradation of the novel structure with respect to SOI MOSFET.Fig. 7 shows the on-current to off-current ratio. As can be seen,the Ion/Ioff value has an increasing trend and approaches that of

Fig. 6. Linear threshold voltage, saturation threshold voltage and DIBL versus secondinsulating layer width.

SOI MOSFET for LBI N 90 nm. For LBI greater than 50 nm and smallerthan 90nm, the Ion/Ioff value is even larger than that of SOI MOSFET.This is the region where the novel structure threshold voltage getsslightly higher than that of SOI MOSFET. Therefore, the off-currentreduces. Hence, increased ratio is obtained. The Ion/Ioff ratio getsidentical to that of SOI MOSFET as threshold voltage converges toSOI MOSFET value. There is a sharp kink observed for LBI N 90 nmwhich can be due to coarse simulation stepping.

The buried insulator of SOD substrate dissipates the generatedheat in the channel to the underlying substrate and heat sink contact.Fig. 7 shows the maximum lattice temperature which is obtained atVGS=VDS=0.8 V for all the structures. As can be seen, TMAX for SOIsubstrate is substantially larger than that of SOD substrate leadingto pronounced self-heating effects. The novel SOD device showssmaller lattice temperature than that of SOI MOSFET. In the novelstructure, although the heat-flow path through the silicon isshallower at large LBI, only 5% increase in TMAX of the lattice isobtained compared with SOD substrate. As LBI gets smaller than50 nm and approaches to 20 nm, TMAX increases from a minimumthat occurs at LBI= 50 nm. This is due to lowered threshold voltageat this interval as can be seen from Fig. 6. Therefore, Ion increases asthreshold voltage is lowered and the lattice temperature furtherincreases. This trend can also be observed in Fig. 5 where 15%increase in current drive is obtained comparing the Ion value ofnovel SOD at LBI = 20 nm with the conventional SOD. As a result,elevated TMAX is obtained when LBI approaches to 20 nm.

Comparing the results obtained from threshold voltage and DIBL, itis concluded that these values are identical to that of SOI MOSFET bychoosing the design window as LBI N 90 nm. Therefore, the associateddegradation for SOD MOSFET is eliminated in the novel structure. Inaddition, for the novel structure, self-heating effects are suppressedsince TMAX is considerably lower from SOI MOSEFT in the designwindow.

4. Conclusion

A novel SOD MOSFET structure is demonstrated to improve shortchannel effects which are inherently degraded in SOD devices. A secondinsulating layer over the diamond layer is integrated. The total bodycapacitance through the buried insulators is computed analytically andit showed that proper choice of the insulating material, thickness andwidth of the second insulator have a direct impact on the bodycapacitance value. The variations observed in total body capacitancewere confirmed by hydrodynamic transport model simulation of a22nmSODMOSFET. The calibrateddevice simulation results demonstrateimprovement in drain induced barrier lowering and suppression of self-heating effects.

Fig. 7. On-current to off-current ratio and maximum lattice temperature versus secondinsulating layer width.

55A. Daghighi / Diamond & Related Materials 40 (2013) 51–55

Prime novelty statement

The device structure has already been filed as US Patent US2010/0295128 A1 by the author. In this paper, for the first time, thenovel SOD structure is analyzed by analytical capacitance model andcalibrated hydrodynamic numeric analysis.

References

[1] J.-P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI, 3rd edition KluwerAcademic Publishers, 2004.

[2] G.G. Shahidi, SOI technology for the GHz era, IBM J. Res. Dev. 46 (2/3) (March/May2002) 121–131.

[3] A.K. Goel, T.H. Tan, High-temperature and self-heating effects in fully depleted SOIMOSFETs, Microelectron. J. 37 (2006) 963–975.

[4] C. Fiegna, Y. Yang, E. Sangiorgi, A.G. O'Neill, Analysis of self-heating effects inultrathin-body SOI MOSFETs by device simulation, IEEE Trans. Electron Devices 55(1) (2008) 233–244.

[5] International Technology Roadmap for Semiconductors (ITRS), http://public.itrs.net/.[6] A. Aleksov, J.M. Gobien, X. Li, J.T. Prater, Z. Sitar, Silicon-on-diamond— an engineered

substrate for electronic applications, Diamond Relat. Mater. 15 (2006) 248–253.

[7] J.P. Mazellier, O. Faynot, S. Cristoloveanu, S. Deleonibus, P. Bergonzo, Integration ofdiamond in fully-depleted silicon-on-insulator technology as buried insulator: atheoretical analysis, Diamond Relat. Mater. 17 (2008) 1248–1251.

[8] J.P. Mazellier, F. Andrieu, P. Bergonzo, S. Saada, Substrate of the semiconductor oninsulator type with intrinsic and doped diamond layers, USPTO patent application,US 2011/0156057 A1.

[9] A. Daghighi, Double insulating silicon-on-diamond device, USPTO patent application,US 2010/0295128 A1.

[10] T. Ernst, C. Tinella, C. Raynaud, S. Cristoloveanu, Fringing fields in sub-0.1 μm fullydepleted SOI MOAFETs: optimization of the device architecture, Solid State Electron.46 (2002) 373–378.

[11] DESSIS Manual, ISE Integrated System Engineering, Version 10.0, 2004.[12] R. Granzner, V.M. Polyakov, F. Schwierz, M. Kittler, R.J. Luyken, W. Rősner, M.

Städele, Simulation of nanoscale MOSFETs using modified drift-diffusion andhydrodynamic models and comparison with Monte Carlo results, Microelectron.Eng. 83 (2006) 241–246.

[13] B. Sviličić, V. Jovanović, T. Suligoj, Analytical models of front- and back-gate potentialdistribution and threshold voltage for recessed source/drain UTB SOIMOSFETs, SolidState Electron. 53 (2009) 540–547.

[14] H.G. Lee, S.Y. Oh, G. Fuller, A simple and accurate method to measure the thresholdvoltage of an enhancement-mode MOSFET, IEEE Trans. Electron Devices 29 (2)(1982) 346–348.

[15] A. Ortiz-Conde, F.J. Garcia Sanchez, J.J. Liou, A. Cerdeira, M. Estrada, Y. Yue, A reviewof recent MOSFET threshold voltage extraction methods, Microelectron. Reliab. 42(2002) 583–596.