Short otes

A Note on Logical Gain E C, < F for all j.EIICHI GOTO

i.e., the total fan-outs from thejth element does not exceed F.Owing to the necessity for logical gain or amplification of signals The multiplication process will be said to have a solution if the

in logic circuits, the maximum number of permissible fan-outs has fan-out restrictions are satisfiable by providing xj copies (positivebeen regarded as one of the most important features of logical circuit integers) of the jth element. In other words, we are asking about theelements. Insertion of extra amplifiers certainly provides a simple satisfiability or the feasibility of a set of inequalities,method for getting around the difficulties caused by fan-out restric-

x

tions. A disadvantage of this method, however, consists in the extra E xiC, < Fx1 for ally (2)time delay which may considerably slow down the speed of basic . . .logical operations. s

An alternative method, to be called the multiplication method Moreover, in case (2) is satisfiable with integers, it will also be re-will be exemplified in Figs. 1 and 2. Each square box in the figures quired to minimize the total number of elementsrepresents a logical element with two inputs, I= 2. The precise func- N* = xtioning of each element (i.e., whether each is an "And," or, "Nor" ior a "Nand" box or something else) as well as the clocking of the resulting from the application of the multiplication method.elements will be irrelevant to the present discussions. Suppose we The above feasibility and minimization problems are integer,have obtained a basic logical design of a circuit as Fig. 1 by consider- linear programming problems. Two theorems relating to the feasibil-ing the number of fan-ins, 1=2 only. Further, let the maximum ity will be given. Theorem 1 will state that the present integer linearpermissible number of fan-outs F be two. Boxes 1 and 2 in Fig. 1, re- programming problem is reducible to a real linear programmingspectively, having 4 and 3 fan-outs, violate the fan-out restriction. problem, which is generally easier to handle. Theorem 2 will state aThis may be obviated by providing logically identical copies of ele- sufficient condition for the feasibility.ments 1 and 2, or by duplicating elements 1 and 2. These duplications,however, will cause the fan-outs from elements 1, 2 and 5 to increase. Theorem 1Hence, more copies of these elements will be needed. As a result of The multiplication method has a solution, i.e., (2) is satisfiablesuch modifications, we obtain a modified logic as shown in Fig. 2 with positive integers, if and only if the set of inequalities (2) arewith all elements satisfying the fan-out restriction. The input to the satisfiable with a set of real numbers xj's not smaller than unity.circuit in Fig. 2 also has to be quadruplicated but this will generally Proof: The "only if" part is trivial. From the theory of linear pro-be quite permissible, especially in case the input to the circuit is to be gramming,' it is known that when a set of linear inequalities, (2) andobtained from another circuit consisting of similar logical elements. xj> 1, is satisfiable with real numbers there exists at least one extreme

The multiplication method, providing a possible solution to the point solution xj(e satisfying all of the inequalities and that each valuefan-out problem of the above example, may not have a solution in xj(e is equal to a quotient of certain two determinants consisting of thesome cases. Fig. 3 is a simple example, wherein the multiplication coefficients of the inequalities. The coefficients Cij, F and the l's inprocess obviously does not have any solution at all. the right side of xj >1 being integers in our present case, x/(6 must all

The main objective of this note is to examine the feasibility Of be rationals. Hence, by denoting the least common multiple of thethe multiplication method. Logical elements each having at most (a denominators of x1(e's by M, Mx/(e clearly gives a set of integers satis-positive integer) F fan-outs will be considered. Suppose we have ob- fying (2) and Mx(e.>M>1. (Q.E.D.)tained a basic logical design of a circuit consisting of N elements byconsidering the restriction on inputs only. In this basic design, let the Theorem 2number of wires coupling the output of thejth element to the input of If the number of fan-outs F exceeds the number of inputs I, i.e.,the ith element be (non-negative integers) Cj, with i and j being if F>I, the multiplication method has a solution, otherwise, i.e.,running suffixes, i, = 1, 2, 3 * * , N. The restrictions on Cx, and on if F<I it may or may not have a solution.

the numberofinputsmay be expressed asProof: As to the latter part of the theorem, Figs. 1 and 2 gives an0 < Cts . I and E Ctj < 1, for all i.*.-. (1) example of the case F= 1=2 having a solution and Fig. 3, that having

i ~~~~~~~~~nosolution. Hence, by virtue of Theorem 1, we only have to showThat is, the total number of inputs to the ith element never ex- the existence of a real solution x1, xj> 1 in case of F>I. We shall

ceeds I. The basic design, of course, is not expected to satisfy the fan- show this by starting from a set of initial values x/0°= 1 for all]j, andout restrictions, by applying the following successive modification process:

Manuscript received January 23, 1964.The author is with the Department of Physics, University of Tokyo, Tokyo,

Japan. ' S. I. Gass, "Linear Programming," New York, N. V.; 1958.

606

Short Notes 607

A Logical Circuit x1(k = xj(k-1 +AkXi= x/(+ AX + A2xj* +Akxi,1 ---_ -_ ___

Akxi = 0 if E xi(k1Cjj < Fx7(k-1 and otherwise

Output AkX, = E Xi(k-1C,,/F - x,(k-1 >0O *. (3)Input 43

2 I 0 By virtue of (1), the sum of the first corrections

to the from the ACircuit fan_outs Circuit

3 . is bounded. Namely,Z Ax, < LE xi(oCijCF < E xi(5I/F < NI/F.

I | I i i i X

Similarly, the sum of the kth corrections

11=2~~~~~~~~~~~~~~~~~~~~~~AX

is also bounded

51 E AkXj X* ( Ex(k-1Cij/F - Xj(k-i)

Xi(k-2 + £5 .Si)ij/L) - (X1(k-2 + Ak-lxj))

Fig. 1-A basic design disregarding fan-out restrictions. < (Ak-ixiCij/F) < (I/F) Z ,A"-xj < (I/F)kN,

where Z means to take the sum of positive terms only.The sum of the modified values

Z Xj(k

is thus bounded by the following geometrical series in case of F>I:l1

l 1 2 LX kX( < N(1 + (I/F) + (I/F)2 + * (I/F)k)< NF/(F- 1) for any k * - (4)

2 2 Hence, the modification process converges to limiting values xj(°,12 i 2 which satisfy the fan-out restrictions,

/xi(Ci, < Fx/( for all j. (Q.E.D.)Output Let us now turn to the minimization of the total number of

3 j /1 3 I velements N* resulting from the modifications in accordance with themultiplication method. The integral solution Mxj(e in the Proof ofTheorem 1 will not, in general, be the optimum solution which

, -b11 | Li 1 | minimizes N* because the least common multiple M will be an un-

14 | LE3I necessarily large number in most cases. In other words, Mx/11 will beInput tI useful only as an existence proof. In most cases, the optimum integral

: l solution x1(m will be a set of integers not too far apart from the real

2 solution xj11 in the Proof of Theorem 2 and the total number N* will

II =2 4 not exceed the bound NF/(F-I) of (4). This has actually been thecase for all of the examples considered so far by the present writer.

F = 2 Therefore, we may expectN* < A(F, I)N, with A(F, I) = F/(F - I) (5)

to hold in almost all practical cases.Thus, from Theorems 1, 2 and (5), we reach the following conclu-

I ~~~~~~~~~~~~~~~~sions.2 . 1 1) F>I, or the excess of the fan-outs F over the inputs I isL 3 '2

4a very important feature of logical elements. WVhile the logical abilityof elements satisfying F>I is equivalent to that of elements having

L - - - - - - - - - - - - - - - - - - - infinite permissible fan-outs in respect to speed, the ability of ele-ments of F<I is highly restrictive.

Fig. 2-The multiplication method applied to Fig. 1. 2) In case of F>I, logical designs may be made in two steps. Thefirst step will consist of making a basic design without considering thefan-out restrictions. The second step will consist of a purely mechan-

I = F =2 ical modification procedure called the multiplication method whichff n ~~~~~~~~~~~takescare of the fan-out restrictions. Neither revision of the basic

I 3 1~~~~~~~~~~logical structure nor increase in extra delay time will be required in| ;i ~~~~~~~~~~~the second step.

I u Output ~~~~~~~3)The multiplication method may cause the number of elementsL_-- required to increase byafactor of A (FI= F /(FItimes in the

Fig. 3-A circuit to which the multiplication mlethod is not applicable, worst case. A (F, I), or its inverse a(F, I) = 1/A (F, I), may thus be

608 IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS October

regarded as the most reasonable figure of merit for logical gain. r , -l T l. llConsider, for example, a two-input universal element, say a 1.4 \ - - _-

"Nor" box consisting of a tunnel diode. The effort trying to increase , ._-t_- _lthe fan-outs F from two to three will be very highly rewarding be- 1;2 ,____ 4

cause it corresponds to the drastic qualitative change from F< I to 1. WF>I. That from F=3 to 4 will be rewarded, in general, with a reduc- _ _ __ __ - __tion of number of elements by a factor of 2/3 since A(4, 2)/A(3, 69 - _.i _2) = 2/3. An effort to increase from F= 10 to F= 20, say, may not be ___ __ -_ -- rl -worth trying since the profit will only be from A (10, 2)=5/4 to t.7_-L____ L_________I__A(20, 2)= 10/9. L- I II___

The multiplication process was actually used in the logical design _ _of two parametron computers PC-1 (consisting of 4300 parametrons) _ _ Tand PC-2(13,000 parametrons) at the University of Tokyo and has -been proved to be quite practicable. Each parametron element was 3 __ -- -- - -used as a majority organ of not greater than five inputs with 12 _2_ | -'maximum fan-outs, i.e., 1<5 and F= 12. While 33 per cent increase It -in number of elements was the worst to be expected from formula (5), 3 4 6 78 910 20 30 40 soa60A(12, 5)=4/3 =100+33 per cent, the actual increase caused by the kmultiplication method was only less than 10 per cent. Fig. 1.

The amount of equipment involved has been reduced to equiva-lent transistors, considering the cost of three diodes as equivalent tothe cost of one transistor, and assuming that the cost of associatedelements (resistances, capacitors, printed circuits, etc.) per transistoris the same in both cases. The cost per operation in the arithmetic unit

Base 3 vs Base 2 Synchronous Arithmetic Units may be considered proportional to the cost of the unit and to the

J. SANTOS AND H. ARANGO time necessary to perform the operation. The cost of the unit is pro-portional to the number of equivalent transistors required in the

The growing complexity of modern computers makes a compara- shifting registers and in the adder.tive evaluation from an economical point of view very difficult. The The numbers may be processed serial wise, parallel wise or in atimes necessary to perform certain operations (e.g., addition, multi- serial-parallel combination. Although the number of the equivalentplication, red tape orders, etc.) are no longer relevant by themselves transistors will remain the same in the registers, its number in theand must be considered in conjunction with the size of rapid access adder will increase with the increasing number of stages operating instores, code of instructions, available time-sharing facilities, etc. parallel, but a corresponding reduction in the time required to per-

The ultimate test to determine which one of two computers is form the operation is obtained.faster would be to process the same problem, optimum programmed, The number of bits processed, the number of stages operating inon both. parallel, the times required to perform an operation in binary or

Even this test would be conclusive only for that particular type ternary fashion and the ratio of the figures of merit for both cases areof problem, but considering the cost of the machine and the time re- expressed asquired to process the program, a figure of merit in the form of the breciprocal of a cost per operation could be obtained. k =

The problem of estimating a figure of merit for the whole com- n

puter may be broken down to a separate weighted evaluation of t2 -= kevery unit within the computer. The following is an analysis of nsynchronous arithmetic units from the base 3 vs base 2 point of view. b k

It is a very well-known result of the Theory of Information that t3 l.58=if the amount of equipment required to staticize the information isproportional to the base, 3 is the most economical integer base for 0r80c3k + 0.63s3number systems. 2c2k + S2

Base 2 (or other bases binary coded) however, have been used in wherealmost every digital computer developed up to the present. Thefundamental reason behind this fact is that almost every physical b=number of bts ineac aroeadevice used in the actual construction has two clearly distinguishable

k =numbe of sta n parallel

states, easily correlated to Boolean values 0 and 1 k = b means a serial addera intermediate values mean aBased on the Kilburn fast carry propagation circuit [2 J, the combimatn a serialae i rmate vlesauthors developed ternary and binary versions of an adder and their combination of both in the serial-parallel typerespective shifting registers, using in both cases the same type of t esrequiredotransistors, diodes and associated components, in order to compare respectivelyunits of similar electronic design. The ternary adder is described in rSantos and Arango [ti, and the binaryversion is actuallyincorporated c2, c3=cost of the binary or ternary multivibrator in the shiftingin CEUNS [31, an octal base binary codified computer that the registers, respectively

authors ~ ~ .ar deeopn at th Unvria Naioa de Sur The 5°t 53 = cost of the binary or ternary adder stage, respectively.hypotheses of the same shifting speed in the registers, whether binary In our circuits, G2.~3.33, c3~6, s2~-20, s3..56, and thereforeor ternary, and the same carry propagation speed in both accumula-tors seem to be valid. 4.8k± 35.4

6.6k + 20Manuscript received April 25, 1964. In Fig. 1, r is plotted vs k for the particular values of c and s quotedThe authors are wvith the Department of Electrotecnia, Universidad Nacionalbeo.

del Sur, nahia Blanca, Bs. As., Argentina.beo.