A New Era in Manufacturable, Low-Temperature and Ultra-Fine Pitch Cu Interconnections and Assembly Without Solders

Vanessa Smet*, Makoto Kobayashi†, Tao Wang, Pulugurtha Markondeya Raj, and Rao Tummala

3D Systems Packaging Research Center, Georgia Institute of Technology, Atlanta, USA †Namics Corporation, Niigata, Japan

* Email: vanessa.smet@prc.gatech.edu

Abstract This paper presents the first demonstration of a high-

throughput die-to-panel assembly technology to form Cu interconnections without solder at temperatures below 200°C. This interconnection technology, previously established with individual single-chip packages on both organic and glass substrates, at pitches down to 30µm, is brought up to a significant manufacturable level by two major innovations: 1) ultra-fast thermocompression bonding (TCB) process with pre-applied polymer, in air, and without any prior surface activation; 2) die-to-panel assembly process with heating from die side exclusively for reduced substrate warpage. The initial proof of concept reported in this paper consists of assembly of 15 silicon dies with Cu bumps at 100 µm pitch, on a 3” x 5” organic substrate, by sequential TCB at 210°C for 3 seconds, and 190°C for 10 seconds. X-ray analysis, C-SAM imaging, cross-section observation with optical microscopy and SEM, and electrical yield characterization indicate the formation of strong metallurgical interconnections. This pioneering technology addresses many manufacturability challenges presently hindering the technology-transfer of direct Cu-Cu bonding, the “holy grail” in the semiconductor industry, by offering a potentially low-cost, high-throughput solution, compatible with industry-standard assembly lines. Scalable to ultra-fine pitches onto low-CTE glass, silicon or organic packages, it has the potential to become a major enabler for the next two or more decades.

Introduction The need for higher bandwidth between two or more ICs

at low power for next generation mobile and high-performance systems is expected to drive off-chip interconnections pitches down to 10 µm and below by 2020. Reduction in pitch ultimately leads to scaling down the micro-bump standoff height and diameter, and, in case of solder-based technologies, to reduction in solder volume. Standard copper pillars with solder cap, currently dominating the market at pitches as low as 40 µm, face many fundamental challenges to meet the miniaturization and performance targets of emerging applications, including bridging, increased interfacial stress between intermetallic layers and residual solder due to the reduced solder volume, and poor current-handling capability. Therefore, what is required is a new class of ultra-short solder-free interconnection technologies that relies on solid-state bonding to achieve ultra-fine interconnection pitch without the risk of bridging and eliminating unstable interfaces associated with intermetallic compounds. Copper has high electrical and thermal conductivities enabling high-speed signal transmission and high power-handling capability, and is also compatible with back-end-of-line processes, benefiting from well-established

plating infrastructures. All-copper interconnections are consequently highly sought and extensively researched as the “holy grail” in the semiconductor packaging industry. However, the current approaches to direct copper-to-copper bonding often involve strenuous processing steps for surface activation and oxide removal, such as chemical-mechanical polishing, or complicated bonding processes at temperatures exceeding standard lead-free reflow, with long annealing times for interdiffusion or recrystallization, or requiring vacuum or a specific atmosphere [1-8]. The complexity of these solutions leads to high manufacturing cost, thus hindering technology transfer to high-volume assembly lines. Further, the proposed assembly technologies have low tolerance to substrate warpage, and bump and pad non-coplanarities, which are invariably present in wafers and substrates fabrication.

The low-temperature copper interconnection technology recently patented by the Georgia Tech 3D Systems Packaging Research Center [9] comprehensively addresses these challenges with the following key innovations: 1) preventing copper oxidation, typically present in Cu-Cu bonding, by standard ENIG (electroless Ni – immersion Au) or ENEPIG (electroless Ni – electroless Pd – immersion Au) surface finish, applied on micro-bumps and pads; 2) accommodation of micro-bumps and pads non-coplanarities by collapse of the interconnections under pressure during thermocompression bonding; 3) warpage reduction with assembly at temperatures as low as 180°C, below the glass transition temperature Tg of low-CTE (coefficient of thermal expansion) laminates; 4) reduction in bumping cost by eliminating solder plating and using ultra-short all copper bumps, about 10 µm in height. The superior thermomechanical reliability and electromigration resistance at 106 A/cm2 of these advanced copper interconnections were demonstrated on low-CTE organic and glass interposers at pitches as low as 30 µm [10-12].

The current phase of this research aims at scaling this technology down to 20 µm pitch and below [13], and also bringing it to a manufacturable level with a high-throughput assembly strategy. This forms the key focus of this paper. The established process for low-temperature copper bonding consists of thermocompression bonding with a unique pre-applied polymer (e.g. B-stageable no-flow underfill – BNUF, nonconductive adhesive, film or paste – NCA, NCF or NCP), as capillary underfill is not applicable for such fine gap. Compared to a traditional flip-chip bonding sequence that comprises of die-to-substrate pick-and-place on a strip, followed by batch reflow, each die is generally assembled individually onto the substrate in thermocompression bonding, therefore penalizing assembly throughput and increasing processing cost. Reducing the time spent under the

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thermocompression tool is subsequently critical for manufacturability. This paper demonstrates an enhanced assembly technology that enables the formation of a strong metallurgical bond between micro-bumps and pads by pressure-induced plastic deformation of non-oxidized metal surfaces in a mere few seconds. The bonding time is found to be dependent on the polymerization of the epoxy-based pre-applied material, as is explained in the first section. To further increase the throughput, a panel-based process has been developed, relying on heating only from the die side, to limit warpage effects. Daisy chain test dies with copper interconnections ~20 µm in height, at 100 µm peripheral pitch were fabricated for this first proof-of-concept demonstration, and assembled on 3” x 5” organic substrates. The initial process conditions – 3 seconds at 210°C and 10 seconds at 190°C – were validated by several analytical methods, including electrical DC measurements, to evaluate the quality of the joints and interconnection yield. The preliminary results are discussed to assess the enhanced manufacturability of the proposed approach, applicable in standard assembly lines.

Test Vehicle Fabrication A test-vehicle that incorporates daisy chain structures was

designed to evaluate the yield and reliability of the copper interconnections after panel-level thermocompression bonding. Although this technology targets wide I/O, large-die and ultra-fine pitch applications, coarser design rules were chosen for this first process demonstration. The silicon die is 5 mm x 5 mm and 600 µm in thickness. It features 760 copper micro-bumps that are 30 µm in diameter and ~20µm in height, with 3 peripheral rows at 100 µm pitch, and a central area array at 250 µm pitch. The design includes 4 two-point probe structures for corner daisy chains, 8 half-edge daisy chains, while the central area array is broken into 4 individual daisy chains as illustrated in Figure 1.

The dies were fabricated from a 600 µm thick wafer using a standard semi-additive process. A 2 µm thick SiO2 layer was first deposited by Plasma-Therm PECVD, followed by sputtering of a 30 nm Ti – 500 nm Cu seed layer. A 2.5 µm thick Cu dogbone redistribution layer is then laid out on the wafer by electrolytic plating, followed by bumping photolithography and electroplating of the ~20 µm height Cu micro-bumps. After photoresist strip and seed layer etching, ENIG surface finish is applied on the Cu bumps to prevent oxidation. This surface finish consists of ~5 µm of electroless Ni and ~100 nm of immersion Au. Commercial electrolyte formulations from Atotech were used for the Cu plating and ENIG finish.

Although the application focus of this interconnection technology is primarily with low-CTE glass and silicon interposers, the semi-additive fabrication process is time-consuming, involving complex process steps such as dielectric film lamination, electroless Cu plating to form a seed layer, lithography followed by Cu electrolytic plating to build the redistribution layers, photoresist stripping, seed layer etching, and finally surface finish. Organic Cu-cladded FR4 substrates, in 6” x 6” size, patterned with the substractive method were thus used for this feasibility study. The 50 µm thick Cu film coating on both sides of the 1 mm thick organic core was first etched down to 10 µm thickness, before proceeding with

lithography and etch-back processes to build the Cu pattern without the need for a seed layer. After photoresist strip, ENIG surface finish is plated with 5.5–7 µm Ni and ~100 nm immersion Au. The individual single-die interposer unit represented in Figure 1 is about 20 mm x 20 mm in size.

Interface Characterization and Bonding Mechanism Process-of-record (PoR) for low-temperature Cu

interconnections without solders: The assembly process was previously demonstrated on glass and organic interposers with excellent reliability performance in high-temperature storage, unbiased highly-accelerated stress test and thermal cycling test obtained at 30 µm pitch [10-12]. A unique polymer material with a filler-free composition such as pre-applied underfill or non-conductive film is first dispensed on the substrate bonding area with good control of the viscosity and deposited volume. B-stageable no-flow underfill (BNUF from Namics Corporation) was used for this set of experiments. After dispensing, this epoxy-based material requires B-staging at 70°C for 1h in air. The Si die is then assembled onto the polymer-coated substrate by thermocompression bonding at 200°C, 365 MPa with a 60s dwell time at peak temperature, consistent with the established PoR conditions. The BNUF material reaches a low-viscosity point at temperatures ~100°C, allowing the excess material to be squeezed out from the bonding interface and flow, enabling contact between Cu micro-bumps and pads, then starts hardening at higher temperature. By the end of the bonding process, the BNUF material is fully cured and the assembled structure does not necessitate any post-treatment.

Interface analysis and proposed bonding mechanism: During thermocompression bonding, the pressure applied on the die transfers directly to the Cu micro-bumps, resulting in high stress concentration per unit area at the rough bump-to-pad interfaces. When the bonding stress exceeds the yield strength of copper, plastic deformation of the bumps and pads ensues, leading to partial collapse of the bumps. The pictures in Figure 2 show a scanning acoustic microscopy (SEM) analysis of micro-bumps before and after thermocompression with 365 MPa applied pressure. A vertical collapse of the bumps can be clearly observed, with a decrease of the bump height by ~3µm, resulting from deflection of the bumps and landing pads. Further, no significant lateral expansion of the bumps can be noted, with an increase in bump diameter by less than 1 µm. This bonding technology thus addresses major challenges faced by ultra-short interconnections due to non-

Figure 1. Test vehicle layout showing daisy chains for yield and reliability evaluation: 5 mm x 5mm die (left) and 20 mm x 20 mm substrate with probing pads (right).

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coplanarities arising from bump and pad height variations and substrate warpage by offsetting ~3 µm non-coplanarities with no risk of lateral bridging.

Figure 2. SEM pictures of Cu micro-bumps (a) as plated, (b) after thermocompression bonding in PoR conditions [13].

The SEM picture in Figure 3 shows the cross-section of a Si die (top) on a polymer-laminated glass interposer (bottom) after ion-milling. The pre-applied underfill fills the gap between die and interposer without any apparent voids. Both Cu bumps and landing pads are plastically deformed. The lack of a distinct bonding interface indicates the formation of a metallurgical bond between bumps and pads over a large portion of their surfaces. Pressure-induced local plastic strain brings the thin immersion Au layers from the ENIG surface finish into intimate contact, enabling solid-state interdiffusion of the Au atoms. The combination of 4 interdependent factors – oxide-free Cu surfaces; pressure to reduce diffusion distances and accelerate interdiffusion by enhancing dislocation and lattice defect densities at the interface; temperature to increase the diffusion rate; and time for interface recrystallization – leads to the formation of the observed metallic bond. Nickel acts as a barrier layer to prevent diffusion of Au into Cu, eliminating the risk of forming Kirkendall voids. The pre-applied underfill enhances the die shear strength by introducing compressive stress in the structure due to polymer shrinkage, and also prohibits oxidation and degradation of the Cu interconnections due to its built-in fluxing action. In addition, it may fill in any gaps, as a transient liquid, that exist between the two surfaces. The bonding mechanism is analyzed and detailed in [13].

Figure 3. SEM picture of the ion-milled cross-section of a Si test die, assembled on an ultra-thin glass interposer with thermocompression bonding using a pre-applied underfill.

Considering the temperature-dependence of yield strength of metals, maximum plastic deformation of bumps and pads is permanently and instantaneously achieved upon reaching the bonding peak temperature, initiating metallic bonding. A few

seconds is enough to create a metallurgical bond, as confirmed by the SEM pictures in Figure 4 of two ion-milled cross-sections of Cu interconnections formed at 200°C – 365 MPa for 60s and 3s, respectively.

Figure 4. SEM pictures of ion-milled cross-sections of Cu interconnections formed by thermocompression bonding at 200°C – 365 MPa applied for (a) 60s (PoR conditions) and (b) 3s.

Temperature-dependence of polymer curing: Curing kinetics of the pre-applied underfill is another factor that constrains the bonding time at peak temperature. While it is not necessary to achieve full cure of the material during assembly, the bonding pressure can only be released after polymerization initiation. The graph in Figure 5 illustrates the temperature-dependence of the curing behavior of epoxy, given as an example, as most BNUF, NCF or NCP are epoxy-based materials. The curing rate increases with temperature and a shorter time is required to kick off the hardening phase at a higher temperature. Temperature impacts the curing kinetics with an exponential Arrhenius-type relation rather than a simple linear dependence. For instance, while BNUF polymerization starts after only 3s at 210°C, 10s are required at 190°C. A decrease in temperature by 10% thus leads to a 3x increase of the time under the thermocompression tool, dramatically impacting the assembly throughput. The polymer material properties should subsequently be optimized to enable fast initiation of the hardening phase at temperatures below 200°C.

Figure 5. Illustration of the temperature-dependence of the curing behavior in an epoxy-based system.

Once the polymer reaches a gel-like firmness, the bonding pressure can be released. A batch-type post-cure might be necessary to reach the polymer solid state. The BNUF used here requires further baking for 3h at 165°C in air. This additional curing phase also enhances joint recrystallization, improving the quality of the metallurgical bond.

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High-throughput Die-to-Panel Assembly Demonstration Apart from large 2.5D high-performance interposers

where the dies are mounted on singulated units for cost and yield reasons, assembly in industry-standard low- to high-volume lines is usually performed on a substrate strip to facilitate BGA balling for board-level interconnections, for both traditional flip-chip bonding or low-pressure thermo-compression Cu pillar with solder cap technology. In the latter case, two strategies can be considered: (1) tacking the die by pre-cure of a non-conductive paste followed by gang bonding where pressure is applied on multiple dies at once to reflow the solder and fully cure the NCP; (2) bonding of each die individually using a thermocompression tool, potentially followed by a batch-type process to cure the polymer. Although the first scenario could potentially have higher throughput since the bonding time is now divided by the number of dies on a strip, it is more difficult to implement as it requires pressure uniformity on a strip-scale, which can only be achieved with high-accuracy equipment with micron-scale parallelism between the press plates. The second approach involves a specific assembly sequence where the heat transfer is dominated by the thermocompression flip-chip tool. The plate onto which the substrate is placed is maintained at a constant temperature below laminate Tg, to limit substrate warpage and to prevent any degradation of the joints of the mounted components during subsequent assemblies. Unidirectional heat transfer may jeopardize uniform flowability and polymerization of the pre-applied polymer (NCP, BNUF) during bonding as this class of materials is essentially thermally insulating. Thin dies with ultra-short interconnections resulting in a smaller gap and thinner polymer layer are thus desirable for strip-level thermocompression assembly.

Figure 6. Illustration of panel-level assembly capability: 6” x 6” glass panel accommodating 25 dies, sitting on the flip-chip bonder stage after assembly.

A panel-level process was developed using a Finetech

Matrix semi-automatic flip-chip bonder with a placement accuracy of 3 µm and controllable temperature and force profiles. The stage can accommodate a 6” x 6” substrate size as illustrated in Figure 6, and has thus a very low heat capacity with a temperature ramp rate limited to 2°C/s. A customized 6 mm x 6 mm vacuum-locked spring gimbal tool head, enabling pre-leveling of the die, was used to prevent any

die tilt during assembly. BNUF was first dispensed on a 3” x 5” organic substrate that can accommodate 15 dies, and B-staged. The substrate was then placed onto the stage and maintained at 70°C during the entire assembly sequence to slightly decrease BNUF viscosity to prevent misalignment of the die during placement. Each die is eventually picked, placed and bonded at 210°C applied for 3s. The temperature ramp rate being limited to 6°C/s for the tool head, the assembly cycle for a single chip lasts ~90s, but the 365 MPa bonding pressure is released before the cool-down phase. After assembly of all dies, the panel is subjected to an oven cure at 165°C for 3h in air to ensure that the BNUF material would reach its final solid stage.

Interconnection Yield Characterization The assembly process with heating only from the top was

first validated at substrate-unit level. The resistances of the unit daisy chains were measured prior to oven cure, to assess the interconnection yield after thermocompression bonding. All daisy chains were yielded with resistance values within the expected range (~1–4 ). The samples were then mounted in epoxy molds and polished to prepare them for cross-section analysis. The optical images displayed in Figure 7 confirm adequate joint quality and underfilling.

Figure 7. Optical image of cross-section of assembled Si die on organic substrate with Cu interconnections formed by thermocompression bonding with heating from die side only at 210°C, 365 MPa with a 3s dwell time at peak temperature.

The first panel-level demonstration was conducted on the 3” x 5” organic substrate of Figure 8 (a) onto which 15 Si dies were assembled by thermocompression bonding at 210°C, maintained for 3s and an applied force of 200 N, using the process described in the previous section. Additional assembly trials were performed at a lower temperature – 190°C for 10s – on a smaller substrate with 4 dies introduced in Figure 8 (b). The assembled structures were screened by X-ray analysis and C-SAM acoustic imaging to evaluate the alignment accuracy and quality of underfilling, respectively. Close-up pictures of a typical sample are displayed in Figure 9 for both bonding conditions, confirming that the placement accuracy is within the 3 µm tolerance of the flip-chip bonder.

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Figure 8. Optical picture of organic substrate with multiple 5mm x 5mm Si dies assembled by panel-level thermo-compression bonding with 365 MPa applied pressure and at (a) 210°C for 3s, and (b) 190°C for 10s.

Figure 9. Close-up X-ray imaging of a typical die assembled at panel-level on organic substrate with (a) 210°C for 3s, and (b) 190°C for 10s, showing accurate alignment.

No voiding was observed by C-SAM analysis of the assembled panels, as shown in Figure 10. Good quality underfilling was thus obtained despite the unidirectional heat transfer, due to the unique flowability and curing properties of the BNUF material developed by Namics Corporation.

Figure 10. C-SAM imaging of assembled structures with (a) 210°C for 3s, and (b) 190°C for 10s showing void-free underfill layer at panel and unit levels.

The interconnection yield was assessed by DC measurements of the daisy chains resistance after

thermocompression bonding and post-cure. The number of functional chains, over the 16 designed, is reported for each individual unit in Tables 1 and 2, respectively corresponding to each bonding conditions. Apart from one unit with only 50% functional structures, which was found to be due to poor alignment, the yield exceeded 75% for all 18 assembled units, validating the process conditions.

Table 1. Electrical yield evaluation of the 15 as-bonded dies assembled on a 3” x 5” organic substrate at 210°C for 3s.

Number of functional daisy chains / 16 14 14 16 14 15 14 13 13 14 12 16 12 16 14 8

Table 2. Electrical yield evaluation of the 4 as bonded dies assembled on a 2” x 2” organic substrate at 190°C for 10s.

Number of functional daisy chains / 16 14 16 14 15

Figure 11. 3D microscopy images of a typical Si test die showing bump height variations of (a) ~3 µm and (b) ~9 µm across 3 and 7 Cu interconnections, respectively.

Possible causes for a non-perfect yield include die tilt, bump non-coplanarities and substrate warpage. As no specific orientation was noticed in the failed daisy chains, and no significant die tilt was observed in the cross-sections, flatness and parallelism of the bonding tool head were ruled out as the causes for yield loss. The bump co-planarity was analyzed

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with 3D microscopy on a Si die randomly picked from the wafer. The results are summarized in Figure 11, with large discrepancies in the measured bump height across a die, up to 9 µm. These height variations exceed the non-coplanarities that can be offset by pressure-induced plastic deformation, resulting in non-land of the bumps adjacent to a larger one. This directly translates into an open-circuit and a nonfunctional daisy chain reading. Optimization of the Cu electrolytic bath conditions and plating densities is required for enhanced bump height uniformity and optimum interconnection yield.

Conclusions This paper demonstrated, for the first time, an innovative

low-temperature, ultra-fast, die-to-panel Cu interconnection and assembly process, compatible with standard thermocompression bonding tools. The bonding mechanism is metallurgical in nature as confirmed by interface characterization. The main limiting factor in reducing the bonding time further was found to be the hardening of the pre-applied polymer, which is highly temperature-dependent. Two sets of temperature and time for which the BNUF exhibited initial polymerization – 210°C for 3s and 190°C for 10s – were selected for initial trials. A panel-level assembly sequence was developed and demonstrated with heat-transfer from the die side exclusively. Preliminary trials were conducted on 2” x 2” and 3” x 5” organic substrates accommodating 4 and 15 Si dies with Cu interconnections at 100 µm pitch, respectively. Good alignment and underfilling quality were achieved. The interconnection yield was found to exceed 75%, excessive non-coplanarities of bumps accounting for the failed daisy chains. These preliminary results are a promising proof-of-concept demonstration of the Georgia Tech PRC patented technology. Further optimization of the bumping plating process is required to achieve better interconnection yield. Further reduction of the bonding time, combined with decreasing the thermocompression pressure, will bring this advanced interconnection process to a more manufacturable level, offering a compelling solution for the future generations of ultra-fine pitch high-performance systems, starting a new era without solders.

Acknowledgments This research is supported by the Interconnections and

Assembly (I&A) program at Georgia Tech PRC. The authors would like to thank the full members and supply chain partners for their funding and intellectual support, in particular Atotech for their plating chemistries, and Namics Corporation who specifically developed the underfill material for the targeted application. The authors are very grateful to Anne Matting and Anna Stumpf, interns from TU Dresden, for their support with fabrication and cross-sectioning. Finally, special thanks to Xian Qin for her help with 3D microscopy, and Saumya Gandhi and Florian Nebe for their polishing skills.

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