A NEW COMPENSATION TECHNIQUE FOR ENHANCING POWER

SUPPLY REJECTION RATIO IN TWO-STAGE CMOS OPERATIONAL

AMPLIFIERS

BY

SRI HARSH PAKALA, B.Tech

A dissertation submitted to the Graduate School

in partial fulfillment of the requirements

for the degree

Master of Sciences, Engineering

Specialization in: Electrical Engineering

New Mexico State University

Las Cruces, New Mexico

February 2012

“A New Compensation Technique for Enhancing Power Supply Rejection Ra-

tio in Two-Stage CMOS Operational Amplifiers,” a dissertation prepared by

Sri Harsh Pakala in partial fulfillment of the requirements for the degree, Mas-

ter of Sciences has been approved and accepted by the following:

Linda LaceyDean of the Graduate School

Chair of the Examining Committee

Date

Committee in charge:

Dr. Paul M. Furth, Associate Professor, Chair.

Dr. Jaime Ramirez-Angulo, Professor.

Dr. Abbas Gassemi, Professor.

ii

DEDICATION

Dedicated to my mother Gayatri, father Gopal Mani, sister Jyotsna, my

grandmother Suryakantham.

iii

ACKNOWLEDGMENTS

I would like to thank my parents Gayatri Kappaguntala and Hara Gopal

Mani Pakala for their support and their confidence. I am who I am because of the

way they brought me up. I would like to thank my sister Sirisha Sri Jyotsna Gorti

and my brother-in-law Gorti Narasimha Murty for being there for me during a

turbulent summer in 2010. I would like to thank my grandmother Suryakantham

Pakala for being the foundation stone for my family. Our family is in a good

position by the grace of the Almighty God and due to her perseverance.

I am forever indebted to my advisor Dr. Paul M. Furth. It is due to

him that I found the interest in Microelectronics. His teaching methods and

his treatment of students encouraged me to study harder during my graduate

program. Dr. Paul M. Furth also is a great human being and I would like to

thank him for inviting us to his residence for over a year during friday evenings.

I learnt a lot about him and his family during that time and I thank him for

trusting us and sharing his life with his students.

Great appreciation to Dr. Jaime Ramirez-Angulo for being a member of

my thesis committee. I like him as a professor and also as a human being. I learnt

a lot from all his courses and It woud be a dream to perform research with him.

I would like to thank Dr. Abbas Ghasemmi for accepting my request to

be a member of my thesis committee. He was the first professor to offer financial

support to me during the second semester. That greatly helped me as an Interna-

iv

tional student. He is an angel in NMSU and I am lucky to know such a brilliant

man.

Thanks to my cousins, Su,Teju,Sidhu,Puppy,Chelli,Keerthi and all my rel-

atives.

I would like to thank my undergraduate friends, Goutham, Vamsi, Swa-

roop, Santhosh, Anil, Revanth, Murali, Sushma, Saranya, Sherin, Rachana and

Priyanka.

I would also like to mention my buddies for life, Avinash, Rohini, Sharada,

Akhilesh and Shilpa. We have been a close-knit group for a decade and I shall

always miss not being with them.

I would like to thank my seniors in las cruces, Rajesh Satyavada, Chaitanya

mohan, Harish, Ramesh, Venkat, Annajirao and Punith. They taught me Cadence

and also many vital concepts (esp. Punith and his night lessons).

Thanks to my friends in las cruces, Venkat Harish Nammi, Nitya, Srikanth,

Vamshi, Abhinav, Raghu, Hardik, Vineet, Krishnakanth, Vinush, Tapaswvy, Chan-

dana, Chayya, Divya, Paari, Rahul, Santosh, Saiprasad, Srikar, Aditya, Mahesh,

Madhu, Akhil, Sudhir. I would like to thank all the members of Indian Student

Association (ISA) for supporting me.

v

VITA

Education

2005 - 2009 B.Tech. Electronics and Communications Engineering,JNTU, India

2009 - 2012 MS. in Electrical Engineering,New Mexico State University, USA - GPA 3.64/4.0

Awards and Achievments

2011 - 2012 Outstanding Graduate Assistant Award, NMSU,USA.

2011 - 2012 Nominated for Outstanding Graduate Student Award, NMSU,USA.

Experience

Graduate Research Assistant, Arrowhead Center, Entrepreneurship Institute, NMSU,Fall-2010, Spring 2011, Fall 2011, Spring 2012Graduate Research Assitant, Klipsch School of Electrical and Computer Engineer-ing, NMSU, Spring-2010

vi

ABSTRACT

A NEW COMPENSATION TECHNIQUE FOR ENHANCING POWER

SUPPLY REJECTION RATIO IN TWO-STAGE CMOS OPERATIONAL

AMPLIFIERS

BY

SRI HARSH PAKALA, B.Tech

Master of Sciences, Engineering

Specialization in Electrical Engineering

New Mexico State University

Las Cruces, New Mexico, 2012

Dr. Paul M. Furth, Chair

February, 2012

Thomas and Brown Hall, TB 207, 1:30 PM

CMOS operational amplifiers are used in various applications such as: low-

dropout voltage regulators, audio amplifiers, and filters. To ensure stability, fre-

quency compensation techniques are required. In most electronic devices, ripple

noise in supply line is unavoidable. Hence a robust noise performance at high

frequencies is required. A new compensation technique is applied to a two-stage

CMOS operational amplifier. The compensation is established by a capacitor con-

nected between the output node and the source node of the input differential am-

vii

plifier. The technique allows better performance in terms of unity-gain frequency

and Power Supply Rejection Ratio (PSRR) when compared to existing compensa-

tion techniques, such as Miller and cascode compensation. Operational amplifiers

using Miller, cascode and the proposed compensation methods were fabricated in

a 0.5 µm 2P3M CMOS process. The circuits operate at a total quiscent current

of 90µA with ±1.5V power supplies when driving a load of 20pF||20kΩ. Experi-

mental results show that the proposed compensation scheme increases unity-gain

frequency by 25% and improves PSRR from the positive rail by 22 dB and 26

dB at 3 MHz when compared to Miller and cascode compensation techniques,

respectively.

viii

TABLE OF CONTENTS

LIST OF TABLES xii

LIST OF FIGURES xiii

1 INTRODUCTION 1

1.1 Purpose of Work . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 Unique Contributions . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.3 Organization of Thesis . . . . . . . . . . . . . . . . . . . . . . . . 4

2 LITERATURE REVIEW 5

2.1 Two-Stage Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Compensation Techniques . . . . . . . . . . . . . . . . . . . . . . 7

2.2.1 Miller Compensation . . . . . . . . . . . . . . . . . . . . . 7

2.2.2 Cascode Compensation . . . . . . . . . . . . . . . . . . . . 9

2.2.3 Other compensation techniques . . . . . . . . . . . . . . . 11

2.3 Power Supply Rejection Ratio . . . . . . . . . . . . . . . . . . . . 14

2.3.1 Miller Compensation PSRR Analysis . . . . . . . . . . . . 14

2.3.2 Cascode Compensation PSRR Analysis . . . . . . . . . . . 16

2.3.3 Blakiewicz’s compensation PSRR Analysis . . . . . . . . . 17

3 DESIGN AND SIMULATIONS 19

ix

3.1 Two-Stage Opamp: Design I . . . . . . . . . . . . . . . . . . . . . 19

3.1.1 Operation of Design I . . . . . . . . . . . . . . . . . . . . . 20

3.2 Two-Stage Opamp: Design II . . . . . . . . . . . . . . . . . . . . 21

3.3 Two-Stage Opamp: Design III . . . . . . . . . . . . . . . . . . . . 23

3.3.1 Op-amp Gain . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.3.2 Existing Compensation Techniques . . . . . . . . . . . . . 26

3.3.3 Proposed Compensation Strategy . . . . . . . . . . . . . . 26

3.3.4 Small-Signal Analysis . . . . . . . . . . . . . . . . . . . . . 27

3.4 Power Supply Rejection Ratio Analysis . . . . . . . . . . . . . . . 28

3.4.1 Miller compensated Two-stage opamp design III’s PSRRAnalysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.4.2 Cascode compensated Two-stage opamp design III’s PSRRAnalysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.4.3 Tail compensated Two-stage opamp design III’s PSRR Anal-ysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.5 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.5.1 AC Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.5.2 Transient Analysis . . . . . . . . . . . . . . . . . . . . . . 37

3.5.3 Bandwidth Analysis . . . . . . . . . . . . . . . . . . . . . 38

3.5.4 Power-Supply Rejection Ratio . . . . . . . . . . . . . . . . 39

4 EXPERIMENTAL RESULTS 51

4.1 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.2 Test Apparatus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4.3 Hardware Test Results . . . . . . . . . . . . . . . . . . . . . . . . 54

5 DISCUSSION AND CONCLUSION 60

x

5.1 Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

APPENDICES 62

A. Test Document 63

B. Maple 73

REFERENCES 102

xi

LIST OF TABLES

3.1 Device Sizings for Design I Two-stage opamps . . . . . . . . . . . 21

3.2 Device Sizings for Design II Two-stage opamps . . . . . . . . . . . 22

3.3 Device Sizings of Design III Two-stage opamps . . . . . . . . . . . 25

3.4 Poles and Zeros Equations for Design III Two-stage opamp withMiller compensation . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.5 Poles and Zeros Equations for Design III Two-stage opamp withcascode compensation . . . . . . . . . . . . . . . . . . . . . . . . 29

3.6 Poles and Zeros Equations for Design III Two-stage opamp withtail compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.7 Location of PSRR Poles and Zeros for Miller compensated Design III 33

3.8 Location of Poles and Zeros PSRR Cascode . . . . . . . . . . . . 35

3.9 Location of Poles and Zeros PSRR Tail . . . . . . . . . . . . . . . 35

3.10 Simulated Results for Design I two-stage opamps . . . . . . . . . 48

3.11 Simulated Results for Design II two-stage opamps . . . . . . . . . 49

3.12 Summary of Results with a supply voltage of ±1.5V of Design IIITwo-stage Opamp . . . . . . . . . . . . . . . . . . . . . . . . . . 50

4.1 Summary of Measured Results of Design III Opamps with a supplyvoltage of ±1.5V while driving a load of 20kΩ||20pF . . . . . . . 59

5.1 Summary of Measured Results of Design III Opamps with a supplyvoltage of ±1.5V while driving a load of 20kΩ||20pF . . . . . . . 61

xii

LIST OF FIGURES

1.1 Architecture of 2-stage CMOS opamp using Miller compensation. 2

1.2 Cascode compensation small signal diagram. . . . . . . . . . . . . 3

2.1 Basic two-stage opamp using Miller compensation. . . . . . . . . . 7

2.2 Miller compensation. . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Miller compensation with nulling resistor. . . . . . . . . . . . . . . 9

2.4 Cascode compensation. . . . . . . . . . . . . . . . . . . . . . . . . 10

2.5 Cascode compensation small signal diagram. . . . . . . . . . . . . 11

2.6 Blakiewicz compensation. . . . . . . . . . . . . . . . . . . . . . . 12

2.7 Blakiewicz compensation small signal diagram. . . . . . . . . . . . 13

2.8 PSRR small signal model for basic two-stage opamp with Millercompensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.9 PSRR small signal model for basic two-stage opamp with cascodecompensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.10 PSRR small signal model for basic two-stage opamp with Blakiewicz’scompensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1 Schematic of Design I two-stage opamp. . . . . . . . . . . . . . . 20

3.2 Schematic of Design II two-stage opamp. . . . . . . . . . . . . . . 21

3.3 Schematic of Design III two-stage operational amplifier illustratingMiller, cascode, and proposed compensation techniques. . . . . . . 24

3.4 Small signal model of Fig. 3.3 using Miller compensation. . . . . . 27

xiii

3.5 Small-signal model of Fig. 3.3 using cascode compensation. . . . . 29

3.6 Small-signal model of Fig. 3.3 tail compensated two-stage opamp. 30

3.7 Small signal diagram of Miller scheme for PSRR analysis. . . . . . 31

3.8 Small signal diagram of Cascode scheme for PSRR analysis. . . . 34

3.9 Small signal diagram of tail scheme for PSRR analysis. . . . . . . 34

3.10 AC analysis test bench of two-stage operational amplifiers . . . . 36

3.11 Frequency plots of Design I two-stage opamps with Miller Compen-sation and proposed Compensation. . . . . . . . . . . . . . . . . . 37

3.12 Frequency plots of Design II two-stage opamps with Miller Com-pensation, Cascode Compensation and proposed Compensation. . 38

3.13 Frequency plots of Design III two-stages opamp with Miller com-pensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.14 Frequency plots of Design III two-stages opamp with cascode com-pensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.15 Frequency plots of Design III two-stages opamp with proposed com-pensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.16 Transient analysis test bench in inverting configuration. . . . . . . 41

3.17 Transient output of Design I two-stage opamps with Miller com-pensation and proposed compensation schemes. . . . . . . . . . . 42

3.18 Transient output of Design II two-stage opamps with Miller com-pensation, cascode and proposed compensation schemes. . . . . . 43

3.19 Transient outputs of Design III two-stage opamps with Miller, cas-code and proposed compensation techniques. . . . . . . . . . . . . 44

3.20 Test bench for measuring PSRR. . . . . . . . . . . . . . . . . . . 44

3.21 Frequency plots of PSRR for Design I opamps using Miller andproposed compensation schemes. . . . . . . . . . . . . . . . . . . . 45

3.22 Frequency plots of PSRR for Design II two-stage opamps usingMiller, cascode and proposed compensation schemes. . . . . . . . 45

3.23 Frequency plots of PSRR for Design III two-stage opamp usingmiller compensation technique. . . . . . . . . . . . . . . . . . . . 46

xiv

3.24 Frequency plots of PSRR for Design III two-stage opamp usingcascode compensation technique. . . . . . . . . . . . . . . . . . . 46

3.25 Frequency plots of PSRR for Design III two-stage opamp usingproposed compensation technique. . . . . . . . . . . . . . . . . . . 47

3.26 Frequency plots of PSRR for Design III two-stage opamp usingproposed compensation technique. . . . . . . . . . . . . . . . . . . 47

4.1 Overall chip layout. . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.2 Layout of design I two-stage opamp with Miller compensation.. . . 52

4.3 Layout of design I two-stage opamp with Tail compensation. . . . 53

4.4 Layout of design II two-stage opamp with Miller compensation. . 53

4.5 Layout of design II two-stage opamp with Cascode compensation. 54

4.6 Layout of design II two-stage opamp with Tail compensation. . . . 54

4.7 Layout of design III two-stage opamp with Miller compensation. . 55

4.8 Layout of design III two-stage opamp with Cascode compensation. 55

4.9 Layout of design III two-stage opamp with Tail compensation. . . 55

4.10 Hardware waveforms of Design III two-stage amplifiers with Miller,cascode and tail compensation schemes. . . . . . . . . . . . . . . . 56

4.11 Hardware PSRR frequency response outputs of Design III two-stageamplifier with Miller, cascode and tail compensation schemes. . . 57

4.12 Hardware PSRR frequency response outputs of Design III two-stageamplifier with cascode scheme. . . . . . . . . . . . . . . . . . . . . 57

4.13 Hardware PSRR frequency response outputs of Design III two-stageamplifier with tail scheme. . . . . . . . . . . . . . . . . . . . . . . 58

4.14 Hardware PSRR frequency response outputs of Design III two-stageamplifier with tail scheme. . . . . . . . . . . . . . . . . . . . . . . 58

xv

Chapter 1

INTRODUCTION

CMOS opamps are the most ubiquitous analog blocks in analog and mixed-signal

systems [1]. Due to their versatile functionality, they are utilized in most of the

present-day electronic systems. Operational amplifiers find use in many applica-

tions, such as buffers, filters, error amplifiers and power amplifiers, to name a few.

Most opamps are designed based on a set of specifications. Depending on the

application, opamps are designed to exhibit a few desired features, such as high

gain, low power, high bandwidth, class-AB operation, high slew rate, and high

power supply rejection ratio. Due to design trade-offs involved in analog circuit

design, all of these desired features may not be met simultaneously.

When CMOS processes were more friendly to analog circuitry, one-stage

opamps were sufficient, as they exhibited high gain. Though the basic one-stage

opamp has many advantages, such as inherent stability without compensation,

it isnt preferred because of low gain with modern technologies and also because

of load driving constraints, as it can only drive capacitive loads. Though trends

indicate the usage of three or more stages in cascade to form multi-stage opamps,

they also result in greater power consumption and need for complicated frequency

compensations for achieving stability. Therefore, if the specifications indicate low

power consumption and low area, two-stage opamps can be selected. Hence, two-

stage opamps are preferred, due to their reasonable gain, relatively less complex

compensation schemes and also because they can drive both capacitive and resis-

1

tive loads. They are widely used in analog systems due to their many features such

as: simple biasing, large output-voltage swing and improved noise performance [2].

AV1Vin

Vout+

-

-AV2

CM

R1C1 RoutCout

V1+

-

Figure 1.1: Architecture of 2-stage CMOS opamp using Miller compensation.

In general, frequency compensation is required for ensuring closed-loop

stability [1]. The simplest frequency compensation technique, shown in Fig. 1.1,

is achieved by connecting a compensation capacitor CM between the output nodes

of the two stages, thus employing the Miller effect. In Miller compensation, a

nulling resistor is also required in order to move a Right-Half-Plane (RHP) zero

to the Left-Half-Plane (LHP) [3]. Another technique, known as Ahuja or cascode

compensation [4], depicted in Fig. 1.2, utilizes a compensating capacitor between

the source node of a cascode transistor of the first stage and the output node.

Comparing Miller to cascode compensation, the major advantages of cascode are:

increased bandwidth and improved PSRR [5].

2

AV1Vin

Vout+

-

-AV2

CC

R1C1 RoutCout

V1

gmC

+

-

gmC

1

VY

Figure 1.2: Cascode compensation small signal diagram.

In most portable electronic devices, when the operating voltage is supplied

by switched-mode power supplies, ripple noise in the supply line is unavoidable.

In many portable communications devices, which consist of transceiver circuits

operating at high frequencies, the supply ripple causes stability degradation at

the frequency of transmission [6]. Hence, for such applications, better noise per-

formance at higher frequencies is required, which Miller and cascode techniques

may fail to provide.

1.1 Purpose of Work

1. To explore and demonstrate a new frequency compensation technique for

two-stage CMOS opamps.

2. To explore any advantages that could arise by using the proposed new com-

pensation technique.

3

1.2 Unique Contributions

1. Introduced a new frequency compensation technique for two-stage CMOS

opamps.

2. Improved PSRR from the positive supply line.

3. Increased Unity-Gain Frequency achieved through utilization of proposed

compensation technique.

4. Performed AC small signal modeling and pole/zero analysis.

5. Performed PSRR small signal modeling and pole/zero analysis.

1.3 Organization of Thesis

This thesis presents the development of a novel frequency compensation

technique which greatly improves the PSRR characteristic of a two-stage opamp.

Theoretical analysis for verifying the simulated results was developed. Chapter 2

provides information about the existing compensation techniques, their small sig-

nal behavior and PSRR performance. Chapter 3 presents the different topologies

to which the compensation schemes were implemented. The different topogolies

which were explored during the design process are progressively complex design

variants. Hence, the best design of them, Design III two-stage opamps are dis-

cussed in detail. Small signal analysis and PSRR small signal analysis for Design

III and simulation results for all eight designs are presented in detail in Chapter 3.

Chapter 4 contains the test chip results measured and compared with the derived

theoretical values. The thesis is concluded in Chapter 5, along with discussion

about future work. Appendices contain detailed description of test procedures,

MAPLE analysis.

4

Chapter 2

LITERATURE REVIEW

This chapter discusses the work done in the literature. The different types of

compensation techniques used for two-stage amplifiers are discussed, as well as

models used for analyzing power-supply rejection.

2.1 Two-Stage Amplifiers

Two-stage operational amplifiers are widely used in analog systems due

to their many features such as: simple biasing, large output-voltage swing and

better noise performance [2]. Two-stage opamps, compared to single-stage which

only drive capacitive loads, have the ability to drive capacitve and resistive loads.

In general, frequency compensation is required for ensuring closed-loop stability

of two-stage amplifiers [1]. The simplest frequency compensation technique is

achieved by connecting a compensation capacitor CM between the output nodes

of the two stages, thus employing the Miller effect. In Miller compensation, a

nulling resistor is also required in order to move a Right-Half-Plane (RHP) zero

to the Left-Half-Plane (LHP) [3]. Another technique, known as Ahuja or cascode

compensation [4] utilizes a compensating capacitor between the source node of a

cascode transistor of the first stage and the output node. Comparing Miller to

cascode compensation, the major advantages of cascode are: increased bandwidth,

wider range of capacitive load, and improved PSRR [5].

For an operational amplifier to be stable, the gain must be below unity

before the phase response reaches -180o. The difference between -180o and the

5

value of the phase response at unity-gain frequency is termed as phase margin. It

is an important term used to determine the stability of an opamp. A fast transient

response with no ringing translates to a phase margin value of approximately 60o.

A phase margin of 40o translates to a higher amount of ringing in the time-domain.

The frequency response of an operational amplifier is determined by the

low-frequency gain, pole/zero locations and the number of poles/zeros. These

are determined by the circuit topology, values chosen for each circuit element,

and number of stages used in an opamp. Poles and zeros are classified based

on their effects on the magnitude and phase responses. The magnitude response

decreases at a rate of -20dB/decade and the phase response drops to 90o, for

LHP poles. RHP poles make amplifiers unstable. For zeros, if the magnitude

response increases at a rate of 20dB/decade and the phase response goes up by

90o, then it is termed as a LHP zero. RHP zeros increase the magnitude response

by 20dB/decade while decreasing the phase response by 90o and tend to decrease

stability of a circuit.

Due to the positive effects of LHP zeros, most frequency compensation

techniques concentrate on creating LHP zeros which are either placed to can-

cel LHP poles or increase the phase margin. Pole-splitting is another important

feature of compensation networks. Through this method, the dominant pole is

pushed to lower frequencies and the non-dominant pole is pushed to higher fre-

quencies.

Multi-stage amplifiers are those which have two or more stages. They

are needed as the gain/stage is getting lower with each technology node. The

complexity of the compensation network increases with the number of cascaded

stages [7]. Different compensation techniques are used to improve the stability

6

and some of them are discussed in the next section. In this work, we will restrict

ourselves to two-stage amplifiers.

2.2 Compensation Techniques

Amplifiers are compensated in different manners, depending on the number

of stages. Miller compensation and Cascode compensation are used in amplifiers

with two or more cascaded stages.

M2M1VIN+VIN-

V1

M4M3

VBN

M 5

M 7

M6

CM

2 Ib

VDD

VSSFirst Stage Output Stage

VOUT

m=2

VBN

Figure 2.1: Basic two-stage opamp using Miller compensation.

2.2.1 Miller Compensation

Miller compensation is widely used and discussed in the literature [8, 9,

10, 11]. It is implemented in a two-stage opamp as shown in Fig. 2.1. The

first stage consists of two NMOS transistors M1 and M2, connected to a PMOS

current-mirror load of two transistors M3 and M4. The second stage consists of a

common-source stage realized through PMOS transistor M7. A capacitor CM is

connected between the output node and the internal node V1. This results in pole

splitting; the dominant or low frequency pole at the output of the first stage moves

7

AV1Vin

Vout+

-

-AV2

CM

R1C1 RoutCout

V1+

-

Figure 2.2: Miller compensation.

to lower frequencies and the non-dominant or high frequency (with respect to the

first pole) pole at the output stage moves to higher frequencies. The existence of

a feed-forward path from V1 to VOUT creates a RHP zero. A RHP zero increases

the gain by 20dB/decade and drops the phase by 90o. Due to this negative trait,

RHP zeros must be pushed to extremely high-frequencies, as they tend to decrease

the phase margin. The small signal diagram of this implementation is shown in

Fig. 2.2. The equations of two LHP poles are:

ωP1 =1

AV 2 ·R1 · CM

. (2.1)

ωP2 =AV 2

(R1 +RM) · COUT

. (2.2)

8

AV1Vin

Vout+

-

-AV2

CM

R1C1 RoutCout

V1+

-

RM

Figure 2.3: Miller compensation with nulling resistor.

To remove the RHP zero, Miller capacitor with a nulling resistor in series is used

as shown in Fig 2.3. The equation of the zero becomes

ωZ1 =1

CM · ( 1gm7−RM)

. (2.3)

If the value of the resistor RM is equal to 1gm7

, where gm7 is transconductance of

second stage, then the zero moves to infinity. If RM increases, beyond a value

of 1gm7

, then the RHP zero moves to the LHP, which can be used to improve the

phase margin and increase stability.

2.2.2 Cascode Compensation

The cascode compensation scheme helps in increasing the stability, phase

margin and bandwidth of an amplifier through a feedback capacitor connected

in series with a current-buffer. Instead of an extra current-buffer circuit, the

cascoded transistor is used as the current-buffer as shown in Fig. 2.4. The cascoded

9

M2M1VIN+VIN-

V1

VY

M4

M6M5

M3 CP

M 7

M 8

CC

VDD

VSS

First Stage Output Stage

VOUT

Ib

VBNVBN

M 9

2 Ib

V

Figure 2.4: Cascode compensation.

transistor is a common-gate amplifier which has a positive gain of gm4R1, from the

source to drain terminals of transistor M4. The input impedance of the cascode

transistor M4 is 1gm4

as proposed in [12]. Therefore the overall feedback is negative.

The small signal diagram of cascode compensation is shown in Fig. 2.5.

The effect of first stage is modeled as voltage controlled current source of value:

gm1Vin. The impedance to ground at the output of first stage node V1 are R1 and

C1 in parallel. The effect of the cascode transistor M4 is modeled as gm4VY . The

effect of the second stage is given by: gm7V1. The output impedances are Rout

and Cout in parallel. The compensation capacitor CC is connected between nodes

VY and Vout.

The dominant pole in cascode compensation is given by:

ωP1 =1

gm7R2R1CC

. (2.4)

10

The non-dominant pole is given by:

ωP1 =gm7CC

C1(CC + CL). (2.5)

The first LHP zero through cascode compensation is given by:

ωZ1 =gm7

CC

(2.6)

where gm7 is the transconductance of second-stage.

+

-

V1

gm7V1

outC

outR

Vout

Vin m4

g1

Cc

C1

R1

VY

gm4VY

Vingm1

Figure 2.5: Cascode compensation small signal diagram.

2.2.3 Other compensation techniques

A new compensation technique was reported in the literature in [13], which

improves the PSRR characteristic in a two-stage opamp and is shown in Fig. 2.6.

Instead of placing the compensation network between the signal paths of the first

and second stages, the compenstion network is created by using a stage of two

transistors and a compensation capacitor CC . The small signal diagram for this

compensation scheme is shown in Fig. 2.7.

11

M2M1VIN+VIN-

V1

M4M3

VBN

M 5

M 7

M6

CC

2 Ib

VDD

VSSFirst Stage Output Stage

VOUT

VBN

M8

M 9

VB2

Figure 2.6: Blakiewicz compensation.

Generally compensation schemes result in pole splitting and hence band-

width extension, but this technique results in the formation of two dominant

low-frequency poles given by:

ωP1 =1

Av ·R1 · CC

. (2.7)

ωP2 =1

R2 · CL

. (2.8)

A LHP zero is also created at medium frequencies and is given by:

ωZ1 =1

RC · CC

. (2.9)

12

RC

CC

R1C1

V1

gm1VinROutCOut

gm7V1

VOut

Vin

G

+

–

S

gm8V1

Figure 2.7: Blakiewicz compensation small signal diagram.

Due to this unique pole-zero locations, the range of achievable phase re-

sponses by the implemented opamp is limited. Though the authors reason that a

single pole response is achievable thorugh careful design of omegaz1, it is practi-

cally difficult due to the large sizes as seen in 2.7. Phase margin at UGF is 60o

whereas for frequencies below the UGF it is permitted to drop as low as 30o. This

leads to ringing in the time-domain response.

Another scenario possible in this design is when the zero is located between

ωP1 and GB. This results in a non-monotonic phase response, which greatly limits

the operational voltage gain of the circuit. The most important postive trait of this

technique is the drastic reduction of the required value of compensation capacitor

by 12 times when compared to Miller compensation technique.

Another reported method in the literature [14] improves the PSRR by

sacrificing the open-loop gain. In order to decrease the gain from power supply to

the output, they employ a sampled biasing technique. To further attenuate the

13

signal from the supply, the input transistors are sized small, thus resulting in a

low open-loop gain.

2.3 Power Supply Rejection Ratio

PSRR is the ability of an opamp to reject ripple noise from the supply

line. This has become an import figure of merit due to the increased integration

of digital and analog circuit blocks for system-on-chip (SOC) applications. Usually

opamps have relatively high PSRR at low frequencies. But this value degrades

with frequency mainly due to the compensation networks used to stablize them [2,

15, 16, 13]. This is highly undesirable as most analog blocks are integrated with

noise generating fast switching digital blocks in modern mixed-signal SoCs [13].

PSRR at high frequencies is usually improved through increasing the domi-

nant pole or through noise cancellation techniques [13]. In the literature, including

current buffer [17, 12, 18] or voltage buffers [19] in the compensation networks gen-

erally improve the PSRR through increasing the dominant pole location. Other

schemes, such as [14], improve PSRR through specialized biasing techniques and

sacrificing DC gain.

2.3.1 Miller Compensation PSRR Analysis

The small signal model for analyzing PSRR for a basic two-stage opamp

using Miller compensation technique is shown in Fig. 2.8. The effect of change

in current in the first stage due to supply voltage changes is modeled as VDD

ro1,

where ro1 is the intrinsic resistance of the differential NMOS transistor M1 of a

basic two-stage opamp. The parasitic capacitance at the output of first stage is

modeled as C1 and the intrinsic resistance of transistor M2 is labelled as ro2. The

compensation network consisting of: CC and RC is connected between nodes V1

and VOUT . The second stage is modeled as a voltage controlled current source of

14

value: gm7 times the gate-to-source voltage, VDD-V1. The output impedance is

ROUT and COUT .

CC VOUT

o7r

OUTR’ OUT

C

(gm7 VDD-V1)

V

V1

VDD o1rDD

gm1VOUT

o4r

o2r C1

RC

Figure 2.8: PSRR small signal model for basic two-stage opamp with Miller com-pensation.

The PSRR gain at low frequencies is given by:

PSRRDC =gm1ro1ro4gm7ro7

ro2 + ro4. (2.10)

The first dominant pole in PSRR is given by:

ωP1 =(ro2 + ro4)

(ro1ro4gm7ro7CC). (2.11)

The above equations relate to the poor PSRR performance achieved by Miller

compensation. The dominant pole according to eq. 2.11, leads to the degradation

of PSRR performance from that particular low frequency. The effect decreased

impedace at high- frequencies, of the compensation capacitor CC , leads to track-

ing of the gate voltage of transistor M7 to VDD. This results in a poor PSRR

performance from the positive rail.

15

2.3.2 Cascode Compensation PSRR Analysis

The small signal model for analyzing PSRR for a basic two-stage opamp

using cascode compensation technique is shown in Fig. 2.9. The effect of change

in current in the first stage due to supply voltage changes is modeled as VDD

ro1,

where ro1 is the intrinsic resistance of the differential NMOS transistor M1 of a

basic two-stage opamp. The parasitic capacitance at the output of first stage

is modeled as C1 and the intrinsic resistance of transistor M2 is labelled as ro2.

The current through cascode transistor M4 is modeled as ic going into node V1.

The compensation network consisting of: CC is connected between nodes VY and

VOUT . The second stage is modeled as a voltage controlled current source of value:

gm7(VDD − V1). The output impedance is ROUT and COUT .

CC VOUT

o7r

OUTR’ OUT

C

(gm7 VDD-V1)

V

V1

VDD o1rDD

gm1VOUT

VY

(gm4 VY -VDD)

o4r

o6r

o2r C1

Figure 2.9: PSRR small signal model for basic two-stage opamp with cascodecompensation.

16

The PSRR gain at low frequencies is given by:

PSRRDC =g2m1ro2gm7ro6ro7

(gm1ro6 + gm7ro7). (2.12)

The first dominant pole in PSRR is given by:

ωP1 =(gm1ro6 + gm7ro7)

(gm1ro2ro4gm7ro7CC). (2.13)

Though cascode transistor is reported to have a better PSRR performance from

the negative rail, for this work, the performance from the positve rail was explored.

According to eq. 2.12, the DC gain for PSRR is sufficiently high around 80 dB,

but similar to Miller compensation, the dominant pole occurs at a low frequency

due to the gain-multiplied effect on the compensation capacitor CC as seen in

eq. 2.13. This results in a PSRR magnitude response, similar to that achieved

through the Miller compensation.

2.3.3 Blakiewicz’s compensation PSRR Analysis

The positve PSRR for circuit implemented using this compensation is cal-

culated using the small-signal diagram as shown in Fig. 2.10.

The first stage is modeled as a voltage controlled current source gm1Vin,

with R1 and C1 being the impedances of the first stage. The second stage is

modeled with the transconductance of transistor M7 being gm7 times the output

voltage of the first stage, which is V1. The output impedance is ROut and COut.

The compensation network is placed between nodes V1 and the source node of

transistor M8 modeled as gm8V1. Here, RC is equivalent to 1gm8

.

The first dominant pole in PSRR is given by:

ωP1 =1

2R1(CC + Ci)A2

. (2.14)

17

RC

CC

R1C1

V1

gm1VinROutCOut

gm7V1

VOut

Vin

G

+

–

S

gm8V1

VDD

Figure 2.10: PSRR small signal model for basic two-stage opamp with Blakiewicz’scompensation.

The dominant pole achieved through this scheme is of a higher magnitude

than that of Miller compensation as shown in eq. 2.14. This is because of the much

smaller CC used for compensating the opamp, thus extending the bandwidth of

the PSRR. The dominant poles of the three implemented designs in [13] have a

-3dB bandwidth equal to 4.5kHz, 10kHz and 25kHz. They also report that at

higher frequencies around 0.5-10 MHz, the PSRR performance increased by 20

dB.

18

Chapter 3

DESIGN AND SIMULATIONS

Three two-stage operational amplifier designs are presented along with their de-

sign specifications and considerations. The first design consists of a first stage

with a single PMOS transistor load at each differential transistor branch, thus re-

sulting in a low gain configuration. The second design includes a cascoded PMOS

transistor load, thus increasing the gain by a factor of two. The third and fi-

nal design contains a feed-forward path which helps to increase the slew-rate and

bandwidth of the amplifier along with increasing the gain of the opamp. In the

first design two compensantion techniques were implemented: the classical Miller

scheme and the proposed tail scheme. In the second and third designs, Miller,

cascode and tail compensation were implemented for a fair comparison regarding

their performance.

3.1 Two-Stage Opamp: Design I

A two-stage opamp is designed with the first stage operating with a PMOS

current source transistor on one of the differential transistor branches, rather than

the traditional current-mirror load. The transistor M3 is in a diode-connected con-

figuration and is used for matching, with respect to the current source connected

branch. The second stage is a common-source stage with negative gain. The

schematic of this design is shown in Fig. 3.1. Two types of compensation schemes

were implemented seperately: (i) Miller Compensation Technique (ii) Proposed

Compensation Technique. The Miller scheme is established by connecting the

19

voltage node V1 and the output node VOUT , with a nulling resistor RM in series

with compensation capacitor CM . The tail scheme is established by connecting a

compensation capacitor CT between voltage node VX , at the tail, or source termi-

nals of the NMOS differential pair, and output node VOUT . The total bias current

for this configuration is 80.2µA.

Gm1

M 2M 1V IN+V IN-

V1

VX

M 4M 3

VBPV

BP

VCN

VBN

M 5

M 6M 11

M 12

M 13

M 10

M 9

VCN

VBN

M 8

M 7

CM RM

C T

R

Ib

2 Ib

V DD

V SS First Stage Output StageBias Circuit

Ib

VOUT

Tail

Miller

Gm2

Ib

m=2

m=2

m=K

Ib

m=K

VBN

K Ib

Figure 3.1: Schematic of Design I two-stage opamp.

3.1.1 Operation of Design I

As the input VIN+ increases, the current through M2 increases, which re-

sults in the decrement of voltage at node V1. As the voltage at node V1 decreases

the source-gate voltage of transistor M8 in the second stage common-source in-

creases, producing more current, and increasing VOUT . Conversely, if VIN− in-

creases then the voltage at node V1 also increases. Since the the voltage at node

V1 is increased, the transistor M8 produces less current, so that VOUT is decreased.

The device sizes for this amplifier are given in Table. 3.1.

20

Table 3.1: Device Sizings for Design I Two-stage opamps

Device Sizing

M1 −M2,M5 −M6 (9 µm /1.5 µm) m=4

M3 −M4,M13 (27 µm /1.5 µm) m=2

M9,M12 (9 µm /1.5 µm) m=2

M7 (8 x 9 µm/1.5 µm) m=8

M8 (8 x 27 µm /1.5 µm) m=8

RM 15kΩ

CM , CT 1.85pF, 2.3pF

Gm1

M 2M 1V IN+V IN-

V1

VY

VX

M 4

M 6M 5

M 3

VBPV

BP

VCP

VCN

VBN

M 7

M 8M 14

M 12

M 15

M 16

M 13

M 11

VCN

VBN

M 10

M 9

C M R M

C T

C C

RR

Ib

2 Ib

V DD

V SS First Stage Output StageBias Circuit

Ib

VOUT

Tail

Miller

Cascode

Gm2

Ib

m=2

m=2

m=K

Ib

m=K

VBN

K Ib

Figure 3.2: Schematic of Design II two-stage opamp.

3.2 Two-Stage Opamp: Design II

The schematic diagram of the design II: two stage opamp is shown in

Fig. 3.2. The design II varies from design I by the load of the first stage of the

21

Table 3.2: Device Sizings for Design II Two-stage opamps

Device Sizing

M1 −M2,M7 −M8 (9 µm /1.5 µm) m=4

M3 −M6,M15-M16 (27 µm /1.5 µm) m=2

M11-M14 (9 µm /1.5 µm) m=2

M9 (8 x 9 µm/1.5 µm) m=8

M10 (8 x 27 µm /1.5 µm) m=8

RM 15kΩ

CM , CC , CT 1.85pF, 1.72pF, 2.35pF

opamp. Instead of a simple PMOS current source load a cascoded current source

is utilized in each branch to increase the gain by a factor of two through creating

a larger output impedance. The operation does not differ and is similar to that

of design I. The total bias current of this configuration is 80.2µA. Three types

of compensation schemes were implemented seperately: (i) Miller Compensation,

(ii) Cascode Compensation, and (iii) Proposed Compensation. The Miller scheme

is established by connecting the voltage node V1 and the output node VOUT ,with

a nulling resistor RM in series with compensation capacitor CM . The cascode

scheme is created by placing a compensation capacitor CC between the voltage

node VY , the source of cascode transistor M4, and the output node VOUT . The

proposed scheme is established by connecting a compensation capacitor CT be-

tween voltage node VX and output node VOUT . The device sizes for this amplifier

are given in Table. 3.2.

22

3.3 Two-Stage Opamp: Design III

The circuit implementation of a two-stage operational amplifier is given in

Fig. 3.3. The circuit consists of two stages, a differential input pair with single-

ended load and a common-source output stage with a negative gain. Transistors

M1 and M2 form the NMOS differential pair of the first-stage. Generally the

transconductance of a differential amplifier equals the transconductance of one

of the differential input transistors gm1. This is because of a current mirror load

generally connected to the differential pair transistors. Instead, the load of the

first stage is a current source transistor M6. In the circuit realized in this work,

the current through transistor M2 is not mirrored to node V1; hence, the transcon-

ductance is reduced from gm1 to gm1

2. In order to achieve better current matching,

a cascoded current mirror is realized through PMOS transistors M3 and M4. The

PMOS transistor M5 is implemented as a diode-connected transistor. The current

through transistor M2 is utilized to create a feed-forward path directly to node

VOUT through transistors M8-M12. The transistors M8-M12 are designed with a

dimension ratio of 1 : K, thus giving rise to an effective transconductance to the

output node of K gm1

2. In this way, the current generated through the M2 branch

is utilized for two purposes: (i) enhancing the negative going slew-rate and (ii)

biasing the output stage of the amplifier.

The output of the first-stage differential amplifier is connected to the gate

of the PMOS transistor M13 of the second-stage common-source amplifier, which

is sized K times the unit-sized transistors of the first stage. Similarly, transistor

M12 is sized K times larger in order to achieve high output current drive capability.

The bias circuit is used to generate the bias and control voltages required to keep

the transistors in saturation and for the cascode transistors.

23

Gm1

M 2M 1V IN+V IN-

V1

VY

VX

M 4

M 6M 5

M 3

VBPV

BP

VCP

VCN

VBN

M 7

M 8

M 10

M 9

M 11M 17

M 15

M 18

M 19

M 16

M 14

VCN

VBN

M 13

M 12

C M R M

C T

C C

RR

Ib

2 Ib

V DD

V SS Feed-forward Path First Stage Output StageBias Circuit

Ib

VOUT

Tail

Miller

Cascode

Gm2

Ib

m=2

m=2

m=K

Ib

m=K

gmC

Figure 3.3: Schematic of Design III two-stage operational amplifier illustratingMiller, cascode, and proposed compensation techniques.

Three different compensation networks were realized seperately: (i) Miller

compensation placed between the voltage node V1 and the output node VOUT ,

consisting of nulling resistor RM and compensation capacitor CM , (ii) cascode

compensation placed between the voltage node VY and the output node VOUT ,

which consists of compenastion capacitor CC , and (iii) tail compensation realized

through a compensation capacitor CT between voltage node VX and output node

VOUT . The amplifier is implemented using all three compensation techniques

in order to clearly measure the performance characteristics of tail compensation

compared to the other two techniques. The device sizes for this amplifier are given

in Table. 3.3.

3.3.1 Op-amp Gain

We derive the overall gain of the realized operational amplifiers employing

Miller, cascode and the proposed compensation technique using the circuit in

Fig. 3.3. The transconductance of the first-stage differential pair is denoted by

Gm1 and the transconductance of the second-stage common-source amplifier is

24

Table 3.3: Device Sizings of Design III Two-stage opamps

Device Sizing

M1 −M2,M7 −M8 (9 µm /1.5 µm) m=4

M3 −M6,M9 −M10,M18 −M19 (27 µm /1.5 µm) m=2

M11,M14 −M17 (9 µm /1.5 µm) m=2

M12 (8 x 9 µm/1.5 µm) m=8

M13 (8 x 27 µm /1.5 µm) m=8

RM 15kΩ

CM , CC , CT 1.25pF, 1.55pF, 2.75pF

denoted as Gm2. The equivalent resistance and capacitance to ground at the

output node of the first stage are R1 and C1, respectively. The impedance to

ground at the output node VOUT is ROUT || COUT .

Hence, the gain of the first stage differential pair is:

AV 1 = Gm1R1 = −gm1

2R1 (3.1)

where R1 = rom1||(rom6 · gm4rom4).

The gain of the second stage is given by:

AV 2 = −Gm2ROUT (3.2)

where ROUT = (rom13||rom12||RL)

25

The overall gain of the two-stage amplifier, including the feed-forward path

is:

AV = AV 1 · AV 2 +K(Gm1ROUT ) (3.3)

3.3.2 Existing Compensation Techniques

In order to stabilize a two-stage amplifier, the prevailing compensation

topologies are Miller compensation and cascode compensation [4, 17]. Although

these techniques are widely used owing to their effectiveness in stabilizing the

circuit, in some circumstances they are prone to poor power-supply rejection ratio

(PSRR). As shown in Fig. 3.3, the compensation capacitors for Miller and cascode

compensation are both close to the positive power supply rail. As such, supply

noise is easily induced through the capacitors to the output node.

3.3.3 Proposed Compensation Strategy

The new compensation method introduced in this paper, tail compensation

is connected to an internal node VX from the output node. This particular internal

node is selected due to the very low impedance achieved by the source terminals

of differential pair transistors M1 and M2. The output of the first stage is isolated

from the feedback network by a current buffer. As in current buffer compensation

schemes [4] there is no feed-forward path from node V1 to VOUT and hence, no

right-half plane (RHP) zero is created.

The feedback current due to the negative feedback, is split in two parts,

half through M1 and half through M2. Current fedback through M1 establishes

the dominant low-frequency pole at ωp1 =(gm2ROUT ·R1(

CT

2))−1

.

26

In applications such as low-voltage dropout (LDOs) voltage regulators,

where PSRR from the positive rail is important, we can apply tail compensation.

3.3.4 Small-Signal Analysis

AC analysis was conducted using the small-signal models of the two-stage

amplifier with Miller compensation, cascode compensation and tail compensation

are shown in Fig. 3.4, 3.5 and 3.6. Three LHP poles and two LHP zeros were

derived through detailed analysis. A summary of the equations of poles and

zeros along with their approximate frequencies for each compensation network

are given in Tables. 3.4, 3.5, 3.6. Each configuration behaves as a three-pole, two-

zero system and through careful design, the second pole can be approximately

cancelled by the first zero. Hence, the amplifiers would then demonstrate an AC

response of a single-pole system.

+

-

V1

OUTCOUT

R

VOUT

VIN

C1

R1

VIN

Gm1

MRCM

Gm2V1

VIN

Gm1K

Figure 3.4: Small signal model of Fig. 3.3 using Miller compensation.

The dominant poles in each configuration, Miller, cascode and tail, are

established by the compensation capacitances CM , CC and CT , respectively. The

effect of the first non-dominant pole ωp2 is approximately nullified through careful

27

placement of the first LHP zero ωz1. The second zero ωz2 is at very high frequencies

(f ωUGF ), hence is assumed to have negligible effect on the op-amp’s stabil-

ity.The first and second non-dominant poles ωp2 and ωp3 are dependent on the

output capcitor value COUT , whereas the zero ωz1 depends on the compensation

capacitances.

Table 3.4: Poles and Zeros Equations for Design III Two-stage opamp with Millercompensation

Poles/Zeros Miller Freq. (Hz)

ωp11

gm2ROUT ·R1CM5k

ωp2gm2CM

CMC1+COUT (CM+C1)3M

ωp31

RM

(1C1

+ 1CM

+ 1COUT

)170M

ωz11

RMCM8M

ωz2gm2

KC1250M

ωUGF2

√2gm1gm2

4COUTCM5.65M

In tail compensation, compensation capacitance and multiplication factor

K affect the locations of ωp2 and ωp3. Here K is designed to be 4 resulting in the

effect of splitting ωp2 and ωp3, where ωp2 is approximately cancelled by the zero

ωz1 and moving ωp3 to higher frequencies.

3.4 Power Supply Rejection Ratio Analysis

Small signal analysis was performed on the implemented schemes to deter-

mine their performance related to power supply rejection. Power supply rejection

is the amount by which noise from the supply is rejected by the operational am-

plifier. In existing compensation techniques, the low frequency location of the

dominant pole results in a faster deterioration of PSRR [17] . This is caused by

28

+

-

V1

Gm2V1

OUTC

OUTR

VOUT

VIN mC

g1

CC

C1

R1

gmCVY

VINGm1

VY

VINGm1K

Figure 3.5: Small-signal model of Fig. 3.3 using cascode compensation.

Table 3.5: Poles and Zeros Equations for Design III Two-stage opamp with cascodecompensation

Poles/Zeros Cascode Freq. (Hz)

ωp11

gm2ROUT ·R1CC4k

ωp2gm2CC(

COUTCCgmCR1

)+C1(COUT+CC)

16M

ωp3 gmC

(1

COUT+ 1

CC

)+ 1

R1C166M

ωz1gmC

CC14M

ωz2gm2

KC1250M

ωUGFgm1

2CC7.7M

the impedance of the compensation capacitor dropping as the frequency increases,

resulting in the formation of a diode-connected transistor M13. Hence the sup-

ply ripple gets transmitted through the compensation capacitor. The approach

to place the compensation network away from the gate of the output transistor

29

+

-

m1G (VIN-V

X)

V1

Gm2V1 Xm1G VK

OUTCOUTR

VOUT

VIN

m1g1

CT

C1R1

VX1

m2g1

1

+

-

VIN

Figure 3.6: Small-signal model of Fig. 3.3 tail compensated two-stage opamp.

Table 3.6: Poles and Zeros Equations for Design III Two-stage opamp with tailcompensation

Poles/Zeros Tail Freq. (Hz)

ωp12

gm2ROUT ·R1CT4.5k

ωn

√gm1gm2

CgdC1+COUTCgd+C1COUT15M

ωz1gm1

CT10.1M

ωz2gm2

C1156M

ωUGFgm1

CT10.1M

M13 was suggested in [17]. A similar approach with a different opamp topology

is proposed here. The small signal diagrams of the three different compensation

schemes are shown in Fig. 3.7, 3.8 and 3.9.

In order to determine the power supply rejection, the opamp is connected in

a unity-gain configuration and an AC signal in series with the DC power supply

30

voltage is induced at the VDD terminal. Through this method, the ratio VDD

VOUT

determines the PSRR+ of the opamp.

3.4.1 Miller compensated Two-stage opamp design III’s PSRR Anal-

ysis

MRCM

VDD

V1

o2r

o1rC1

VOUT

o13r

OUT OUTC

(gm13 VDD -V1 )

VOUT

-g

2

m1

VOUT

Kg

2m1

R’

VDD

Figure 3.7: Small signal diagram of Miller scheme for PSRR analysis.

According to Fig. 3.7, node V1 is effected by the active current source load

M4, predominantly through its intrinsic resistance roM1. As the input node VIN+

is also grounded the effect of transistor M2 is only through its intrinsic resistance

roM2. Since VOUT is connected to VIN− to configure the opamp in a voltage buffer

configuration, the effect of the feedback on node V1 is a dependent current sink of

value −gm1VOUT

2. C1 is the total capacitance from VDD to node V1. It is dominated

31

by the gate-to-source capacitance of the large output transistor M13. The node

V1 is loaded by the intrinsic resistance of transistor M2, being roM2, assuming the

PMOS cascode load is a much higher resistance. Bias voltages VBP and VCP tend

to track VDD.

The second stage amplifier is modeled with transconductance gm13 times

the gate-to-source voltage, VDD-V1. The feed-forward path is modeled as Kgm1VOUT

2.

Finally ROUT and COUT are the overall output impedances, where R′OUT=ROUT

|| roM13.

For common mode voltage signals in particular VDD, node VX is considered

open, since it is loaded by a cascoded DC current source M7-M8 equal to 2IB.

Therefore, whatever current enters node VX through transistor M1 must circulate

back through transistor M2 onto node V1. The voltage at the gates of M3-M5 is

assumed to be very close to VDD becaude they are diode-connected. Therefore,

the current entering node VX through transistor M1 is approximately VDD

roM1. This

current appears at node V1 as a dependent current source of value VDD

roM1, as shown

in Fig. 3.7. Equations for poles and zeros along with their approximate frequency

values are given in Table. 3.7.

The overall low-frequency PSRR of the designed two-stage amplifier is:

PSRRDC =gm1

2ro1gm13ro13 (3.4)

3.4.2 Cascode compensated Two-stage opamp design III’s PSRR Anal-

ysis

The small signal diagram for the cascode compensation scheme is shown

in Fig. 3.8. The difference when compared to Fig. 3.7 is seen regarding the place-

32

Table 3.7: Location of PSRR Poles and Zeros for Miller compensated Design III

Poles/Zeros Miller Freq. (Hz)

ωp11

gm13ro13·ro1CM1.5k

ωp21

RMro13CM150M

ωp3gm13

C1180M

ωz11

RMCM4.5M

ωz2gm1

2Cgd200M

ωz3gm1gm13

2C1CL800M

ment of compensation capacitor CC . In Fig. 3.8, CC is connected between nodes

VOUT and VY instead of node V1. Due to this placement, the impedance looking

towards the supply VDD is approximately equivalent to 1gm4

. The current through

compensation capacitor CC is labelled as ic and appears at node V1 as a dependent

current source. The effect of the gate-to-drain parasitic capacitance is modeled

as Cgd connected between V1 and VOUT . Pole/zero equations along with their

approximate frequency locations are given in Table. 3.8.

3.4.3 Tail compensated Two-stage opamp design III’s PSRR Analysis

The approach for analyzing the small signal model for the proposed com-

pensation scheme differs slightly when compared to the Miller and cascode com-

pensation schemes. Fig. 3.9 depicts the small signal diagram for tail compensa-

tion. In order to cleary model all the effects, the node VX has to be exposed in

the model. The compensation capacitor CT is placed between nodes VOUT and

VX . Here too, the effect of the feedback is modeled as −gm1VX . The feed-forward

path is modeled as Kgm1(VOUT -VX). The effect of the feedback is shown through

33

CC VOUT

o13r

OUTR’ OUT

C

(gm13 VDD -V1 )

VOUT

Kg

2m1

V

V1

o2r

C1

VOUT

-g

2

m1

ci

o1rDD

gm4

1

VY

Cgd

VDD

Figure 3.8: Small signal diagram of Cascode scheme for PSRR analysis.

(gm13 VDD -V1 )

VX

-gm1

VX

VOUT

Kgm1( )-VX

VDD

o1r

VDD

V1

o2r

C

gm2

1

CT

gm1

1

Cgd

11

VOUT

o13r

OUTR’ OUTC

1

Figure 3.9: Small signal diagram of tail scheme for PSRR analysis.

34

Table 3.8: Location of Poles and Zeros PSRR Cascode

Poles/Zeros Cascode Freq. (Hz)

ωp11

gm13ro13·ro1CC1.2k

ωp2gm13

C1160M

ωp3gm4

Cgd340M

ωz1gm1

2CM7.6M

ωz2gmC

Cgd340M

ωz3gm1gm13

C1CL800M

Table 3.9: Location of Poles and Zeros PSRR Tail

Poles/Zeros Proposed Freq. (Hz)

ωp11

gm13ro13·ro1Cgd25k

ωp22gm1

CT17.3M

ωp3gm13

C1150M

ωz1gm1

CT8.75M

ωz2gm13CT

2C1CL10M

ωz32gm1

CT17.3M

the connection of a voltage buffer of gain 1 between nodes VOUT and VX through

the 1gm1

source terminal of transistor M1. The pole-zero equations along with their

approximate frequency locations are given in Table. 3.9.

35

3.5 Simulation Results

All eight two-stage operational amplifier variants are designed and sim-

ulated in the ONSEMI 0.5µm CMOS process. DC, AC, transient and PSRR

simulations are done and the outputs are shown in the next subsections. The

results in each design configurations I, II and III are compared and presented in

Table. 3.10, 3.11 and 4.1.

+

Vout

+

-

RLCL

VSIN

+

-

Amplifier

RLargeCLarge

AC magnitude =1

Phase = -180

Figure 3.10: AC analysis test bench of two-stage operational amplifiers

3.5.1 AC Analysis

Frequency analysis of the amplifiers are done by breaking the loop of the

amplifier with a large resistor as shown in Fig. 3.10. The test bench has an AC

input source withAC magnitude set to 1 and phase set to 180o, such that the

phase plot starts from 0o. AC simulation is done for output load of 20pF||20kΩ.

The frequency plots of two-stage opamps in design I, design II and de-

sign III with Miller, cascode and proposed compensation schemes are shown in

Fig. 3.11, Fig. 3.12 and Fig. 3.13, 3.14, 3.15 respectively.

36

Figure 3.11: Frequency plots of Design I two-stage opamps with Miller Compen-sation and proposed Compensation.

3.5.2 Transient Analysis

Time-domain analysis is done using transient analysis. The amplifier is

tested in an inverting configuration. Two resistors of 40kΩ are used to have a

gain of unity to the amplifier. The positive terminal is connected to ground and

a 200kHz pulse signal is given as the input. The analysis is done for a load

of 20pF||40kΩ, and the waveforms are plotted. Metrics such as slew rate are

computed and used for comparing different designs.

The transient simulation outputs of two-stage opamps in design I, design

II and design III with Miller, cascode and proposed compensation schemes are

shown in Fig. 3.17, Fig. 3.18 and Fig. 3.19 respectively.

37

Figure 3.12: Frequency plots of Design II two-stage opamps with Miller Compen-sation, Cascode Compensation and proposed Compensation.

3.5.3 Bandwidth Analysis

The bandwidth of each opamp was obtained by simulating them in a similar

method to that of transient analysis. Here, an input of 100mV peak-peak is given

to the positive terminal of the opamp and the negative terminal through the 40kΩ

resistor is given to ground. The rms voltage is found and the frequency is increased

till output voltage is 3dB lower than at low frequencies. Since this is a gain of

two configuration, the measured frequency is doubled to obtain the bandwidth of

each opamp.

38

Figure 3.13: Frequency plots of Design III two-stages opamp with Miller compen-sation.

3.5.4 Power-Supply Rejection Ratio

Power-supply rejection ratio (PSRR) is used to find the attenuation of the

noise from the power-supply by the amplifier. The test bench for finding PSRR

is shown in Fig. 3.20. The inputs of the amplifier in the inverting configuration

is connected to ground and an AC sinusoidal signal source with 100mVPP is con-

nected in series with the dc power-supply. The frequency of the ac signal is varied

to calculate PSRR at different frequencies. The equation of PSRR is

PSRR+ = 20log(RippleSupplyRippleOutput

). (3.5)

The PSRR is plotted at various frequencie ranging from 100 Hz - 3 MHz, for

all the designs I, II and III two-stage operational amplifiers and summarized in

39

Figure 3.14: Frequency plots of Design III two-stages opamp with cascode com-pensation.

Table. 3.10. Simulated PSRR plots for design I, design II and design III are shown

in Fig. 3.21, 3.22, 3.23, 3.24, 3.25, 3.26.

40

Figure 3.15: Frequency plots of Design III two-stages opamp with proposed com-pensation.

Vout

+

-

RLCL

VIN

+

-

Amplifier

RF1RF2

+

200kHz step

input

Figure 3.16: Transient analysis test bench in inverting configuration.

41

Figure 3.17: Transient output of Design I two-stage opamps with Miller compen-sation and proposed compensation schemes.

42

Figure 3.18: Transient output of Design II two-stage opamps with Miller compen-sation, cascode and proposed compensation schemes.

43

Figure 3.19: Transient outputs of Design III two-stage opamps with Miller, cas-code and proposed compensation techniques.

Vout

+

-

RLCL

VIN

+

+

-

Amplifier

RF1RF2

+

VSIN

+

-

Figure 3.20: Test bench for measuring PSRR.

44

Figure 3.21: Frequency plots of PSRR for Design I opamps using Miller andproposed compensation schemes.

Figure 3.22: Frequency plots of PSRR for Design II two-stage opamps using Miller,cascode and proposed compensation schemes.

45

Figure 3.23: Frequency plots of PSRR for Design III two-stage opamp using millercompensation technique.

Figure 3.24: Frequency plots of PSRR for Design III two-stage opamp using cas-code compensation technique.

46

Figure 3.25: Frequency plots of PSRR for Design III two-stage opamp using pro-posed compensation technique.

Figure 3.26: Frequency plots of PSRR for Design III two-stage opamp using pro-posed compensation technique.

47

Table 3.10: Simulated Results for Design I two-stage opamps

Parameters Miller proposed

Power supply ±1.5V ±1.5V

Dc gain 60dB 60dB

Bandwidth 4.6MHz 7.8MHz

Phase margin 61.2o 61.3o

RL 20kΩ 20kΩ

CL 20pF 20pF

CC 1.8pF 2.3pF

SR + /SR− (V/µs) 4.4/1.04 4.2/1.5

PSRR @1kHz 72.9dB 72.4dB

PSRR @500kHz 53.6dB 53.1dB

PSRR @1MHz 33.6dB 32.9dB

48

Table 3.11: Simulated Results for Design II two-stage opamps

Parameters Miller Cascode proposed

Power supply ±1.5V ±1.5V ±1.5V

Dc gain 63dB 63dB 63dB

Bandwidth 4.6MHz 7.7MHz 7.7MHz

Phase margin 60.9o 61.5o 61.7o

RL 20kΩ 20kΩ 20kΩ

CL 20pF 20pF 20pF

CC 1.85pF 1.72pF 2.35pF

SR + /SR− (V/µs) 4.3/1.04 5.0/1.08 4/1.08

PSRR @1kHz 72.9dB 72.4dB 79.3dB

PSRR @500kHz 53.6dB 53.1dB 61.0dB

PSRR @1MHz 33.6dB 32.9dB 41.2dB

49

Table 3.12: Summary of Results with a supply voltage of ±1.5V of Design IIITwo-stage Opamp

Parameter/Design Miller Cascode proposed

RC , CC 15kΩ, 1.25pF -, 1.55pF -, 2.75pF

ADC (dB) 63.6 63.6 63.6

Bandwidth (MHz) 5.9 8.2 10.6

Phase Margin 62.9o 63.0o 62.7o

RL 20kΩ 20kΩ 20kΩ

CL 20pF 20pF 20pF

SR+/SR- (V/µs) 6.3/2.9 5.8/3.0 3.4/5.1

PSRR+ @ 1kHz (dB) 74.4 74 76

PSRR+ @ 100kHz (dB) 44 40 66

PSRR+ @ 3MHz (dB) 14 8 36

50

Chapter 4

EXPERIMENTAL RESULTS

Layout of all the amplifiers, a micrograph of the fabricated chip and hardware

results are discussed in this chapter.

4.1 Layout

Figure 4.1: Overall chip layout.

51

The overall chip layout, consisting of Design I (Miller and tail), Design

II (Miller, cascode and tail) and Design III (Miller, cascode and tail) two-stage

opamps are shown in Fig. 4.1. On the left side of the chip, eight two-stage opamps

(design I, design II and design III) are laid out in closed-loop configurations. The

resistors used for the closed-loop setup are two 40kΩ resistors. The right side

of the chip consist of the eight opamps in open-loop configuration. The rest of

the chip is filled with substrate contacts and metal layers as per the requirements

for submitting the chip to MOSIS. There are VDD and VSS that are used for the

padring and open-loop amplifiers. There is a second set of VDD and VSS for the

closed-loop opamps. All 40-pins were utilized carefully to be able to test each

block individually. The supply and output wires are laid out with extra width as

they carry the maximum currents.

Figure 4.2: Layout of design I two-stage opamp with Miller compensation..

The layout of Design I two-stage opamp with Miller compensation is shown

in Fig. 4.2. The area of the amplifier is 136x63µm2.

The layout of Design I two-stage opamp with proposed tail compensation

is shown in Fig. 4.3. The area of the amplifier is around 155x58.8µm2.

The layout of Design II two-stage opamp with Miller compensation is shown

in Fig. 4.4. The area of the amplifier is around 176x74.5µm2.

52

Figure 4.3: Layout of design I two-stage opamp with Tail compensation.

Figure 4.4: Layout of design II two-stage opamp with Miller compensation.

The layout of Design II two-stage opamp with cascode compensation is

shown in Fig. 4.5. The area of the amplifier is around 169x74µm2.

The layout of Design II two-stage opamp with proposed tail compensation

is shown in Fig. 4.6. The area of the amplifier is around 199x74µm2.

The layout of Design III two-stage opamp with Miller compensation is

shown in Fig. 4.7. The area of the amplifier is around 179x74µm2.

The layout of Design III two-stage opamp with cascode compensation is

shown in Fig. 4.8. The area of the amplifier is around 181x75µm2.

The layout of Design III two-stage opamp with proposed tail compensation

is shown in Fig. 4.9. The area of the amplifier is around 210x74µm2.

53

Figure 4.5: Layout of design II two-stage opamp with Cascode compensation.

Figure 4.6: Layout of design II two-stage opamp with Tail compensation.

4.2 Test Apparatus

We used voltage supplies of ±1.5 V and ground to test the chip. An Agilent

5400 function generator is used to generate a 200 kHz pulse signal with a peak-to-

peak voltage of 1.6 V. A Hewlett Packard 54603B oscilloscope is used to observe

the waveforms of transient analysis as described in the test procedure shown in

APPENDIX A.

4.3 Hardware Test Results

The chip was fabricated in the 0.5µm 2P3M ONSEMI technology through

MOSIS. The chip was tested with supply voltages ±1.5V and an input bias current

of 10µA to all the amplifiers.

54

Figure 4.7: Layout of design III two-stage opamp with Miller compensation.

Figure 4.8: Layout of design III two-stage opamp with Cascode compensation.

Transient measurements were performed for the closed-loop amplifiers in

an inverting configuration and gain of one. Two integrated and carefully matched

40 kΩ resistors were used in the negative feedback to achieve unity gain. The

Figure 4.9: Layout of design III two-stage opamp with Tail compensation.

55

input is a 200 kHz square wave with peak-to-peak voltage of 1.6 V. All amplifier

types were tested with an external load of 40 kΩ and 20pF in parallel. Three of

the combination outputs are presented. The positive slew rate is measured as the

slope of the rising edge from 10% to 90% of output peak-to-peak voltage and the

negative slew rate is similar for the falling edge.

Figure 4.10: Hardware waveforms of Design III two-stage amplifiers with Miller,cascode and tail compensation schemes.

The time-domain response of the design III two-stage opamps in closed-

loop configuration of gain -1 V/V were measured and are shown in Fig. 4.10.

Though the positive going slew-rate of Miller and cascode schemes are marginally

faster, the negative going slew-rate of the proposed tail compensation scheme is

much faster when compared to those of Miller and cascode schemes.

The measured PSRR performance for Design III two-stage opamps are

shown in Fig. 4.11, 4.12, 4.13 and 4.14. The PSRR performance of all the schemes

are identical at low frequencies. Miller and cascode schemes portray similar pos-

56

itive supply noise rejection performance across a wide range of frequencies. The

proposed tail compensation performs exellent in this characteristic. At a high

frequency of 1MHz, the tail compensation has a PSRR gain of 44 dB, whereas the

Miller and cascode schemes have PSRR gains of 21 dB and 19 dB respectively.

The measured results of the opamps are summarized in Table 4.1.

Figure 4.11: Hardware PSRR frequency response outputs of Design III two-stageamplifier with Miller, cascode and tail compensation schemes.

Figure 4.12: Hardware PSRR frequency response outputs of Design III two-stageamplifier with cascode scheme.

57

Figure 4.13: Hardware PSRR frequency response outputs of Design III two-stageamplifier with tail scheme.

Figure 4.14: Hardware PSRR frequency response outputs of Design III two-stageamplifier with tail scheme.

58

Table 4.1: Summary of Measured Results of Design III Opamps with a supplyvoltage of ±1.5V while driving a load of 20kΩ||20pF

Parameter/Design Miller Cascode Tail

RC , CC 15kΩ, 1.25pF -, 1.55pF -, 2.75pF

UGF (MHz) 6.4 8.2 10.3

SR+/SR- (V/µs) 6.3/2.9 5.8/3.0 3.4/5.1

PSRR+ @ 1kHz (dB) 74.4 74 76

PSRR+ @ 100kHz (dB) 44 40 66

PSRR+ @ 3MHz (dB) 14 8 36

59

Chapter 5

DISCUSSION AND CONCLUSION

A novel compensation scheme is introduced in detail and verified for two-stage

opamps. Eight opamps were designed and simulated. Miller, cascode and the

proposed compensation technique were implemented with similar specifications.

In comparison, the new compensation technique exhibits a greater PSRR from

positive supply line by 22dB and 26dB at 100kHz than that achieved by Miller

and cascode compensation techniques, respectively. At 3MHz, the PSRR achieved

through the proposed compensation scheme is greater by 22dB and 28dB with

respect to Miller and cascode compensation schemes, respectively. The unity-gain

frequency was also improved to 10.3MHz from 6.4MHz for Miller and 8.2MHz for

cascode compensation techniques, respectively. The minimum slew rate achieved

through the proposed compensation technique is 3.4V/µs, while that measured for

Miller and cascode is 2.9V/µs and 3.0V/µs, respectively. The theoretical analysis

for small signal modeling and PSRR analysis was performed and presented in the

report. The theoretical pole/zero values are verified with simulated and measured

data. A summary of measured results of Design III Two-stage opamps are shown

Table 5.1.

5.1 Issues

The bias pin is shared between two sets of opamps, one closed-loop and

one open-loop. This leads to errors in the generated bias voltage. Measurement

60

Table 5.1: Summary of Measured Results of Design III Opamps with a supplyvoltage of ±1.5V while driving a load of 20kΩ||20pF

Parameter/Design Miller Cascode Tail

RC , CC 15kΩ, 1.25pF -, 1.55pF -, 2.75pF

UGF (MHz) 6.4 8.2 10.3

SR+/SR- (V/µs) 6.3/2.9 5.8/3.0 3.4/5.1

PSRR+ @ 1kHz (dB) 74.4 74 76

PSRR+ @ 100kHz (dB) 44 40 66

PSRR+ @ 3MHz (dB) 14 8 36

of PSRR in open-loop configuration was unsuccessful, which lead us to analyze

the opamps in closed-loop configuration.

5.2 Future Work

This compensation scheme was implemented on a two-stage opamp for the

purpose of verifying its feasibility. The amplifier can be improved by designing it

into a Class-AB amplifier. Also the usage of the proposed compensation scheme

for multi-stage opamps can be explored. Another possibility would be to design a

Low Dropout voltage regulator (LDO) using the proposed compensation scheme.

61

APPENDICES

APPENDIX A

Test Document

SriHarsh Pakala 800431266

Test Procedure

Pin Description Table:

P# Name Pad Type Pin Description

1. V_o_opn4 Protect Output of open loop design_2_casc/ opamp4 2. V_o_opn3 Protect Output of open loop design_2_miler/ opamp3 3. V_o_opn2 Protect Output of open loop design_1_tail/ opamp2 4. V_o_opn1 Protect Output of open loop design_1_miler/ opamp1 5. Vdd_opn Protect Vdd= +1.5V for all open loop opamps 6. V_in-_opn1 Protect Input of open loop design_1_miler/opamp1 7. V_in-_opn2 Protect Input of open loop design_1_tail/opamp2 8. V_in-_opn3 Protect Input of open loop design_2_miler/opamp3 9. V_in-_opn4 Protect Input of open loop design_2_casc/opamp4 10. Vdd_global Vdd Global Vdd connecting vdd power rail across chip 11. Vbias_1 Protect Vbias for both clsd & open loop design_1_miler/opamp1 12. Vbias_2 Protect Vbias for both clsd & open loop design_1_tail/opamp2 13. Vbias_3 Protect Vbias for both clsd & open loop design_2_miler/opamp3 14. Vbias_4 Protect Vbias for both clsd & open loop design_2_casc/opamp4 15. V_in+_clsd Protect Vin+ for all closed loop designs 1-8 16. Vdd_clsd Protect Vdd=+1.5V for all closed loop opamps 17. V_o_clsd_1 Protect Output of closed loop design_1_miler/opamp1 18. V_o_clsd_2 Protect Output of closed loop design_1_tail/opamp2 19. V_o_clsd_3 Protect Output of closed loop design_2_miler/opamp3 20. V_o_clsd_4 Protect Output of closed loop design_2_casc/opamp4 21. V_o_clsd_5 Protect Output of closed loop design_2_tail/opamp5 22. V_o_clsd_6 Protect Output of closed loop design_3_miler/opamp6 23. V_o_clsd_7 Protect Output of closed loop design_3_casc/opamp7 24. V_o_clsd_8 Protect Output of closed loop design_3_tail/opamp8 25. Vss_clsd Vss Vss= -1.5V for all closed loop designs 1-8 26. V_in-_clsd Protect Vin- for all closed loop designs 1-8 27. Vbias_5 Protect Vbias for both clsd &opn loop design_2_tail/opamp5 28. Vbias_6 Protect Vbias for both clsd & opn loop design_3_miler/opamp6 29. Vbias_7 Protect Vbias for both clsd & opn loop design_3_casc/opamp7 30. Vbias_8 Protect Vbias for both clsd & opn loop design_3_tail/opamp8 31. V_in-_opn5 Protect Input of open loop design_2_tail/opamp5 32. V_in-_opn6 Protect Input of open loop design_3_miler/opamp6 33. V_in-_opn7 Protect Input of open loop design_3_casc/opamp7 34. V_in-_opn8 Protect Input of open loop design_3_tail/opamp8 35. V_in+_opn Protect Vin+ input for all open loop designs 1-8 36. Vss_opn Vss Vss= -1.5V for all open loop designs 1-8 37. V_o_opn8 Protect Output of open loop design_3_tail/ opamp8 38. V_o_opn7 Protect Output of open loop design_3_casc/ opamp7 39. V_o_opn6 Protect Output of open loop design_3_miler/ opamp6 40. V_o_opn5 Protect Output of open loop design_2_tail/ opamp5

SriHarsh Pakala 800431266

Testbench for Transient Analysis:

Figure 1: Transient analysis testbench

Supply Voltages:

Vdd = 1.5 V

Vss = -1.5 V

Ibias = 10µA

Procedure:

1) Connect global Vdd (Vdd_global) (pin 10) and global Vss (Vss_opn) (pin 36) and check whether chip is good or fired up.

2) Connect closed loop Vdd (Vdd_clsd) (pin 16) to global Vdd (Vdd_global) (pin 10). 3) Connect global Vss (Vss_opn) (pin 36) closed loop Vss (Vss_clsd) (pin 25). 4) Connect Vin+ input for all closed loop designs (V_in+_clsd) (pin 15) to ground. 5) Connect Vin- input for all closed loop designs (V_in-_clsd) (pin 26) to the Function Generator with input

800mV peak-to-peak signal at a frequency = 200kHz. 6) Calculate and attach the bias resistor required for each op-amp design.

a) Closed loop design_1_miller/opamp1 i) Calculation of Rbias1: Vbias 1 = -397mV

!"#$%1 =!"" − !"#$%1

!"#$%

!"#$%1 = 190KΩ But since each bias line is shared by 2 op-amps (one closed loop and the other open loop), we would need to use an Rbias1 = 95KΩ. ii) Connect 95 KΩ from Vdd (pin 16) to Vbias_1 (pin 11).

!!"#$

"

#

%&'&

!()*+

,-./01023

%45%46"

67789:;<$2.;0=.#$

SriHarsh Pakala 800431266

iii) Connect Vout_1 (pin 17) to RL=40KΩ and RL to ground.

b) Closed loop design_1_tail/opamp2 i) Calculation of Rbias2: Vbias 2 = -397mV

!"#$%2 =!"" − !"#$%3

!"#$%

!"#$%2 = 190KΩ

But since each bias line is shared by 2 op-amps (one closed loop and the other open loop), we would need to use an Rbias2 = 95KΩ. ii) Connect 95 KΩ from Vdd (pin 16) to Vbias_2 (pin 12). iii) Connect Vout_2 (pin 18) to RL=40KΩ and RL to ground.

c) Closed loop design_2_miller/opamp3 i) Calculation of Rbias3: Vbias 3 = -397mV

!"#$%3 =!"" − !"#$%3

!"#$%

!"#$%3 = 190KΩ

But since each bias line is shared by 2 op-amps (one closed loop and the other open loop), we would need to use an Rbias3 = 95KΩ. ii) Connect 95 KΩ from Vdd (pin 16) to Vbias_3 (pin 13). iii) Connect Vout_2 (pin 19) to RL=40KΩ and RL to ground.

d) Closed loop design_2_casc/opamp4 i) Calculation of Rbias4: Vbias 4 = -397mV

!"#$%4 =!"" − !"#$%4

!"#$%

!"#$%4 = 190KΩ

But since each bias line is shared by 2 op-amps (one closed loop and the other open loop), we would need to use an Rbias4 = 95KΩ. ii) Connect 95 KΩ from Vdd (pin 16) to Vbias_4 (pin 14). iii) Connect Vout_4 (pin 20) to RL=40KΩ and RL to ground.

e) Closed loop design_2_tail/opamp5 i) Calculation of Rbias5: Vbias 5 = -397mV

!"#$%5 =!"" − !"#$%5

!"#$%

!"#$%5 = 190KΩ

But since each bias line is shared by 2 op-amps (one closed loop and the other open loop), we would need to use an Rbias5 = 95KΩ. ii) Connect 95 KΩ from Vdd (pin 16) to Vbias_5 (pin 27). iii) Connect Vout_5 (pin 21) to RL=40KΩ and RL to ground.

f) Closed loop design_3_miller/opamp6 i) Calculation of Rbias6: Vbias 6 = -397mV

SriHarsh Pakala 800431266

!"#$%6 =!"" − !"#$%6

!"#$%

!"#$%6 = 190KΩ

But since each bias line is shared by 2 op-amps (one closed loop and the other open loop), we would need to use an Rbias6 = 95KΩ. ii) Connect 95 KΩ from Vdd (pin 16) to Vbias_6 (pin 28). iii) Connect Vout_6 (pin 22) to RL=40KΩ and RL to ground.

g) Closed loop design_3_casc/opamp7 i) Calculation of Rbias7: Vbias 7 = -397mV

!"#$%7 =!"" − !"#$%7

!"#$%

!"#$%7 = 190KΩ

But since each bias line is shared by 2 op-amps (one closed loop and the other open loop), we would need to use an Rbias7 = 95KΩ. ii) Connect 95 KΩ from Vdd (pin 16) to Vbias_7 (pin 29). iii) Connect Vout_7 (pin 23) to RL=40KΩ and RL to ground.

h) Closed loop design_3_tail/opamp8 i) Calculation of Rbias8: Vbias 8 = -397mV

!"#$%8 =!"" − !"#$%8

!"#$%

!"#$%8 = 190KΩ

But since each bias line is shared by 2 op-amps (one closed loop and the other open loop), we would need to use an Rbias8 = 95KΩ. ii) Connect 95 KΩ from Vdd (pin 16) to Vbias_8 (pin 30).

i) Connect Vout_8 (pin 24) to RL=40KΩ and RL to ground. 7) The outputs of opamps 1-8 are observed on the scope by connecting the outputs V_o_clsd1 – V_o_clsd8 of

each opamp to the scope to tabulate and measure the SR+ and SR- of each design.

Design SR+ (V/µs) SR- (V/µs) Design_1_miller/opamp1 4.36 1.04 Design_1_tail/opamp2 4.12 1.46 Design_2_miller/opamp3 4.33 1.04 Design_2_casc/opamp4 5.08 1.07 Design_2_tail/opamp5 3.98 1.07 Design_3_miller/opamp6 6.5 2.9 Design_3_casc/opamp7 6.0 3.0 Design_3_tail/opamp8 3.4 5.1

SriHarsh Pakala 800431266

Testbench for Bandwidth Measurement:

Figure 2: Testbench for bandwidth measurement

Procedure:

1) Repeat steps 1 to 3 as in transient analysis testbench procedure. 2) Connect Vin+ (pin 15) to Function Generator with input signal of 100mV pk-pk at a frequency =

1kHz with an 1X probe. 3) Connect Vout_1 (pin 17) to RL=40KΩ and RL to ground. 4) Connect Vout_2 (pin 18) to RL=40KΩ and RL to ground. 5) Connect Vout_3 (pin 19) to RL=40KΩ and RL to ground. 6) Connect Vout_4 (pin 20) to RL=40KΩ and RL to ground. 7) Connect Vout_5 (pin 21) to RL=40KΩ and RL to ground. 8) Connect Vout_6 (pin 22) to RL=40KΩ and RL to ground. 9) Connect Vout_7 (pin 23) to RL=40KΩ and RL to ground. 10) Connect Vout_8 (pin 24) to RL=40KΩ and RL to ground. 11) In order to measure bandwidth, apply input signal through the Function generator and calculate Vrms

of each opamp’s outputs (Vout_1 to Vout_8). 12) Then calculate !1 = !"#$/ 2 and keep increasing the frequency of the input signal till the

output signal = !1. 13) The value of frequency obtained would then have to be doubled as the analysis is conducted with a

gain configuration of 2.

Design Vrms (V) V1 (V) Freq. at V1 (MHz) BW (MHz) design_3_miller/opamp6 7mV 4.95

design_3_casc/opamp7 7mV 4.95 design_3_tail/opamp8 7mV 4.95

SriHarsh Pakala 800431266

Testbench for Power Supply Rejection+ (PSR+) Measurement

Figure 3: Testbench for measuring PSRR+

Inputs: Both Vin+ and Vin- are grounded. Input given to Vdd pin = 100mV Output: connected to spectrum analyzer

Procedure:

1) Repeat steps 1 to 3 as in transient analysis testbench procedure. 2) Connect Vin+ (pin 15) and Vin- (pin 26) to ground. 3) Connect Vdd_clsd (pin 16) to function generator’s red (positive terminal) wire. 4) Connect negative terminal of function generator (black wire) to the +ve terminal of the D.C

power supply. 5) Ground the negative terminal of the D.C power supply. 6) Make sure to ground the Function generator, Oscilloscope and the Spectrum Analyzer to same

ground region. 7) In order to observe the outputs connect Vout_6 (pin 22), Vout_7 (pin 23) and Vout_8 (pin 24) to

the spectrum analyzer one at a time. 8) To measure till 100kHz Digital spectrum analyzer (Stanford Research SR770) can be used but

beyond that analog spectrum analyzer (HP 4195) was needed. 9) In order to measure using the HP 4195, a voltage buffer was used (LMC 6482). This buffer too

was tested with the spectrum analyzer at frequencies ranging from 1kHz to 1MHz, it’s effect observed and tabulated such that it could be considered to obtain final PSR values.

!!"#$

"

#

%&'&

!()"*+

,-./01023

%45%46

"

!7()

*+

SriHarsh Pakala 800431266

Freq. Vin (mVrms) Vout (m Vrms) Phase

dB

-­‐0.3

100 67.6

65.8

inphase

-­‐0.3 200 67.7

65.6

inphase

-­‐0.3

500 67.6

65.6

inphase

-­‐0.3 1k 70

68

inphase

-­‐0.3

10k 70

67.5

inphase

-­‐0.3 20k 67.4

65

-­‐0.3

50k 13.6

12.8

-­‐0.5 100k 13.5

11.6

lag -­‐35 degrees

-­‐1.31

200k 13.5

9.2

lag -­‐45 degrees 3dB down -­‐3.33

500k 33.3

10

-­‐10.4 1M 68.5

5.1

-­‐22.6

The dB value should be subtracted from figure shown on analyzer for each corresponding frequency.

10) Formula to convert dBm to dB: ! !"# = 20 log(!"#$ !"#$%&'())+ 10 !"

Ex: 73 dBm = 63 dB 11) In such a way PSR values were observed and tabulated for opamp6-8 through pins 22-24. 12) The 100mV input signal’s footprint in dB was observed to be -20 dB. 13) This value has to be subtracted from the figure shown on the analyzer. 14) Further normalization is performed by considering the 2X gain lost due to grounding of the input

terminals. Hence a 6dB has to be added to the values obtained after step 12. 15) The final PSR values are calculated and tabulated.

SriHarsh Pakala 800431266

Tail compensation/opamp8:

Freq. SR770 HP4195 (dBm) HP4195(dB)

Invert (inp@-­‐20dB)+20dB

2x gain +6dB

subtract follower

final PSRR

10 20 50

100 200 500

1000 2000 5000 10k 20k 50k

100k 200k 500k 1M 3M

Cascode Compensation/opamp7:

Freq. SR770 HP4195 (dBm)

HP4195(dB)

Invert (inp@-­‐20dB)+20dB

2x gain +6dB subtract follower

final PSRR

10

20

50

100

200

500

1000

2000

5000

10k

SriHarsh Pakala 800431266

20k 50k

100k

200k

500k

1M

3M Miller Compensation/opamp6:

Freq. SR770 HP4195 (dBm) HP4195(dB)

Invert (inp@-­‐20dB)+20dB

2x gain +6dB subtract follower

final PSRR

10

20

50

100

200

500

1000

2000

5000

10k

20k

50k

100k

200k

500k

1M

3M

APPENDIX B

Maple

O O

(3)(3)

(4)(4)

O O

(2)(2)

(1)(1)

O O

A. Design III Miller Compensated Small Signal Analysis : Summary of DC Gain, Poles and Zeros

Summary of DC Gain, Poles and Zeros

Gain =12

r1 gm13 Rout gm2

Gain =12

r1 gm13 Rout gm2

solve k= 4, gm2= 1.76$10K4

, R1= 1.7$106, C1 = 6.57$10

K14, gm13

= 5.656$10K4

, Rout= 20000, Cout = 20$10K12

, Cm = 1.25$10K12

,

wp1 = 1R1 gm13 Rout Cm $2$3.14

, wp1, gm2, gm13, R1,

Rout, C1, Cout, Cm, k

C1 = 6.570000000 10-14, Cm = 1.250000000 10-12, Cout = 2.000000000 10-11, R1

= 1.700000 106, Rout = 20000., gm13= 0.0005656000000, gm2= 0.0001760000000, k = 4.,

wp1 = 6624.331009

solve k= 4, gm2= 1.76$10K4

, R1= 1.7$106, C1 = 557$10

K15, gm13

= 5.656$10K4

, Rout= 20000, Cout = 20$10K12

, Cm = 1.25$10K12

,

wp2 = gm13 $CmCout$CmCCout$C1CCm$C1 $2$3.14

, wp2, gm2,

gm13, R1, Rout, C1, Cout, Cm, k

C1 = 5.570000000 10-13, Cm = 1.250000000 10-12, Cout = 2.000000000 10-11, R1

= 1.700000 106, Rout = 20000., gm13= 0.0005656000000, gm2= 0.0001760000000, k = 4.,

wp2 = 3.056218204 106

(6)(6)

(5)(5)

(7)(7)

solve k= 4, gm2= 1.76$10K4

, Rm= 15000, R1= 1.57* 106, C1

= 557$10K15

, gm13= 5.656$10K4

, Rout= 20000, Cout = 20

$10K12

, Cm = 1.25$10K12

, wp3 = 12$3.14$ Rm

1C1

C 1Cout

C 1Cm

, wp3, gm13, gm2, Rm, R1, Rout, C1, Cout, Cm, k

C1 = 5.570000000 10-13, Cm = 1.250000000 10-12, Cout = 2.000000000 10-11, R1

= 1.570000 106, Rm = 15000., Rout = 20000., gm13= 0.0005656000000, gm2

= 0.0001760000000, k = 4., wp3 = 2.808208213 107

solve k= 4, gm2= 1.7$10K4

, Rm= 15000, R1= 1.7$106, C1 = 557

$10K15

, gm13= 5.66$10K4

, Rout= 20000, Cout = 20$10K12

, Cm

= 1.25$10K12

, wz1 = 12$3.14$ Rm$Cm

, wz1, gm13, gm2, Rm,

R1, Rout, C1, Cout, Cm, k

C1 = 5.570000000 10-13, Cm = 1.250000000 10-12, Cout = 2.000000000 10-11, R1

= 1.700000 106, Rm = 15000., Rout = 20000., gm13= 0.0005660000000, gm2

= 0.0001700000000, k = 4., wz1= 8.492569003 106

solve k= 4, gm2= 1.7$10K4

, Rm= 15000, R1= 1.7$106, C1 = 557

$10K15

, gm13= 5.6$10K4

, Rout= 20000, Cout = 20$10K12

, Cm

= 1.25$10K12

, wz2 = gm132$3.14$ k$C1

, wz2, gm13, gm2, Rm, R1,

Rout, C1, Cout, Cm, k

C1 = 5.570000000 10-13, Cm = 1.250000000 10-12, Cout = 2.000000000 10-11, R1

(9)(9)

(10)(10)

(8)(8)

(7)(7)

= 1.700000 106, Rm = 15000., Rout = 20000., gm13= 0.0005600000000, gm2

= 0.0001700000000, k = 4., wz2= 4.002332789 107

solve ft = sqrt Kgm2$R1$gm13$Rout2

$ 1gm13$Rout$R1$Cm

$ gm13$CmCout$CmCCout$C1CCm$C1

, ft

ft = 12

K2 gm2 gm13

Cout CmCCout C1CCm C1

solve k= 4, gm2= 1.7$10K4

, Rm= 15000, R1= 1.7$106, C1 = 5.57

$10K15

, gm13= 5.6$10K4

, Rout= 20000, Cout = 20$10K12

, Cm

= 1.25$10K12

, ft = 12

K2 gm2 gm13

Cout CmCCout C1CCm C1, ft, gm13, gm2,

Rm, R1, Rout, C1, Cout, Cm, k

C1 = 5.570000000 10-15, Cm = 1.250000000 10-12, Cout = 2.000000000 10-11, R1

= 1.700000 106, Rm = 15000., Rout = 20000., ft = 4.353191921 107 I, gm13

= 0.0005600000000, gm2= 0.0001700000000, k = 4.

solve k= 4, gm2= 1.7$10K4

, Rm= 15000, R1= 1.7$106, C1 = 5.57

$10K15

, gm13= 5.6$10K4

, Rout= 20000, Cout = 20$10K12

, Cm

= 1.25$10K12

, ft = 12$ 6.28

K2 gm2 gm13Cout Cm

, ft, gm13, gm2,

Rm, R1, Rout, C1, Cout, Cm, k

C1 = 5.570000000 10-15, Cm = 1.250000000 10-12, Cout = 2.000000000 10-11, R1

(10)(10)

O O

(7)(7)

= 1.700000 106, Rm = 15000., Rout = 20000., ft = 6.948224276 106 I, gm13= 0.0005600000000, gm2= 0.0001700000000, k = 4.

O O

O O

O O

(3)(3)

O O

(4)(4)

(2)(2)

O O

O O

O O

(1)(1)

O O

B. Design III Cascode Compensated Small Signal Analysis : Summary of DC Gain, Poles and Zeros

Summary of DC Gain, Poles and Zeros

Gain =12

r1 gm13 Rout gm2

Gain =12

r1 gm13 Rout gm2

solve k = 4, gm2= 1.7$10K4, R1 = 1.7$106, C1 = 5.57$10K15, gm13= 5.6$10K4, Rout = 20000, Cout = 20

$10K12, Cc = 1.55$10K12, wp1 =1

R1 gm13 Rout Cc $2$3.14, wp1, gm13, gm2, R1, Rout, C1,

Cout, Cc, k

C1 = 5.570000000 10-15, Cc = 1.550000000 10-12, Cout = 2.000000000 10-11, R1

= 1.700000 106, Rout = 20000., gm13= 0.0005600000000, gm2= 0.0001700000000, k = 4.,

wp1 = 5395.624451

solve k = 4, gm2= 1.7$10K4, R1 = 1.7$106, C1 = 505$10K15, gm13= 5.6$10K4, gm4= 1.37$10K4, Rout

= 20000, Cout = 20$10K12, Cc = 1.55$10K12, wp2

=gm13$Cc

Cout$Ccgm4$R1 CCout$C1CCc$C1 $2$3.14

, wp2, gm13, gm2, gm4, R1, Rout, C1, Cout,

Cc, k

C1 = 5.050000000 10-13, Cc = 1.550000000 10-12, Cout = 2.000000000 10-11, R1

= 1.700000 106, Rout = 20000., gm13= 0.0005600000000, gm2= 0.0001700000000, gm4

= 0.0001370000000, k = 4., wp2 = 1.254705775 107

(8)(8)

(5)(5)

(7)(7)

(6)(6)

solve k = 4, gm2= 1.5$10K4, R1 = 1.5$106, C1 = 6.57$10K14, gm13= 5.6$10K4, gm4= 1.37$10K4, Rout

= 20000, Cout = 20$10K12, Cc = 1.55$10K12, wp3 =gm4$ 1

Cout C1Cc C

1R1$C1

2$3.14,

wp3, gm13, gm2, gm4, R1, Rout, C1, Cout, Cc, k

C1 = 6.570000000 10-14, Cc = 1.550000000 10-12, Cout = 2.000000000 10-11, R1

= 1.500000 106, Rout = 20000., gm13= 0.0004156000000, gm2= 0.0001500000000, gm4

= 0.0001370000000, k = 4., wp3 = 1.678092838 107

solve k = 4, gm2= 1.5$10K4, Rc = 15000, R1 = 1.5$106, C1 = 6.57$10K14, gm13= 5.6$10K4, gm4= 1.37

$10K4, Rout = 20000, Cout = 20$10K12, Cc = 1.55$10K12, wz1=gm4

2$3.14$ Cc , wz1, gm13, gm2,

gm4, Rc, R1, Rout, C1, Cout, Cc, k

C1 = 6.570000000 10-14, Cc = 1.550000000 10-12, Cout = 2.000000000 10-11, R1

= 1.500000 106, Rc = 15000., Rout = 20000., gm13= 0.0005600000000, gm2

= 0.0001500000000, gm4= 0.0001370000000, k = 4., wz1= 1.407437847 107

solve k = 4, gm2= 1.5$10K4, Rc = 15000, R1 = 1.5$106, C1 = 6.57$10K14, gm13= 4.156$10K4, gm4

= 1.37$10K4, Rout = 20000, Cout = 20$10K12, Cc = 1.55$10K12, wz2=gm13

2$3.14$ k$C1 , wz2, gm13,

gm2, gm4, Rc, R1, Rout, C1, Cout, Cc, k

C1 = 6.570000000 10-14, Cc = 1.550000000 10-12, Cout = 2.000000000 10-11, R1

= 1.500000 106, Rc = 15000., Rout = 20000., gm13= 0.0004156000000, gm2

= 0.0001500000000, gm4= 0.0001370000000, k = 4., wz2= 2.518201825 108

solve ft = Kgm2$R1$gm13$Rout2

$1

R1 gm13 Rout Cc , ft

ft =K12

gm2Cc

solve k = 4, gm2= 1.5$10K4, Rc = 15000, R1 = 1.5$106, C1 = 6.57$10K14, gm4= 1.37$10K4, gm13= 5.6

O O

(9)(9)

$10K4, Rout = 20000, Cout = 20$10K12, Cc = 1.55$10K12, ft = 12$ 6.28

$ gm2Cc , ft, gm2, gm4,

gm13, Rc, R1, Rout, C1, Cout, Cc, k

C1 = 6.570000000 10-14, Cc = 1.550000000 10-12, Cout = 2.000000000 10-11, R1

= 1.500000 106, Rc = 15000., Rout = 20000., ft = 7.704951715 106, gm13

= 0.0005600000000, gm2= 0.0001500000000, gm4= 0.0001370000000, k = 4.

O O

(1)(1)

(3)(3)

O O

(2)(2)

O O

(5)(5)

(4)(4)

C. Design III Tail Compensated Small Signal Analysis : Summary of DC Gain, Poles and ZerosSummary of DC Gain, Poles and Zeros

Gain =12

r1 gm13 Rout gm2

Gain =12

r1 gm13 Rout gm2

solve k = 4, gm2 = 1.76$10K4, R1= 1.7$106, Cgd = 6.54$10K14, C1 = 56.7$10K14, gm13

= 5.59$10K4, Rout= 20000, Cout = 20$10K12, Ct = 2.75$10K12, wp1

=2 gm2

2$227

$ gm2 R1 gm13 Rout Ct, wp1, gm2, gm13, R1, Rout, C1, Cout, Cgd, Ct, k

C1 = 5.67#10 -13, Cgd = 6.54#10 -14, Cout = 2.00#10 -11, Ct = 2.75#10 -12, R1 = 1.70

#106, Rout = 2.00#104, gm13= 5.59#10 -4, gm2= 1.76#10 -4, k = 4.00#100, wp1 = 6.09

#103

solve wp1 =2 gm2

gm2 R1 gm13 Rout Cc , wp1

wp1 =2

R1 gm13 Rout Cc

wp1 =2

R1 gm2 Rout Cc, wp2 =K gm1 R1 gm2 Rout Cc K2 C1 R1 Cout Rout gm1

CC1 R1 k gm1 Rout CcK 2 C1 R1 Rout gm1 CcK 2 Rout Cgd gm1 C1 R1KRout Cgd CcKC1 R1 CcKRout R1 Cgd gm1 CcK 2 Cout Rout gm1 R1 CgdKCout Rout CcKRout R1 gm2 Cgd CcC k gm1 Rout Cc R1 CgdKCc R1 Cgd

solve k = 4, gm2 = 1.76$10K4, R1= 1.7$106, Cgd = 6.54$10K14, C1 = 56.7$10K14, gm13

= 5.59$10K4, Rout= 20000, Cout = 20$10K12, Ct = 2.75$10K12, wp2 =

Kgm13 Ct

K2 C1 CoutCC1 k CtK 2 C1 CtK 2 Cout Cgd, wp2, gm2, gm13, R1, Rout, C1,

(8)(8)

(6)(6)

(7)(7)

(9)(9)

(10)(10)

Cout, Cgd, Ct, k

C1 = 5.670000000 10-13, Cgd = 6.540000000 10-14, Cout = 2.000000000 10-11, Ct

= 2.750000000 10-12, R1 = 1.700000 106, Rout = 20000., gm13= 0.0005590000000, gm2

= 0.0001760000000, k = 4., wp2 = 6.931574794 107

solve wp2 =

K gm1 R1 gm2 Rout Cc K2 C1 R1 Cout Rout gm1CC1 R1 k gm1 Rout Cc

K 2 C1 R1 Rout gm1 CcK 2 Cout Rout gm1 R1 Cgd , wp2

wp2 =Kgm2 Cc

K2 C1 CoutCC1 k CcK 2 C1 CcK 2 Cout Cgd

wz1=k gm1C gm1 R1 gm2

R1 gm2 CcCCcCC1 R1 k gm1K gm1 R1 CgdC k gm1 R1 Cgd

wz1=k gm1C gm1 R1 gm2

R1 gm2 CcCCcCC1 R1 k gm1K gm1 R1 CgdC k gm1 R1 Cgd

solve k = 4, gm2 = 1.76$10K4, R1= 1.7$106, Cgd = 6.54$10K14, C1 = 56.7$10K14, gm13

= 5.59$10K4, Rout= 20000, Cout = 20$10K12, Ct = 2.75$10K12, wz1

=gm2

CtC C1 k gm2gm13 $6.28

, wz1, gm2, gm13, R1, Rout, C1, Cout, Cgd, Ct, k

C1 = 5.670000000 10-13, Cgd = 6.540000000 10-14, Cout = 2.000000000 10-11, Ct

= 2.750000000 10-12, R1 = 1.700000 106, Rout = 20000., gm13= 0.0005590000000, gm2

= 0.0001760000000, k = 4., wz1= 8.090320395 106

solve wz1=gm2 R1 gm13R1 gm13 Ct , wz1

wz1=gm2Ct

(13)(13)

(12)(12)

(11)(11)

solve wp1 =2 gm1

gm1 R1 gm2 Rout CcC 2 C1 R1 gm1 , wp2 =

Kgm2 Cc

K2 C1 CoutCC1 k CcK 2 C1 CcK 2 Cout Cgd , wp1$wp2$wp3

=2$gm1

Rout Cgd Cc C1 R1CCout Rout Cc R1 CgdCC1 R1 Cout Rout Cc, wp1, wp2, wp3

wp1 =2

R1 gm2 Rout CcC 2 C1, wp2 =

Kgm2 Cc

K2 C1 CoutCC1 k CcK 2 C1 CcK 2 Cout Cgd, wp3 =K gm1 K4 C12 Cout

C 2 C12 k CcK 4 C12 CcK 4 C1 Cout CgdK 2 gm2 Rout Cc C1 CoutC gm2 Rout Cc2 C1 kK 2 gm2 Rout Cc2 C1K 2 gm2 Rout Cc Cout CgdRout Cc2 gm2 Cgd C1CCout CgdCC1 Cout

solve k = 4, gm1 = 1.76$10K4, R1= 1.7$106, Cgd = 6.54$10K14, C1 = 56.7$10K14, gm2

= 5.59$10K4, Rout= 20000, Cout = 20$10K12, Cc = 2.75$10K12, wp3 =

K1

Rout Cc2 gm2 C1 Cout $6.28gm1 K2 gm2 Rout Cc C1 CoutC gm2 Rout Cc2 C1 k

K 2 gm2 Rout Cc2 C1K 2 gm2 Rout Cc Cout Cgd , wp3, gm1, gm2, R1, Rout, C1,

Cout, Cgd, Cc, k

C1 = 5.670000000 10-13, Cc = 2.750000000 10-12, Cgd = 6.540000000 10-14, Cout

= 2.000000000 10-11, R1 = 1.700000 106, Rout = 20000., gm1= 0.0001760000000, gm2

= 0.0005590000000, k = 4., wp3 = 1.993057662 107

solve wp3 =K1

Rout Cc2 gm2 C1 Coutgm1 K2 gm2 Rout Cc C1 CoutC gm2 Rout Cc2 C1 k

K 2 gm2 Rout Cc2 C1K 2 gm2 Rout Cc Cout Cgd , wp3

wp3 =Kgm1 K2 C1 CoutCC1 k CcK 2 C1 CcK 2 Cout Cgd

Cc C1 Cout

(18)(18)

(15)(15)

(17)(17)

(14)(14)

(16)(16)

solve wz1=gm1Cc , wz1$wz2=

k gm1C gm1 R1 gm2

C1 R1 Cc, wz1, wz2

wz1=gm1Cc , wz2=

kCR1 gm2C1 R1

solve k = 4, gm2 = 1.76$10K4, R1= 1.7$106, Cgd = 6.54$10K14, C1 = 56.7$10K14, gm13

= 5.59$10K4, Rout= 20000, Cout = 20$10K12, Cc = 2.75$10K12, wz2=R1 gm13

6.28$ C1 R1,

wz2, gm2, gm13, R1, Rout, C1, Cout, Cgd, Cc, k

C1 = 5.670000000 10-13, Cc = 2.750000000 10-12, Cgd = 6.540000000 10-14, Cout

= 2.000000000 10-11, R1 = 1.700000 106, Rout = 20000., gm13= 0.0005590000000, gm2

= 0.0001760000000, k = 4., wz2= 1.569889574 108

solve wz2=R1 gm13 C1 R1

, wz2

wz2=gm13C1

solve wp1 =2

R1 gm2 Rout Cc, wp1$wn$wn

=2$gm1

Rout Cgd Cc C1 R1CCout Rout Cc R1 CgdCC1 R1 Cout Rout Cc, wp1, wn

wn = RootOf Cgd C1CCout CgdCC1 Cout _Z2K gm1 gm2 , wp1

=2

R1 gm2 Rout Cc

allvalues wn = RootOf Cgd C1CCout CgdCC1 Cout _Z2K gm1 gm2

wn =gm1 gm2

Cgd C1CCout CgdCC1 Cout, wn =K

gm1 gm2Cgd C1CCout CgdCC1 Cout

solve k = 4, gm1 = 1.76$10K4, R1= 1.7$106, Cgd = 6.54$10K14, C1 = 56.7$10K14, gm2

(19)(19)

= 5.59$10K4, Rout= 20000, Cout = 20$10K12, Cc = 2.75$10K12, wn =1

2$227

$gm2 gm13

Cgd C1CCout CgdCC1 Cout, wn, gm13, gm2, R1, Rout, C1, Cout, Cgd, Cc,

k

solve wp1 =2

R1 gm13 Rout Cc, wn =

gm2 gm13Cgd C1CCout CgdCC1 Cout

, wp1$wn$q = 2

$gm2 2 C1 R1 Cout Rout gm2KC1 R1 k gm2 Rout CcC 2 C1 R1 Rout gm2 Cc

C 2 Rout Cgd gm2 C1 R1CRout Cgd CcCC1 R1 CcCRout R1 Cgd gm2 Cc

C 2 Cout Rout gm2 R1 CgdCCout Rout CcCRout R1 gm13 Cgd CcK k gm2 Rout Cc R1 Cgd

CCc R1 Cgd , wp1, wn, q

q =K gm2 R1 gm13 Rout Cc gm2 gm13Cgd C1CCout CgdCC1 Cout

K2 C1 R1 Cout Rout gm2CC1 R1 k gm2 Rout CcK 2 C1 R1 Rout gm2 Cc

K 2 Rout Cgd gm2 C1 R1KRout Cgd CcKC1 R1 CcKRout R1 Cgd gm2 Cc

K 2 Cout Rout gm2 R1 CgdKCout Rout CcKRout R1 gm13 Cgd Cc

C k gm2 Rout Cc R1 CgdKCc R1 Cgd , wn =gm2 gm13

Cgd C1CCout CgdCC1 Cout , wp1

=2

R1 gm13 Rout Cc

solve k = 4, gm1 = 1.76$10K4, R1= 1.7$106, Cgd = 6.54$10K14, C1 = 56.7$10K14, gm2

= 5.59$10K4, Rout= 20000, Cout = 20$10K12, Cc = 2.75$10K12, q =

(20)(20)

(22)(22)

(21)(21)

O O

K gm1 R1 gm2 Rout Cc gm1 gm2Cgd C1CCout CgdCC1 Cout

K2 C1 R1 Cout Rout gm1

CC1 R1 k gm1 Rout CcK 2 C1 R1 Rout gm1 CcK 2 Rout Cgd gm1 C1 R1KRout Cgd CcKC1 R1 CcKRout R1 Cgd gm1 CcK 2 Cout Rout gm1 R1 CgdKCout Rout CcKRout R1 gm2 Cgd CcC k gm1 Rout Cc R1 CgdKCc R1 Cgd , q, gm1, gm2, R1, Rout,C1, Cout, Cgd, Cc, k

C1 = 5.670000000 10-13, Cc = 2.750000000 10-12, Cgd = 6.540000000 10-14, Cout

= 2.000000000 10-11, R1 = 1.700000 106, Rout = 20000., gm1= 0.0001760000000, gm2

= 0.0005590000000, k = 4., q = 0.7601904760

solve ft = Kgm2$R1$gm13$Rout2

$2

gm13$Rout$R1$Ct , ft

ft =Kgm2Ct

solve k = 4, gm2 = 1.76$10K4, R1= 1.7$106, Cgd = 6.54$10K14, C1 = 56.7$10K14, gm13

= 5.59$10K4, Rout= 20000, Cout = 20$10K12, Ct = 2.75$10K12, ft = gm2

Ct$2$3.14, ft,

gm2, gm13, R1, Rout, C1, Cgd, Cout, Ct, k

C1 = 5.670000000 10-13, Cgd = 6.540000000 10-14, Cout = 2.000000000 10-11, Ct

= 2.750000000 10-12, R1 = 1.700000 106, Rout = 20000., ft = 1.019108280 107, gm13

= 0.0005590000000, gm2= 0.0001760000000, k = 4.

(2)(2)

(3)(3)

O O

O O

O O O O

(1)(1)

A. Design III Miller Compensated PSRR Small Signal Analysis, Summary of PSRR DC Gain, Poles and Zeros

A.Design III Miller Compensated PSRR Small Signal Analysis, Summary of PSRR DC Gain, Polesand Zeros

Vout= 2 Vddro13 gm2 ro2 gm13

Vout = 2 Vddro13 gm2 ro2 gm13

solve gm2= 1.51$10K4

, gm4= 1.51$10K4

, gm13= 5.7$10K4

, ro1

= 1$106, ro2 = 1$10

6, ro4 = 1$10

6, ro6 = 1$10

6, ro13 = 247$10

3, K

= 4, Routp= 37400, Cm = 1.25$10K12

, C1 = 530$10K15

, CL = 20

$10K12

, Vdd= 1, Vout= 2 Routp Vddro13 Routp gm2 ro2 gm13

, Vout, Vdd,

gm13, gm4, gm2, ro1, ro2, ro4, ro6, ro13, K, Routp, Cm, C1, CL

C1 = 5.300000000 10-13, CL = 2.000000000 10-11, Cm = 1.250000000 10-12, K = 4., Routp

= 37400., Vdd = 1., Vout = 0.00009407651902, gm13= 0.0005700000000, gm2

= 0.0001510000000, gm4= 0.0001510000000, ro1= 1.000000 106, ro13= 2.47000 105, ro2

= 1.000000 106, ro4= 1.000000 106, ro6= 1.000000 106

solve gm2= 1.51$10K4

, gm4= 1.51$10K4

, gm13= 5.7$10K4

, ro1 = 1

$106, ro2 = 1$10

6, ro4 = 1$10

6, ro6 = 1$10

6, ro13 = 250$10

3, K

= 4, Routp= 36000, Rm= 15000, Cm = 1.25$10K12

, Cgd = 65

(5)(5)

(4)(4)

$10K15

, C1 = 530$10K15

, CL = 20$10K12

, Vdd= 1, wp1

= 1Cm ro2 gm13 ro13

, wp1, Vdd, gm2, gm4, gm13, ro1, ro2,

ro4, ro6, ro13, K, Routp, Rm, Cm, Cgd, C1, CL

C1 = 5.300000000 10-13, CL = 2.000000000 10-11, Cgd = 6.500000000 10-14, Cm

= 1.250000000 10-12, K = 4., Rm = 15000., Routp = 36000., Vdd = 1., gm13

= 0.0005700000000, gm2= 0.0001510000000, gm4= 0.0001510000000, ro1

= 1.000000 106, ro13= 2.50000 105, ro2= 1.000000 106, ro4= 1.000000 106, ro6

= 1.000000 106, wp1 = 5614.035088

solve gm2= 1.51$10K4

, gm4= 1.51$10K4

, gm13= 5.7$10K4

, ro1 = 1

$106, ro2 = 1$10

6, ro4 = 1$10

6, ro6 = 1$10

6, ro13 = 250$10

3, K

= 4, Routp= 36000, Rm= 15000, Cm = 1.25$10K12

, Cgd = 65

$10K15

, C1 = 530$10K15

, CL = 20$10K12

, Vdd= 1, wp2

= Cm ro2 gm13 ro136.28$ Rm Cm ro2 Cgd gm13 ro13

, wp2, Vdd, gm2, gm4,

gm13, ro1, ro2, ro4, ro6, ro13, K, Routp, Rm, Cm, Cgd, C1, CL

C1 = 5.300000000 10-13, CL = 2.000000000 10-11, Cgd = 6.500000000 10-14, Cm

= 1.250000000 10-12, K = 4., Rm = 15000., Routp = 36000., Vdd = 1., gm13

= 0.0005700000000, gm2= 0.0001510000000, gm4= 0.0001510000000, ro1

= 1.000000 106, ro13= 2.50000 105, ro2= 1.000000 106, ro4= 1.000000 106, ro6

= 1.000000 106, wp2 = 1.633186347 108

solve gm2= 1.51$10K4

, gm4= 1.51$10K4

, gm13= 5.7$10K4

, ro1 = 1

(6)(6)

O O

(7)(7)

$106, ro2 = 1$10

6, ro4 = 1$10

6, ro6 = 1$10

6, ro13 = 250$10

3, K

= 4, Routp= 36000, Rm= 15000, Cm = 1.25$10K12

, Cgd = 65

$10K15

, C1 = 530$10K15

, CL = 20$10K12

, Vdd= 1, wp3

= gm136.28$ C1

, wp3, Vdd, gm2, gm4, gm13, ro1, ro2, ro4, ro6,

ro13, K, Routp, Rm, Cm, Cgd, C1, CL

C1 = 5.300000000 10-13, CL = 2.000000000 10-11, Cgd = 6.500000000 10-14, Cm

= 1.250000000 10-12, K = 4., Rm = 15000., Routp = 36000., Vdd = 1., gm13

= 0.0005700000000, gm2= 0.0001510000000, gm4= 0.0001510000000, ro1

= 1.000000 106, ro13= 2.50000 105, ro2= 1.000000 106, ro4= 1.000000 106, ro6

= 1.000000 106, wp3 = 1.712534551 108

solve gm2= 1.51$10K4

, gm4= 1.51$10K4

, gm13= 5.7$10K4

,

ro1 = 1$106, ro2 = 1$10

6, ro4 = 1$10

6, ro6 = 1$10

6, ro13

= 250$103, K = 4, Routp= 36000, Rm= 15000, Cm = 1.25

$10K12

, Cgd = 65$10K15

, C1 = 530$10K15

, CL = 20$10K12

,

Vdd= 1, wz1 = 2 ro13C ro13 Routp gm2 ro2 gm13C 2 Routp 6.28$ 2 Cm ro2 RoutpC 2 C1 ro2 ro13C 2 ro2 Cgd RoutpC 2 Rm Cm ro13C 2 C1 ro2 RoutpC 2 Cm ro2 ro13C 2 CL ro13 RoutpC 2 ro13 Routp CgdKCm ro2 ro13 Routp gm2CRm Cm ro13 Routp gm2 ro2 gm13K ro2 Cgd ro13 Routp gm2C 2 Cm ro2 ro13 Routp gm13

(9)(9)

(8)(8)

O O

O O

(7)(7)

O O

C 2 Rm Cm RoutpC 2 ro2 Cgd ro13C 2 Cm ro13 RoutpC 2 ro2 Cgd ro13 Routp gm13 , wz1, Vdd, gm2, gm4,gm13, ro1, ro2, ro4, ro6, ro13, K, Routp, Rm, Cm, Cgd, C1,CL

C1 = 5.300000000 10-13, CL = 2.000000000 10-11, Cgd = 6.500000000 10-14, Cm

= 1.250000000 10-12, K = 4., Rm = 15000., Routp = 36000., Vdd = 1., gm13

= 0.0005700000000, gm2= 0.0001510000000, gm4= 0.0001510000000, ro1

= 1.000000 106, ro13= 2.50000 105, ro2= 1.000000 106, ro4= 1.000000 106, ro6

= 1.000000 106, wz1= 4.459713939 106

wz1 = 1Rm Cm

wz1=1

Rm Cm

solve gm1= 1.51$10K4

, gm4= 1.51$10K4

, gm7= 5.7$10K4

,

ro1 = 1$106, ro2 = 1$10

6, ro4 = 1$10

6, ro6 = 1$10

6, ro7

= 250$103, K = 4, Routp= 36000, Rcm= 15000, Ccm= 1.25

$10K12

, Cgd = 65$10K15

, C1 = 530$10K15

, CL = 20$10K12

,

Vdd= 1, wz2 = Rcm Ccm ro7 Routp gm1 ro1 gm7 6.28$ KRcm Ccm ro1 Cgd ro7 Routp gm1C 2 Rcm Ccm ro1 Cgd ro7 Routp gm7 , wz2, Vdd, gm1,gm4, gm7, ro1, ro2, ro4, ro6, ro7, K, Routp, Rcm, Ccm, Cgd,C1, CL

C1 = 5.300000000 10-13, CL = 2.000000000 10-11, Ccm = 1.250000000 10-12, Cgd

= 6.500000000 10-14, K = 4., Rcm = 15000., Routp = 36000., Vdd = 1., gm1

= 0.0001510000000, gm4= 0.0001510000000, gm7= 0.0005700000000, ro1

= 1.000000 106, ro2= 1.000000 106, ro4= 1.000000 106, ro6= 1.000000 106, ro7

= 2.50000 105, wz2= 2.131976980 108

O O

O O

O O

(11)(11)

(10)(10)

O O

(7)(7)

O O

(12)(12)

wz2 = 12

gm2Cgd

wz2=12

gm2Cgd

solve gm1= 1.51$10K4

, gm4= 1.51$10K4

, gm7= 5.7$10K4

,

ro1 = 1$106, ro2 = 1$10

6, ro4 = 1$10

6, ro6 = 1$10

6, ro7

= 250$103, K = 4, Routp= 36000, Rcm= 15000, Ccm= 1.25

$10K12

, Cgd = 65$10K15

, C1 = 530$10K15

, CL = 20$10K12

,

Vdd= 1, wz3 = 16.28$2

gm1 gm7C1 CL

, wz3, Vdd, gm1, gm4,

gm7, ro1, ro2, ro4, ro6, ro7, K, Routp, Rcm, Ccm, Cgd, C1,CL

C1 = 5.300000000 10-13, CL = 2.000000000 10-11, Ccm = 1.250000000 10-12, Cgd

= 6.500000000 10-14, K = 4., Rcm = 15000., Routp = 36000., Vdd = 1., gm1

= 0.0001510000000, gm4= 0.0001510000000, gm7= 0.0005700000000, ro1

= 1.000000 106, ro2= 1.000000 106, ro4= 1.000000 106, ro6= 1.000000 106, ro7

= 2.50000 105, wz3= 6.464817930 1014

wz3 = 12

gm2 gm13C1 CL

wz3=12

gm2 gm13C1 CL

O O

(3)(3)

O O

O O

(2)(2)

O O

O O

(4)(4)

O O

O O

O O

(1)(1)

B. Design III Cascode Compensated PSRR Small Signal Analysis, Summary of PSRR DC Gain, Poles and Zeros

B.Design III Cascode Compensated PSRR Small Signal Analysis, Summary of PSRR DC Gain,Poles and Zeros

Vout =2 Vdd

ro13 ro2 gm13 gm2Vout = 2 Vdd

ro13 ro2 gm13 gm2

solve gm2= 1.51$10K4

, gm4= 1.51$10K4

, gm13= 5.7$10K4

,

ro1 = 1$106, ro2 = 1$10

6, ro4 = 1$10

6, ro6 = 1$10

6, ro13

= 247$103, K = 4, Routp= 37400, Cc= 1.55$10

K12, C1 = 530

$10K15

, CL = 20$10K12

, Vdd= 1, Vout

= 2 Routp Vddro13 Routp gm2 ro2 gm13

, Vout, Vdd, gm13, gm4,

gm2, ro1, ro2, ro4, ro6, ro13, K, Routp, Cc, C1, CL

C1 = 5.300000000 10-13, CL = 2.000000000 10-11, Cc = 1.550000000 10-12, K = 4., Routp

= 37400., Vdd = 1., Vout = 0.00009407651902, gm13= 0.0005700000000, gm2

= 0.0001510000000, gm4= 0.0001510000000, ro1= 1.000000 106, ro13= 2.47000 105, ro2

= 1.000000 106, ro4= 1.000000 106, ro6= 1.000000 106

solve gm2= 1.51$10K4, gm4= 1.4$10K4, gm13= 5.7$10K4, ro1= 1.03$106, ro2= 1.03$106, ro4

= 1.05$106, ro6= 1.05$106, ro13= 250$103, K = 4, Routp = 36000, Cc = 1.55$10K12, Cgd

= 65$10K15, C1 = 530$10K15, CL = 20$10K12, Vdd = 1, wp2

O O

O O

(6)(6)

(7)(7)

(8)(8)

(4)(4)

O O

(5)(5)

O O

O O

=gm4 gm13 ro13 Cc ro2

6.28$ ro13 gm4 Cc ro2 C1 , wp2, Vdd, gm2, gm4, gm13, ro1, ro2, ro4, ro6, ro13, K,

Routp, Cc, Cgd, C1, CL

C1 = 5.300000000 10-13, CL = 2.000000000 10-11, Cc = 1.550000000 10-12, Cgd

= 6.500000000 10-14, K = 4., Routp = 36000., Vdd = 1., gm13= 0.0005700000000, gm2

= 0.0001510000000, gm4= 0.0001400000000, ro1= 1.030000 106, ro13= 2.50000 105, ro2

= 1.030000 106, ro4= 1.050000 106, ro6= 1.050000 106, wp2 = 1.712534551 108

wp2 =gm13C1

wp2 =gm13C1

wp3 =gm4Cgd

wp3 =gm4Cgd

solve gm2= 1.51$10K4, gm4= 1.4$10K4, gm13= 5.7$10K4, ro1= 1.03$106, ro2= 1.03$106, ro4

= 1.05$106, ro6= 1.05$106, ro13= 250$103, K = 4, Routp = 36000, Cc = 1.55$10K12, Cgd

= 65$10K15, C1 = 530$10K15, CL = 20$10K12, Vdd = 1, wp3 =gm4

6.28$ Cgd , wp3, Vdd,

gm2, gm4, gm13, ro1, ro2, ro4, ro6, ro13, K, Routp, Cc, Cgd, C1, CL

C1 = 5.300000000 10-13, CL = 2.000000000 10-11, Cc = 1.550000000 10-12, Cgd

= 6.500000000 10-14, K = 4., Routp = 36000., Vdd = 1., gm13= 0.0005700000000, gm2

= 0.0001510000000, gm4= 0.0001400000000, ro1= 1.030000 106, ro13= 2.50000 105, ro2

= 1.030000 106, ro4= 1.050000 106, ro6= 1.050000 106, wp3 = 3.429691328 108

solve gm2= 1.51$10K4, gm4= 1.4$10K4, gm7= 5.7$10K4, ro1= 1.03$106, ro2= 1.03$106, ro4

= 1.05$106, ro6= 1.05$106, ro7= 250$103, K = 4, Routp = 36000, Cc = 1.55$10K12, Cgd

= 65$10K15, C1 = 530$10K15, CL = 20$10K12, Vdd = 1, wz1= gm2

6.28$ 2 Cc , wz1, Vdd,

gm2, gm4, gm7, ro1, ro2, ro4, ro6, ro7, K, Routp, Cc, Cgd, C1, CL

C1 = 5.300000000 10-13, CL = 2.000000000 10-11, Cc = 1.550000000 10-12, Cgd

= 6.500000000 10-14, K = 4., Routp = 36000., Vdd = 1., gm2= 0.0001510000000, gm4

= 0.0001400000000, gm7= 0.0005700000000, ro1= 1.030000 106, ro2= 1.030000 106, ro4

(9)(9)

O O

O O

(10)(10)

(8)(8)

(11)(11)

(12)(12)

(4)(4)

O O

= 1.050000 106, ro6= 1.050000 106, ro7= 2.50000 105, wz1= 7.756318060 106

wz1=12

gm2Ccwz1=

12

gm2Cc

solve gm1= 1.51$10K4, gm4= 1.4$10K4, gm7= 5.7$10K4, ro1= 1.03$106, ro2= 1.03$106, ro4

= 1.05$106, ro6= 1.05$106, ro7= 250$103, K = 4, Routp = 36000, Cc = 1.55$10K12, Cgd

= 65$10K15, C1 = 530$10K15, CL = 20$10K12, Vdd = 1, wz2=gm4

6.28$ Cgd , wz2, Vdd,

gm1, gm4, gm7, ro1, ro2, ro4, ro6, ro7, K, Routp, Cc, Cgd, C1, CL

C1 = 5.300000000 10-13, CL = 2.000000000 10-11, Cc = 1.550000000 10-12, Cgd

= 6.500000000 10-14, K = 4., Routp = 36000., Vdd = 1., gm1= 0.0001510000000, gm4

= 0.0001400000000, gm7= 0.0005700000000, ro1= 1.030000 106, ro2= 1.030000 106, ro4

= 1.050000 106, ro6= 1.050000 106, ro7= 2.50000 105, wz2= 3.429691328 108

solve gm1= 1.51$10K4, gm4= 1.4$10K4, gm13= 5.7$10K4, ro1= 1.03$106, ro2= 1.03$106, ro4= 1.05

$106, ro6= 1.05$106, ro7= 250$103, K = 4, Routp = 36000, Ccc = 1.55$10K12, Cgd = 65$10K15, C1

= 530$10K15, CL = 20$10K12, Vdd = 1, wz3=Cgd gm13CL C1

, wz3, Vdd, gm1, gm4, gm13, ro1,

ro2, ro4, ro6, ro7, K, Routp, Ccc, Cgd, C1, CL

C1 = 5.300000000 10-13, CL = 2.000000000 10-11, Ccc = 1.550000000 10-12, Cgd

= 6.500000000 10-14, K = 4., Routp = 36000., Vdd = 1., gm1= 0.0001510000000, gm13

= 0.0005700000000, gm4= 0.0001400000000, ro1= 1.030000 106, ro2= 1.030000 106, ro4

= 1.050000 106, ro6= 1.050000 106, ro7= 2.50000 105, wz3= 3.495283019 106

solve wz3=KCgd ro7 Routp ro2 gm13 gm1ro7 Routp ro2 gm1 CL C1

, wz3

wz3=KCgd gm13CL C1

O O

O O

(8)(8)

(4)(4)

(4)(4)

(1)(1)

(2)(2)

O O

(3)(3)

O O

C. Design III Tail Compensated PSRR Small Signal Analysis, Summary of PSRR DC Gain, Poles and Zeros

C.Design III Tail Compensated PSRR Small Signal Analysis, Summary of PSRR DC Gain, Polesand Zeros

Vout= 2 Vddro13 gm2 ro2 gm13

Vout =2 Vdd

ro13 gm2 ro2 gm13

solve gm2= 1.51$10K4

, gm4= 1.51$10K4

, gm13= 5.7$10K4

, ro1

= 1$106, ro2 = 1$10

6, ro4 = 1$10

6, ro6 = 1$10

6, ro13 = 247$10

3, K

= 4, Routp= 37400, Ct = 2.75$10K12

, C1 = 530$10K15

, CL = 20

$10K12

, Vdd= 1, Vout= 2 Routp Vddro13 Routp gm2 ro2 gm13

, Vout, Vdd,

gm13, gm4, gm2, ro1, ro2, ro4, ro6, ro13, K, Routp, Ct, C1, CL

C1 = 5.300000000 10-13, CL = 2.000000000 10-11, Ct = 2.750000000 10-12, K = 4., Routp

= 37400., Vdd = 1., Vout = 0.00009407651902, gm13= 0.0005700000000, gm2

= 0.0001510000000, gm4= 0.0001510000000, ro1= 1.000000 106, ro13= 2.47000 105, ro2

= 1.000000 106, ro4= 1.000000 106, ro6= 1.000000 106

solve gm2= 1.51$10K4, gm4= 1.51$10K4, gm13= 5.7$10K4, ro1= 1.03$106, ro2= 1.03$106, ro4= 1

$106, ro6= 1$106, ro13= 250$103, K = 4, Routp = 36400, Ct = 2.75$10K12, Cgd = 65$10K15, C1 = 505

$10K15, CL = 20$10K12, Vdd = 1, wp1 =2 ro1 gm2

6.28 2 ro1 ro2 Cgd gm13 ro13 gm2, wp1, Vdd, gm2,

gm4, gm13, ro1, ro2, ro4, ro6, ro13, K, Routp, Ct, Cgd, C1, CL

C1 = 5.050000000 10-13, CL = 2.000000000 10-11, Cgd = 6.500000000 10-14, Ct

= 2.750000000 10-12, K = 4., Routp = 36400., Vdd = 1., gm13= 0.0005700000000, gm2

(7)(7)

(4)(4)

(5)(5)

(8)(8)

(6)(6)

= 0.0001510000000, gm4= 0.0001510000000, ro1= 1.030000 106, ro13= 2.50000 105, ro2

= 1.030000 106, ro4= 1.000000 106, ro6= 1.000000 106, wp1 = 16690.71381

wp1 =1

ro2 Cgd gm13 ro13wp1 =

1ro2 Cgd gm13 ro13

solve gm2= 1.51$10K4, gm4= 1.51$10K4, gm13= 5.7$10K4, ro1= 1.03$106, ro2= 1.03$106, ro4= 1

$106, ro6= 1$106, ro13= 250$103, K = 4, Routp = 36400, Ct = 2.75$10K12, Cgd = 65$10K15, C1 = 505

$10K15, CL = 20$10K12, Vdd = 1, wp2 =2 ro1 gm2 Cgd gm13 ro13

6.28$ ro1 Cgd gm13 ro13 Ct , wp2, Vdd, gm2, gm4,

gm13, ro1, ro2, ro4, ro6, ro13, K, Routp, Ct, Cgd, C1, CL

C1 = 5.050000000 10-13, CL = 2.000000000 10-11, Cgd = 6.500000000 10-14, Ct

= 2.750000000 10-12, K = 4., Routp = 36400., Vdd = 1., gm13= 0.0005700000000, gm2

= 0.0001510000000, gm4= 0.0001510000000, ro1= 1.030000 106, ro13= 2.50000 105, ro2

= 1.030000 106, ro4= 1.000000 106, ro6= 1.000000 106, wp2 = 1.748697163 107

wp2 =2 gm2Ct

wp2 =2 gm2Ct

solve gm1= 1.51$10K4, gm4= 1.51$10K4, gm7= 4.7$10K4, ro1= 1.03$106, ro2= 1.03$106, ro4= 1$106,

ro6= 1$106, ro7= 250$103, K = 4, Routp = 36400, Cct = 2.75$10K12, Cgd = 65$10K15, C1 = 505

$10K15, CL = 20$10K12, Vdd = 1, wp3 =gm7

6.28$ C1 , wp3, Vdd, gm1, gm4, gm7, ro1, ro2, ro4,

ro6, ro7, K, Routp, Cct, Cgd, C1, CL

C1 = 5.050000000 10-13, CL = 2.000000000 10-11, Cct = 2.750000000 10-12, Cgd

= 6.500000000 10-14, K = 4., Routp = 36400., Vdd = 1., gm1= 0.0001510000000, gm4

= 0.0001510000000, gm7= 0.0004700000000, ro1= 1.030000 106, ro2= 1.030000 106, ro4

= 1.000000 106, ro6= 1.000000 106, ro7= 2.50000 105, wp3 = 1.481995333 108

wz1= 2 ro7 gm1C 2 Routp gm1C ro7 Routp gm12 KC gm12 ro2 ro7 Routp gm72 ro2 Cgd Routp gm1CRoutp CctC 2 ro2 Cgd gm7 ro7 Routp gm1C 2 ro2 Cgd ro7 gm1

(9)(9)

(10)(10)

(4)(4)

(11)(11)

C 2 C1 ro2 ro7 gm1C ro2 Cgd ro7 Routp gm12 KC 2 CL ro7 Routp gm1C ro7 CctC ro7 Routp gm1 CctK gm12 ro2 ro7 Routp CgdC 2 ro7 Routp Cgd gm1CC1 ro2 ro7 Routp gm12 KC 2 C1 ro2 Routp gm1C gm1 ro2 Cct ro7 Routp gm7

wz1= 2 ro7 gm1C 2 Routp gm1C ro7 Routp gm12 KC gm12 ro2 ro7 Routp gm72 ro2 Cgd Routp gm1CRoutp CctC 2 ro2 Cgd gm7 ro7 Routp gm1C 2 ro2 Cgd ro7 gm1C 2 C1 ro2 ro7 gm1C ro2 Cgd ro7 Routp gm12 KC 2 CL ro7 Routp gm1C ro7 CctC ro7 Routp gm1 CctK ro2 Cgd ro7 Routp gm12

C 2 ro7 Routp Cgd gm1CC1 ro2 ro7 Routp gm12 KC 2 C1 ro2 Routp gm1C gm1 ro2 Cct ro7 Routp gm7

solve gm1= 1.51$10K4, gm4= 1.51$10K4, gm7= 4.7$10K4, ro1= 1.03$106, ro2= 1.03$106, ro4= 1$106,

ro6= 1$106, ro7= 250$103, K = 4, Routp = 36400, Cct = 2.75$10K12, Cgd = 65$10K15, C1 = 505

$10K15, CL = 20$10K12, Vdd = 1, wp3 =gm7C1 , wp3, Vdd, gm1, gm4, gm7, ro1, ro2, ro4, ro6, ro7,

K, Routp, Cct, Cgd, C1, CL

wz1= 2 ro7 gm1C 2 Routp gm1C ro7 Routp gm12 KC gm12 ro2 ro7 Routp gm72 ro2 Cgd Routp gm1CRoutp CctC 2 ro2 Cgd gm7 ro7 Routp gm1C 2 ro2 Cgd ro7 gm1C 2 C1 ro2 ro7 gm1C ro2 Cgd ro7 Routp gm12 KC 2 CL ro7 Routp gm1C ro7 CctC ro7 Routp gm1 CctK ro2 Cgd ro7 Routp gm12

C 2 ro7 Routp Cgd gm1CC1 ro2 ro7 Routp gm12 KC 2 C1 ro2 Routp gm1C gm1 ro2 Cct ro7 Routp gm7

solve gm1= 1.51$10K4, gm4= 1.51$10K4, gm7= 4.7$10K4, ro1= 1.03$106, ro2= 1.03$106, ro4= 1$106,

ro6= 1$106, ro7= 250$103, K = 4, Routp = 26400, Cct = 2.75$10K12, Cgd = 65$10K15, C1 = 505

$10K15, CL = 20$10K12, Vdd = 1, wz1=gm12 ro2 ro7 Routp gm7

6.28$ gm1 ro2 Cct ro7 Routp gm7 , wz1, Vdd, gm1,

gm4, gm7, ro1, ro2, ro4, ro6, ro7, K, Routp, Cct, Cgd, C1, CL

C1 = 5.050000000 10-13, CL = 2.000000000 10-11, Cct = 2.750000000 10-12, Cgd

= 6.500000000 10-14, K = 4., Routp = 26400., Vdd = 1., gm1= 0.0001510000000, gm4

(15)(15)

(13)(13)

(14)(14)

(12)(12)

(4)(4)

(11)(11)

= 0.0001510000000, gm7= 0.0004700000000, ro1= 1.030000 106, ro2= 1.030000 106, ro4

= 1.000000 106, ro6= 1.000000 106, ro7= 2.50000 105, wz1= 8.743485814 106

solve wz1=gm12 ro2 ro7 Routp gm7gm1 ro2 Cct ro7 Routp gm7 , wz1

wz1=gm1Cct

solve wz1=gm1Cct , wz1$wz2= 2 ro7 gm1C 2 Routp gm1C ro7 Routp gm12 K

C gm12 ro2 ro7 Routp gm7 CL ro7 Routp CctCC1 ro2 Routp CctC 2 C1 ro2 gm1 ro7 Routp CgdC 2 ro2 Cgd CL ro7 Routp gm1C ro2 Cgd Routp CctCC1 ro2 ro7 Routp gm1 CctC ro2 Cgd ro7 CctC ro7 Routp Cgd CctCC1 ro2 ro7 CctC 2 C1 ro2 CL ro7 Routp gm1C ro2 Cgd gm7 ro7 Routp Cct , wz1, wz2

wz1=gm1Cct , wz2= Cct 2 ro7C 2 RoutpC ro7 Routp gm1 K

C gm1 ro2 ro7 Routp gm7 CL ro7 Routp CctCC1 ro2 Routp CctC 2 C1 ro2 gm1 ro7 Routp CgdC 2 ro2 Cgd CL ro7 Routp gm1C ro2 Cgd Routp CctCC1 ro2 ro7 Routp gm1 CctC ro2 Cgd ro7 CctC ro7 Routp Cgd CctCC1 ro2 ro7 CctC 2 C1 ro2 CL ro7 Routp gm1C ro2 Cgd gm7 ro7 Routp Cct

solve gm1= 1.51$10K4, gm4= 1.51$10K4, gm7= 4.7$10K4, ro1= 1.03$106, ro2= 1.03$106, ro4= 1$106,

ro6= 1$106, ro7= 250$103, K = 4, Routp = 36400, Cct = 2.75$10K12, Cgd = 65$10K15, C1 = 505

$10K15, CL = 20$10K12, Vdd = 1, wz2=Cct gm1 ro2 ro7 Routp gm7

6.28$ 2 C1 ro2 CL ro7 Routp gm1 , wz2, Vdd, gm1,

gm4, gm7, ro1, ro2, ro4, ro6, ro7, K, Routp, Cct, Cgd, C1, CL

C1 = 5.050000000 10-13, CL = 2.000000000 10-11, Cct = 2.750000000 10-12, Cgd

= 6.500000000 10-14, K = 4., Routp = 36400., Vdd = 1., gm1= 0.0001510000000, gm4

= 0.0001510000000, gm7= 0.0004700000000, ro1= 1.030000 106, ro2= 1.030000 106, ro4

= 1.000000 106, ro6= 1.000000 106, ro7= 2.50000 105, wz2= 1.018871792 107

solve wz2=Cct gm1 ro2 ro7 Routp gm7

2 C1 ro2 CL ro7 Routp gm1 , wz2

wz2=12

Cct gm7C1 CL

(18)(18)

(17)(17)

(16)(16)

(4)(4)

(11)(11)

solve wz1=gm1Cct , wz2=

12

Cct gm7C1 CL

, wz1$wz2$wz3

=2 ro7 gm1C 2 Routp gm1C ro7 Routp gm12 KC gm12 ro2 ro7 Routp gm7

ro2 Cgd CL ro7 Routp CctCC1 ro2 Cct ro7 Routp CgdCC1 ro2 CL ro7 Routp Cct,

wz1, wz2, wz3

wz1=gm1Cct , wz2=

12

Cct gm7C1 CL

, wz3

=2 C1 CL 2 ro7C 2 RoutpC ro7 Routp gm1 KC gm1 ro2 ro7 Routp gm7

Cct gm7 ro2 ro7 Routp Cgd CLCC1 CgdCC1 CL

solve gm1= 1.51$10K4, gm4= 1.51$10K4, gm7= 4.7$10K4, ro1= 1.03$106, ro2= 1.03$106, ro4= 1$106,

ro6= 1$106, ro7= 250$103, K = 4, Routp = 36400, Cct = 2.75$10K12, Cgd = 65$10K15, C1 = 505

$10K15, CL = 20$10K12, Vdd = 1, wz3=2 C1 CL gm1 ro2 ro7 Routp gm7Cct gm7 ro2 ro7 Routp C1 CL

, wz3, Vdd, gm1,

gm4, gm7, ro1, ro2, ro4, ro6, ro7, K, Routp, Cct, Cgd, C1, CL

C1 = 5.050000000 10-13, CL = 2.000000000 10-11, Cct = 2.750000000 10-12, Cgd

= 6.500000000 10-14, K = 4., Routp = 36400., Vdd = 1., gm1= 0.0001510000000, gm4

= 0.0001510000000, gm7= 0.0004700000000, ro1= 1.030000 106, ro2= 1.030000 106, ro4

= 1.000000 106, ro6= 1.000000 106, ro7= 2.50000 105, wz3= 1.098181818 108

solve wz3=2 C1 CL gm1 ro2 ro7 Routp gm7Cct gm7 ro2 ro7 Routp C1 CL

, wz3

wz3=2 gm1Cct

k = 4, gm1 = 1.76$10K4, R1= 1.7$106, Cgd = 6.54$10K14, C1 = 56.7$10K14, gm7 = 5.59$10K4, Rout= 20000, Cout = 20$10K12, Cc = 2.75$10K12

solve k = 4, gm1 = 1.76$10K4, ro1 = 1.7$106, ro2= 1.03$106, ro4= 1$106, ro6= 1$106, ro7= 250

(20)(20)

(19)(19)

(4)(4)

(11)(11)

O O

$103, Cgd = 6.54$10K14, C1 = 56.7$10K14, gm7 = 5.59$10K4, Rout= 20000, Cout = 20

$10K12, Cct = 2.75$10K12, Vdd = 1, wz1=

gm12 ro2 ro7 Routp gm76.28$ gm1 ro2 Cct ro7 Routp gm7 , wz1, Vdd,

gm1, gm4, gm7, ro1, ro2, ro4, ro6, ro7, k, Rout, Cct, Cgd, C1, Cout

C1 = 5.670000000 10-13, Cct = 2.750000000 10-12, Cgd = 6.540000000 10-14, Cout

= 2.000000000 10-11, Rout = 20000., Vdd = 1., gm1= 0.0001760000000, gm4= gm4, gm7

= 0.0005590000000, k = 4., ro1= 1.700000 106, ro2= 1.030000 106, ro4= 1.000000 106, ro6

= 1.000000 106, ro7= 2.50000 105, wz1= 1.019108280 107

solve k = 4, gm1 = 1.76$10K4, ro1 = 1.7$106, ro2= 1.03$106, ro4= 1$106, ro6= 1$106, ro7= 250

$103, Cgd = 6.54$10K14, C1 = 56.7$10K14, gm7 = 5.59$10K4, Rout= 20000, Cout = 20

$10K12, Cct = 2.75$10K12, Vdd = 1, wz2=

12

Cct gm7C1 Cout

, wz2, Vdd, gm1, gm4, gm7, ro1, ro2,

ro4, ro6, ro7, k, Rout, Cct, Cgd, C1, Cout

C1 = 5.670000000 10-13, Cct = 2.750000000 10-12, Cgd = 6.540000000 10-14, Cout

= 2.000000000 10-11, Rout = 20000., Vdd = 1., gm1= 0.0001760000000, gm4= gm4, gm7

= 0.0005590000000, k = 4., ro1= 1.700000 106, ro2= 1.030000 106, ro4= 1.000000 106, ro6

= 1.000000 106, ro7= 2.50000 105, wz2= 6.777998236 107

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