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A new approach of PMOS LDO voltage regulator,for small analog cores

Alexandre Henrique Rodrigues Neves

Abstract— This paper provides a solution for the present daysneeds, in the integrated low power regulation field, for mobileelectronic applications. In order to design a new low currentcapacitor-less LDO regulator several topologies are presented.Less capacitance, lower current (ILoadmax = 1 mA) andlower output voltage (1.55 V) allow the mobile systems tobecome smaller and more autonomous. The presented regulatoris designed in SMIC 0.13 µm CMOS technology, consuming only96 µA of ground current with a dropout voltage of 150 mV.Simulated results show that the proposed capacitor-less LDOachieves the expected specifications. Monte Carlo simulationsshow that the overall architecture is robust to process variationsand load conditions. Thus, the presented capacitor-less LDOvoltage regulator is designed for system-on-chip (SoC) solutions.

Index Terms— LDO Voltage Regulator, Capacitor Less, Mo-bile Devices, Low Output Voltage and Current, SoC.

I. INTRODUCTION

IN these times technology develops every day, we can seethat in the all types of electronic devices that surround

us. This evolution is especially noticed in mobile deviceslike cellular phones, PDA’s, MP3 players, GPS, and all kinddevices that have a chip inside. Each new model tends tobe smaller and more complete (with more features) thanthe previous version. This evolution is due to the miniatur-ization/integration of the technology and to the increase ofcomplexity in electronic circuits. Consequently this two factorsbring a new challenge: the autonomy of the electronic devices.Therefore, power-managment-units (PMU) need to be moreefficient than ever and integrated circuits (ICs) to performpower regulation and management have become examples ofthe fastest growing segments of the electronics industry.

The typical PMOS LDO topologies are presented in SectionII. In Section III, a new LDO approach is presented andthe respective results are presented in section in Section IV.Finally, Section V, presents the conclusions of the work andfurther research possibilities are discussed.

II. CONVENTIONAL PMOS LDOS REGULATORS

Most of the convencional LDOs are PMOS LDOs. TheLDO regulator uses a single transistor in common-sourceconfiguration operating in the saturation region. The topologyof this kind of LDOs is shown in Figure 1 and referred in thereferences .

This topology consists of a PMOS transistor, controlled byan error amplifier which compares the voltage reference withthe output voltage sensed through the feedback resistors R1

Fig. 1. PMOS voltage regulator topology.

and R2. The error signal controls the gate of the pass transistorand forms the negative feedback loop.

The most important challenge for this circuit is to keepthe pass transistor always in the saturation region, in orderto operate properly. Maintaining the pass transistor in thesaturation region becomes difficult with the topology presentedin Figure 1 due to significant variations of the load. Thesevariations can lead the LDO to beacome unstable. In order tominimize this problem a large internal, or external, capacitorin the output node is used, as shown in Figure 2.

Fig. 2. PMOS voltage regulator topology with output capacitor.

The problem of using an output capacitor is the silicon areaused by this capacitor. In order to reduce the capacitance andconsequently the area of the device, several feedback loopswere studied to improve the performance of the LDO and

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reduce the output capacitor.

III. THE NEW LDO APPROACH

A. The Core circuit

The core of the new LDO is presented in this secction.Figure 3 shows the basic topology. In this coarse representa-

Fig. 3. The core of the new PMOS LDO topology.

tion, the circuit was simplified in order to explain the basicfunctionality. Alike the typical LDO topology there is a passiveelement: the pass transistor (M87 of Figure 3). This transistoroperates in the saturation region and the current that flowsthrough this transistor can be approximated by equation 1.

iD =12W

LµCox(Vt − vSG)2 (1)

The current is distributed between the load (if any load isconnected to the LDO) and to transistor MP2, as shown inFigure 3. The transistor MP2, like the M87, operates in thesaturation region. The gate of MP2 is set to the referencevoltage provided by a Band-gap (the voltage value that theLDO regulates). MP2 transistor operates like a comparatorbecause the drain current that flows through this transistor(I1) has dependency with vSG (vSG = vOUT − Vref1). Thetransistor MP78 acts like current source and an active load,providing the current I2. Current source IC2 has a static valueof current It which is the result of sum I1 with I2.After the presentation of each circuit element, the basic voltageregulation principles used by the LDO will be explained. Like

in the conventional LDO, the comparator closes the feedbackloop. As referred earlier, MP2 regulates the amount of current,I1 depending on the load variations. This current amountforced by MP2 will be summed to I2 and therefore IC2 toI2 = It − I1. Theoretically it is easy to show the vOUTindependence of RL. In equation 2 vOUT depends only onconstants and on I1.

I1 = kµp2(VOUT − Vref1 − Vt)2 (2)

However, is the difference between two constant currents(I1 = I2 − It). Therefore, Vout is defined by equation 3.

I2 − It = kµp2(Vout − Vref1 − Vt)2 (3)

For load variations the RL MP78 acts like an active loadwhich means that the gate voltage of the pass transistor vsgis controlled by the variations of current I2. Therefore, thecurrent that flows through the pass transistor is controlled byI2 which in turn is controlled by I1 (It has a constant valuewhich allows I1 to control I2).Now taking the example of a load change, from full load tothe absence of load, this situation will produce a vout increase,consequently I1 will increase due to vSG = vOUT − VREF1

of MP2. When I1 increases, I2 will decrease, making thevoltage in the gate (vG) of pass transistor higher (this isbecause, M78 acts like an active load). If vG becomes higher,the vSG of the pass transistor becomes lower and the draincurrent also becomes lower. The current that flows throughthe pass transistor regulates the current I1 to a lower valueand consequently lowering the output voltage as required.Now the opposite situation: from no load to a situation offull load. This change of load will produce a Vout decrease,consequently, I1 will decrease due to thr vSG = vOUT −VREF1 of MP2. So if I1 decreases, I2 will increase makingthe voltage in the gate (vG) of the pass transistor lower (onceagain M78 acts like an active load). If vG becomes lower thevSG of the pass transistor becomes higher making the currentthat flows through it higher, regulating the current I1 to ahigher value and consequently, increasing the output voltageas required.

B. Improving the LDO

In the previous section the concept of the new topology waspresented. In this section, new components are added to thebasic circuit, to improve it and to allow the integrated imple-mentation. In Figure 4 the changes are presented, introducingthree new elements: a cascode transistor M127, transistor MP5and capacitor Cout.

The cascode transistor maintains the voltage in the gate ofthe pass transistor at a level which keeps, the pass transistor,always in the saturation region. MP5 is needed so that theVout dependency on Vref becomes independent of the Vt ofthe PMOS transistors. Cout is used to keep vOUT steady forhigh frequency load variations. If the load conected to LDOincreas, Cout discharges to the load in order to keep vOUTsteady.

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Fig. 4. The improved PMOS LDO topology.

C. Shunt regulation

In order to improve the transient response of the LDOduring load variations, it is proposed a new congurationof shunt regulation. As shown in Figure 5 shunt transistor,M109, is driven by the sense transistor, M110, if there is apeak of current M108 is the active load of M110. M106 and107 just act as a voltage divider to bias the gate of M110.The current mirror M73, M74, M70 and M102, controlled byM99, allow to reduce the sensibility of this shunt regulationfor higher load currents. IfvSG of M87 and M99 increases dueto a larger current consumption in the load M108 will reducethe vGS of M109 reducing the shunt regulation inuence invOUT . When needed, the source of M110 is pulled up byvOUT , vGS of M109 increases and M109 drains the excess ofcharge, reaching the voltage and current stability faster. Thisoccurs when the load that is connected to the LDO is suddenlydisconnected, creating a peak of current as illustrated in Figure6. Analyzing this gure we can see on the top of the loadvariation between 1mA and 5 A, with rise an fall time of2.5 s. The transient analysis in the middle presents the LDOoutput voltage without the shunt circuit. The bottom transientanalysis shows the LDO output voltage with the shunt circuitactive. Comparing the simulations, signicant differences canbe noticed such as the reduction of the peak levels observedwith the shunt circuit. Additionally, the shunt circuit removesthe oscillation that occurs after load variations, meaning thatthe LDO gains phase margin increases. with the shunt circuitthe LDO becomes more stable.

D. Faster feedback loop

This additional feedback loop makes the response of theLDO faster.The topology of this loop is shown in Figure 7.The loop controls the current that ows through the currentmirror (M130, M80, M120 and M100) which providesI 2 thecurrent in the active load (current mirror composed by M77and M78). The work of this sub-circuit is quiet simple. Thisfast path makes the currentI 2 lower or higher according to

Fig. 5. Shunt circuit.

Fig. 6. Example of the shunt circuit functionality.

the current peaks inherent to load variations, controlling thepass transistor, M87, before the response of the main loop.

E. Amplifying the Reference Voltage

The voltage provided by the bandgap (Vref ) has half thevalue of the output voltage (Vout ). Therefore, the referencevoltage needs to be amplied. As shown in Figure 8, atransconductance amplier is used for this purpose.

The amplication topology used is the non-inverting, asshown in Figure 9.

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Fig. 10. LDO block diagram

which compounds the LDO (F1 = F2 = 4). The third termcorresponds to the pass transistor transconductance multipliedby it’s gate resistance Rx which is given by the equation 7.The last of the DC gain is the output resistance which is givenby equation 8.

ADC ≈14gmdifpair×(F1 +F2)×gmpassRx×Rout = 71dB

(6)

Rx = ro78// (gm127 × ro127 × ro95) (7)

Rout = ro87//(ro49 + ro50)//RL (8)

As previously referred one of the concerns when designingthe LDO is the improvement of the PSRR analysis. This is thereason why the sub circuits are supplied by the output voltageVout. However, this solution introduces feedback produced bythe ro of the current mirrors that compound the projectedfeedback loops (the cut "AC" block shown in doesn’t coverthis feedbacks). This effect is illustrated in Figure 11. Figure10 interrupts the AC feedback of the main loop, keeping theDC feedback. The open loop analysis was performed addingthis cut AC instance and simulating the vout/vin ratio.

Fig. 11. Parasitic feedbacks.

The DC gain is not independent of the LDO operation state(full load and no load) because of the RL dependency in Rout.

Fig. 12. AC open loop analysis with full load.

Fig. 13. AC open loop analysis without load.

Analyzing the simulated results shown in figures 12 and 13,we can conclude that the Rout term is not the dominant term,since the DC gains are very similar. However, it still can beseen that the no load simulation has a DC gain which is a littlehigher than the full load simulation, once the term Rout ishigher in the no load situation. In this two figures we also cansee that the phase margin in both cases is around 80 degrees,which means that the circuit is very stable in both situations.This is new in this kind of circuits because of the dependencyof the second pole with the load, comparing with the typicalLDOs.

Using a tool of the simulator ( .PZ ) we can extract thelocation of the poles and zeros. Table I shows the poles andthe zeros which are comprehended in the frequency range ofthe phase margin.

TABLE ISIMULATED POLES AND ZEROS LOCATION

No Load Full Loadfp1 6.3 Hz 7.4 Hzfp2 5.5 kHz 58.8 kHz

• First PoleThe first pole is also called the dominant pole. This poleis produced by the Miller effect associated to the CGD of

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the pass transistor. Equation 9 gives the theoretical valuefor the frequency.

fp1 =1

2πRxApassCgdpass

(9)

Based of equation 9, its easy to see that there is nosignificant dependency on the load. Only the changedimposed by the gain (Apass) The terms that compoundthe pole location are:

– Rx, the resistance in the gate of the pass transistorwhich is given by equation 7;

– Apass the gain of the pass transistor which is givenby the equation 10;

– Cgdpass the capacitance of the pass transistor be-tween the gate and the drain.

Apass ≈ gm87 × (ro87//RL) (10)

• Second PoleThis pole is introduced by the output capacitor and theload resistance. The location of this pole is given by theequation 11.

fp2 =1

2πCout(ropass//Rload)(11)

B. Transient Analysis

This Section describes the behavior of the capacitor lessLDO voltage regulator, during load variations. These varia-tions are simulated with a current source in the output ofthe LDO, between 5µA and 1mA (no load situation and fullload situation respectively), with a rise time and a fall timeof 2.5µs. This analysis is much more reliable then the ACanalysis, since in this simulation there is no need to interruptany feedback.The simulation described in this section was made for all the64 corners, as it can be seen in Figure 14.

The result achieved is very good because the overshootpeaks are small and the time response of the circuit is fast,even in the worst corners. It can also be seen that after thetransient occurs, the regulator offset for all corners, in bothsituations, is less than 10 mV (≈ 0.65%)

1) Power up and down Analysis: In this sub-section thepower up and power down transient behavior is presented.Figure 15 is shown the enable signal switching from a lowerlevel to a higher level and the LDO output voltage respondingto this variation.

Looking carefully to Figure 15, it can be seen that thepower up occurs between 10µs and 15µs for all the simulatedcorners. This means that, even in the worst case, the LDOis turned on very quickly. Figure 16 illustrates the oppositechange. The LDO has a fast shutdown response.Looking at Figure 17 we realize that in standby the LDOconsumption is near 0A and when it is turn on its consumptionis around 96µA.

Fig. 14. Transient analysis in all 64 corners.

Fig. 15. Power up analysis.

C. Steady-state Parameters

The steady state parameters define the capacitor-lessLDOs static state conditions. There were two importantcharacteristics that defined the steady-state LDO parameters,the line regulation and the load regulation. The line regulationwas simulated for for full load condition, 1mA output current(because most of the time the regulator is working in a fullload condition). The input voltage was swept from 1.7 Vto 3.7 V with a step of 1 mV and the correspondent outputvoltage was measured. The results are shown in Figure 18.

For the load regulation analysis, the input voltage was fixed

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Fig. 16. Power down analysis.

Fig. 17. Consumption analysis.

in 2.65 V, and the output current was swept from 0 mA to 1.1mA with a sept of 0.01 mA. Figure 19 shows the simulationresults.

The output voltage deflects from the nominal 1.5 V output.However in both cases the deflection is inferior to 3 mV forthe worst corner. Which means that the regulator has a goodbehavior for the steady state conditions.

D. PSRR Analysis

This section presents the PSRR analysis. This analysisevaluates the impact of the supply variations impact on theoutput voltage. One of the concerns on the LDO design is tohave a low PSRR. In this case the LDO will be integratedwith a DC-DC converter that operates at 2MHz. In order toimprove the PSRR several filters and pole/zeros were addedand some parts of teh circuti were supplied with the outputvoltage. Figures 20 and 21 show the PSRR analysis withoutand with load, respectively. Analyzing these two figures, wesee that at 2MHz we have PSRR less or equal than -20dB foralmost all of the simulated corners.

E. Monte Carlo Simulations

Monte Carlo analysis was performed to study the capacitorless LDO sensitivity to process variation such as carrier

Fig. 18. Line regulation with full load.

Fig. 19. Load regulation.

mobility and MOSFET threshold voltage. The Monte Carloanalysis was performed in the DC steady-state output voltage(with sampling of M=100, in order to get reliable results). Thesimulation was performed in the two extreme conditions: withno load and with full load. In order to observe the offset ofthe regulator due to the process variations. These results areshown in Figure 22 and Figure 23 respectively.

The results show that the two simulations are very similar.Looking more carefully to the results it can be seen that themaximum offset is 30 mV and only in few cases (in bothfigures). A great part of the cases are in the desired voltageor in it’s neighborhood. These results mean, not only that theDC steady-state of the regulator is not affected by the load,but also shows the robustness of the regulator to the processvariations.

V. CONCLUSIONS

A novel LDO topology has been presented that allows toremove the large external capacitor found in typical LDOs.The new capacitor less LDO presents good results in all kindsof analysis. The good results presented are not only resultof the combination of fast feedback loops but also due tothe regulator’s core. This core combines a transconductanceamplifier, acting like an error amplifier, with current amplifiers

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Fig. 20. PSRR analysis without load.

Fig. 21. PSRR analysis with load.

that drive an active load connected to the gate of the passdevice. The shunt regulation was also introduced in order toimprove the transient response and to minimize the outputcapacitor. Another very important concern in the regulatordesign was the PSRR. The architecture also prove to be robustto process variations (by Monte Carlo simulations).The proposed capacitor less LDO voltage regulator was de-signed in SMIC 0.13 µm, CMOS technology in Chipidear.The final characteristics of the designed LDO are presented inTable II.

TABLE IIFINAL RESULTS

Symbol Parameter Min Typ Max UnitVout Line Regulation 1.547 1.55 1.5495 VVout Load Regulation 1.547 1.55 1.551 VVout Monte Carlo Simulation 1.53 1.55 1.58 VItot Current Consumption - - 96 µAItot Power down - - 168.51 pAPM Phase Margin 83 - 83 deg

PSRR PSRR (at 2 Mhz with load) -29 -25 -18 dbCout Output Capacitor - 30 - pFESR Equivalent Series resistor - 1.55 - kΩArea Total core area 0.025 mm2

The whole development process provided an excellent view

Fig. 22. Process variation on DC steady-state output voltage for Iout =0mA.

Fig. 23. Process variation on DC steady-state output voltage for Iout =1mA.

of microelectronic power circuits design and how this designtakes place in the industrial world.

A. Future Work

Even though this capacitor less LDO design has met thespecifications that were defined for the inclusion in a mobilePMU, there is also a scope for improvement. Other feedbackloops need to be experimented.The major concerns in this type of circuits are: fast response,consumption, PSRR and area. These are relevant aspects, thatthe future work should focus in order to research a bettertradeoff with new technologies.

REFERENCES

[1] Vishal Gupta, Gabriel A. Ricón-Mora, and Prasum Raha, Analysis anddesign of monolithic, high psr, linear regulators fo soc aplications, IEEE00 (2004), 311–315.

[2] Ashis Maity, Raghavendra R. G., and Pradip Mandal, On-chip voltageregulator with improved transient response, 18th International Conferenceon VLSI Design held jointly with 4th International Conference onEmbedded Systems Design (VLSID?05) (2005), 1–6.

[3] Robert Jon Milliken, A capacitor-less low drop-out voltage regulator withfast transient response, December 2005.

[4] Behzad Razavi, Design of analog cmos integrated circuits, 1st ed.,McGraw-Hill Science/Engineering/Math, New York, NY, USA, 2000.

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[5] Adel S. Sedra and Kenneth C. Smith, Microelectronic circuits, 2nd ed.,5th ed., Holt, Rinehart & Winston, Austin, TX, USA, 1987.

[6] TeTsuo, Kazuhia Sunaga, Hiroshi Sakuraba, and Fujio Masuoka, Anon-chip 96.5% current efficiency cmos linear regulator using a flexiblecontrol technique of output current, IEEE JOURNAL OF SOLID-STATECIRCUITS 36 (2001), 34–39.