A Low Power 900MHz Superheterodyne

Compressive Sensing Receiver for Sparse

Frequency Signal Detection

Hamid Nejati and Mahmood Barangi

EECS department, University of Michigan, Ann Arbor

{hnejati,barangi}@umich.edu

Abstract—In this report, a full implementation of a com-pressive sensing receiver is introduced. The receiver is basedon the superheterodyne receiver configuration. The system-level modeling and design of this structure as well as circuitlevel design and layout implementation of this structure aredemonstrated. The narrowband receiver is designed for 900MHzfrequency and can detect sparse signals in the frequency domainin the band of interest. In the superheterodyne topology, the localoscillator replaced with a linear feedback shift register (LFSR),the application of the mixer changes to multiplier, and finally thelow pass filter, ideally an integrator, can do the summation.

I. INTRODUCTION

compressive sensing has been attracted a lot of interest

recently due to its ease of implementation and the rapid devel-

opment of signal reconstruction algorithms. One of the most

important advantages of the compressive sensing technique is

that it can directly extract information from the input desired

signal. In most analog and digital systems, we are dealing

with a huge set of redundant data that can be compressed

with signal processing methods without removing significant

information [1]. Compressive sensing has been used in a lot

of applications including: image processing, data processing,

and object classifications. In the analog design world, dif-

ferent implementations of the compressive sensing algorithm

has been introduced such as random demodulation, random

sampling, and random filtering [2]. Among these systems,

random demodulation technique has shown a great potential

for future communication systems [3]. This configuration can

be utilized in the transmitter design such as sensor nodes in

a wireless sensor network or it can be used in the receiver

architecture to reduce the complexity and power consumption

of the receiver. In the receiver design, which is the focus of

this report, this configuration can reduce the burden of the

analog to digital converters (ADCs) as well as reducing the

overall power consumption of the system.

Compressive sensing (CS) is a compression technique that

can be utilized for sparse signals recovery. A sparse signal

can be defined as any signal that can be expressed by a

small number of components. As an example a sinusoidal

signal is sparse in Fourier domain. The CS algorithm relies

on the multiplication of the input sparse signal by a random

matrix known as random measurement matrix. The number

of measurements should be less than the whole number of

Mixer

a)

LNA

Mixer

Amp. ∫ ADCData

Recovery∫

LFSR Reset

Data x ∑b)

Data

Recoveryx ∑b)

Φ

Fig. 1. System level configuration of (a) superheterodyne compressivesensing receiver and (b) mathematic modeling of the compressive sensingbased receivers topology.

data points (Nyquist rate). Adding the measurement data

can generate a single output data for each measurement. By

sending the single data for each measurement, CS algorithm

can recover the original data.

A superheterodyne receiver can be interpreted as a random

demodulation system by replacing the multiplication by mix-

ing, local oscillator with a random number generator, and the

summation operator by integrator/low pass filter.

The overall system block diagram is shown in Fig. 1 (a).

The input RF signal incident to the antenna is the input of the

system. This signal is amplified with a narrowband low noise

amplifier (LNA). The amplified signal is multiplied (mixed)

with a random number string. The mixed signal passes through

a low pass filter/integrator and the output data is digitally

sampled with a low rate ADC. The sampled data is processed

in the processing unit. In our implementation, we utilized a

Matlab program to recover the input signal. This stage can also

be implemented on a DSP board to make a real-time analysis

and recovery of the data.

In the following section, an overview of the whole system

is explained and the system level design procedure is fully

described. Then, a detailed design, modeling, and imple-

mentation of each block are separately demonstrated. In the

following, the system level results as well as the circuit level

results are illustrated. finally, we conclude the report.

II. SYSTEM LEVEL DESIGN AND IMPLEMENTATION OF

COMPRESSIVE SENSING RECEIVER

We developed an Analog to Information Converter (AIC) [2]

using Compressive Sensing (CS) [3] to decrease the sampling

rate of the ADC leading to power reduction of the whole

system. High speed applications demand flash ADCs, which

consume huge power and require special cooling process.

In this section, we plan to develop behavioral models for

the whole system in Matlab/Simulink by considering the non-

idealities of each building block. We also developed a link

between Matlab and Cadence based on the ocean script to

automatically validate the accuracy of our models compared

to the transistor level design. The overall system is shown

in Fig. 1 (a) and (b). As shown in Fig. 1 (a), the sys-

tem consists of a superheterodyne receiver topology. In this

topology, The input signal enters an LNA and after desired

amplification multiplies with a bipolar random number streams

generated by a pseudo-random number generator. This pseudo-

random number generator is based on linear feedback shift

register (LFSR). The LFSR consists of ten D-flip flops and

two XOR gates. The input 2GHz clock signal is generatedwith the ring oscillator. The minimum clock cycle should

satisfies the Nyquist condition. Since the frequency of the

input signal is 900MHz, the Nyquist condition dictates thatthe system must have the clock frequency more than 1.8GHz.In our setup, we set the input clock frequency to 2GHz.By integrating the multiplication of the random bit stream

with the amplified input signal, we can extract the data

required for compressive sensing signal recovery algorithm.

The compressive sensing recovery algorithm is based on the

recovery of a frequency sparse signal. The one tone signal

is sparse in frequency domain/basis [1]. The Fourier basis is

the matrix ψj = n−1/2ei2πjt/n, where ψj is the jth column

of the basis matrix, n is the total number of points, and t isthe sampling time, respectively. This matrix is complex and

is not appropriate for practical real signal applications. By

utilizing the Euler transformation and splitting the exponential

into periodic harmonic sine and cosine functions and filling

the basis matrix, we can have a twice as large matrix with

all the required information. For reconstruction algorithm, we

utilized an orthogonal matching pursuit algorithm [4] to find

the signal out of the measurement data. The total number of

measurements is less than the whole number of data by a factor

of 8.

III. CIRCUIT LEVEL DESIGN AND ANALYSIS OF THE

WHOLE SYSTEM

In this section, we discribe the overall receiver front end

circuits in more details.

A. Linear Feedback Shift Register and Clock Generator

The linear shift register (LFSR) circuit consists of ten reg-

isters (D-filpflops) as well as two XOR gates. the D-flipflops

are implemented by C2MOS register structure. The LFSRstructure, as shown in Fig. 2, can generate a pseudo random

bit stream. For the recovery purposes, we require a bipolar

D Q D Q D Q D Q D Q

a)

Clk Clk Clk Clk Clk

D Q

Clk

D Q

Clk

D Q

Clk

D Q

Clk

DQ

ClkClk Clk Clk Clk Clk

b)

Q

ClkClk

D Q

ClkClk

D

Fig. 2. (a) The block diagram of the LFSR used to generated pseudorandombit stream. (b) The register implementation by a C2 MOS topology.

random bit stream. The passive mixer can provide the bipolar

random multiplication of bit stream into the RF input signal.

The random bit generator can generate bit streams as long as

1024 clock cycles. We call this length of the clock cycles a

frame. By initializing the D-flip flops, the desired random bit

pattern can be generated. The LFSR requires a clock signal

that can be generated on chip with a series combination of

eleven invertors. The clock signal passes through three clock

buffers. The overall power consumption of this stage is less

than 600µW .

B. Low Noise Amplifier and Buffer

The first stage after antenna should provide high gain and

low noise figure for a guaranteed high performance receiver

system. We utilized an inductively degenerated low noise

amplifier, as shown in Fig. 3. In order to provide impedance

matching between low noise amplifier and mixer, we are

utilizing an RF buffer, as shown in Fig. 4. This buffer is

a common drain structure loaded with an LC tank. The

equivelent circuit of the output port is a parallel RLC tank.

The resistor in this setup is equal to 1

gm

. The step by step

design procedure is as follows, we should appropriately size

the transistor in a way that its 1

gm

= Rs. Then by setting

the output inductor and capacitor in resonance at our desired

frequency 900MHz, the narrowband matching is possible.This buffer can also provide high isolation. The isolation is an

important factor in this design, because the random number

oscilator is generating high power bit stream. The isolation of

the mixer by itself is not high enough to suppress the reflected

signal. By introducing the cascose stage and the buffer the

required isolation can be achieved to satisfy low reflection of

the signal back to the antenna.

C. Mixer/Multiplier

In order to implement the bipolar multiplication of the LFSR

bit streams into the input amplified RF signal, we are utilizing

VDD C

D

LVB

LD

RB

M2

CIN

M2

LCIN

M1

LG

RS

LCP

Port0

LS

CP

Fig. 3. Inductively degenerated cascode amplifier utilized for high gain andlow noise figure.

VVB V

DD

RB

CIN

M1

M1

LS C

SCdecL

S CS

Cdec

Fig. 4. Buffer stage to decouple/isolate the LNA from the Mixer and LFSR.

a passive mixer. This mixer can provide a multiplication of

±1, set by the oscilator signal, into the RF signal, which is

the exact functionality that we require. The ±1 multiplication

is provided by commutatively switching the transistors in a

bridge like structure, as shown in Fig. 5.

D. Integrator

In order to provide the integration, we are using a high

bandwidth amplifier as well as a well known capacitor and

resistor structure to implement the integration. The amplifier

design is shown in Fig. 6. This integrator or in a better sense

low pass filter can implement the summation operator in the

block diagram, shown in Fig. 1 (b). We are also using an

RC low pass filter after the integrator to make low pass data

required for CS.

RS

VLFSR

+VLFSR

-

RS

VV

VLFSR

+ VLFSR

-

Vout

VRF

Fig. 5. Passive mixer design for multiplication purpose.

Fig. 6. Wide bandwidth amplifier utilized to implement the integration.

E. Analog to Digital Converter

Flash ADCs are commonly utilized for high performance

systems. Flash ADCs are power hungary and implementing a

low power structure is highly required [5]. We implemented

a low power 2.6mW , high speed 200MSps flash ADC tomaintain the low power feature of the system. The encoder

including ”thermometer to 1 in N” converter and ROM are

designed customly instead of synthesis tools to reduce the area

and power consumption. The latched structure is chosen for

the comparators to reduce the static power consumption, which

is more than 80 percent of the total power consumption of the

flash ADC.

IV. SIMULATION RESULTS

The overall performance of the receiver is measured by

block by block performance evaluation. The LNA performance

metrics are S-parameters, noise figure, and linearity. The S-

parameters as well as the noise figure are shown in Fig. 8.

Vin

--

+

-

+ROM

Encoder

64 6+

ROMEncoder

-

+

-

+

Fig. 7. 6-bit Flash analog-to-digital converter topology.

Am

pli

tud

e (

dB

)A

mp

litu

de

(d

B)

S11

NF

S22

S12

S21S21

Frequency (GHz)

Fig. 8. The scattering parameters including: input and output matching, gainand isolation as well as the noise figure of the LNA.

The noise figure is as low as 1.2dB, gain is as high as 23dB,input and output matching is as low as −21dB and −14dB,respectively. The isolation is as low as −58dB. The stabilityof the LNA is also checked and the amplifier is stable. The

input refered 1−dB compression point andthird order interceptpoint are shown in Fig. 9 (a) and (b), respectively.

The integrator response and the multiplier noise are shown

in Fig. 10 (a) and (b), respectively.

The SNDR of the ADC at low frequencies and the frequency

of operation (200MSps) are 36.98 and 34.2 respectively,leading to the ENOB of 5.87 and 5.4. The figure of merit of theADC at the frequency of operation is 308fJ/conversionstep.The SNDR, SFDR, ENOB, and THD are shown in Fig. 11 (a),

(b), and (c), respectively.

The response of the multiplication of the LFSR random

bit stream into the amplified RF input signal as well as the

generated clock signal is shown in Fig. 12

a)

Ou

tpu

t p

ow

er

(dB

m)

Ou

tpu

t p

ow

er

(

Input power (dBm)

b)b)

Ou

tpu

t p

ow

er

(dB

m)

Ou

tpu

t p

ow

er

(

Input power (dBm)

Fig. 9. (a) input refered 1-dB compression point and (b) input refered thirdorder intercept point of the LNA.

a)

Am

pli

tud

e (

dB

)A

mp

litu

de

(d

B)

b)

Frequency (GHz)

b)

Am

pli

tud

e (

dB

)A

mp

litu

de

(d

B)

Frequency (GHz)

Fig. 10. (a) Integrator frequency response. (b) The passive mixer noise figure.

(a) (b) (c)

Fig. 11. Flash ADC specifications including: (a) Signal-to-Noise + Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR), (b) EffectiveNumber of Bits (ENOB), and (c) Total Harmonic Distortion (THD).

Amplified RF signalAmplified RF signal

Multiplied signal

Vo

lta

ge

(m

V)

Multiplied signal

Vo

lta

ge

(m

V)

Clock

LFSR bit stream

Time (ns)

Fig. 12. The overall response of the clock, LFSR, amplified RF signal, andthe multiplication of the random bit stream into the amplified RF signal.

The recovery algorithm could recover a single tone sinu-

soidal wave and the recovered signal is shown in Fig. 13 (a)

and (b).

The overall layout of the receiver is shown in Fig. 14.

The overall specification of the system is listed in table I.

V. CONCLUSION

In this report, we investigate a RF receiver frontend, which

is operating optimized for the compressive sensing applica-

tions. CS technique can be utilized for recovery of sparse

frequency signals. We demonstrated a system level as well as

a detailed circuit level design, modeling, and implementation

of the whole receiver system.

VI. ACKNOWLEDGEMENT

We wish to thank Professor David Wentzloff for his advice

and thoughtful suggestions.

0.4

0.5a)

0.2

0.3

Amplitude

0 2 4 6 8 10 12

8

0

0.1

Frequency (Hz)x 10

8Frequency (Hz)

0.5b)

0.3

0.4

0.5

Amplitude

0.1

0.2

0.3

Amplitude

0 2 4 6 8 10 12

x 108

0

Frequency (Hz)

Fig. 13. The frequency spectrum of (a) a single tone sine wave and (b) therecovered single tone sine wave.

Clock & LFSR

Fla

sh A

DCLNA

Fla

sh A

DCLNA

Fla

sh A

DC

Multiplier

Integrator

Buffer

Fig. 14. The layout of the whole system.

TABLE I

THE OVERALL SYSTAM SPECIFICATIONS

Overall system Specification @ 900MHz

LNA + Buffer S11 -21dBS21 23dBS12 -58dBS22 -14dBPower 4.95mWNF 1.2dB1dB compression -12.2dBmIIP3 -3.9dBm

Mixer NF 9.67dB

LFSR + clock Power 600µWclock 2GHz

Integrator Power 1.5mW3-dB cutoff 12MHz

Flash ADC Power 2.6mWSampling 200MSpsSNDR 36.98dBENOB 5.87FOM 308fJ/conversion

REFERENCES

[1] E. Candes and M. Wakin, “An introduction to compressive sampling,”IEEE Signal Processing Magazine, vol. 25, no. 2, pp. 21–30, 2008.

[2] R. Baranuik, “Compressive sensing,” IEEE Signal Processing Magazine,vol. 24, no. 2, pp. 118–121, 2007.

[3] T. Ragheb, J. Laska, H. Nejati, S. Kirolos, R. Baraniuk, and Y. Massoud,“A prototype hardware for random demodulation based compressiveanalog-to-digital conversion,” IEEE Midwest, pp. 37–40, 2008.

[4] J. TROPP and A. GILBERT, “Signal recovery from random measure-ments via orthogonal matching pursuit,” IEEE Transactions on Informa-tion Theory, pp. 1–9, 2007.

[5] K. Yoon, S. Park, and W. Kim, “A 6b 500msample/s cmos flash adcwith a background interpolated auto-zeroing technique,” IEEE JSSC, pp.326–327, 1999.