192 IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 2, FEBRUARY 2008

A High-Stress Liner Comprising Diamond-LikeCarbon (DLC) for Strained p-Channel MOSFET

Kian-Ming Tan, Student Member, IEEE, Ming Zhu, Wei-Wei Fang, Mingchu Yang,Tsung-Yang Liow, Student Member, IEEE, Rinus T. P. Lee, Student Member, IEEE, Keat Mun Hoe,

Chih-Hang Tung, Senior Member, IEEE, Narayanan Balasubramanian, Member, IEEE,Ganesh S. Samudra, Member, IEEE, and Yee-Chia Yeo, Member, IEEE

Abstract—We report the integration of a new liner stressor com-prising diamond-like carbon (DLC) film over a p-channel tran-sistor. A high compressive stress of 6.5 GPa was achieved in ahigh-stress film with a thickness of 27 nm. A 74% enhancement indrive current was observed for the strained device with DLC lineras compared to a control device without DLC liner. Due to its muchhigher intrinsic stress value compared to conventional SiN films,a thinner DLC layer can induce comparable amount of stress inthe transistor channel compared to a thicker SiN. The DLC mate-rial is a potential next-generation high-stress and low-permittivityliner stressor material suitable for application in transistors withaggressively scaled pitch dimensions.

Index Terms—Contact etch stop layer (CESL), diamond-likecarbon (DLC), enhancement, pitch, stress, strain.

I. INTRODUCTION

S TRAIN engineering techniques are widely studied andadopted to improve the carrier mobility and performance of

CMOS devices [1]–[3]. In particular, a high-stress SiN contactetch-stop layer (CESL) is a cost-effective solution that can beeasily implemented in a CMOS process flow. However, withthe scaling down of the gate pitch to increase device packingdensity, the effective stress in the channel decreases when thegap between the gate electrodes is completely filled by the SiNCESL, compromising device performance [4]. Fig. 1 shows thatthe reduction of gate pitch leads to a decline in the magnitudeof longitudinal stress Sxx in the channel region of a transistorhaving compressive stress SiN CESL. Increasing the thicknessof the SiN CESL does not necessarily lead to a higher chan-nel stress. In fact, a thinner SiN CESL with a higher intrinsicstress can achieve higher channel stress even at a reduced pitch.Consequently, CESL or liners with higher intrinsic stress areneeded to maintain or even provide better device performance.

Manuscript received September 5, 2007; revised November 1, 2007. Thiswork was supported in part by the Nanoelectronics Research Program, Agencyfor Science, Technology, and Research, Singapore (A∗STAR) under a ResearchGrant. The review of this letter was arranged by Editor K. De Meyer.

K.-M. Tan, M. Zhu, W.-W. Fang, T.-Y. Liow, R. T. P. Lee, G. S. Samudra, andY.-C. Yeo are with the Silicon Nano Device Laboratory (SNDL), Department ofElectrical and Computer Engineering, National University of Singapore, 119260Singapore, Singapore (e-mail: g0402599@nus.edu.sg; nnizm@nus.edu.sg;g0600189@nus.edu.sg; g0301490@nus.edu.sg; g0403726@nus.edu.sg;eleshanr@nus.edu.sg; yeo@ieee.org).

M. Yang is with the Data Storage Institute, 117608 Singapore, Singapore(e-mail: yang_mingchu@dsi.a-star.edu.sg).

K. M. Hoe, C.-H. Tung, and N. Balasubramanian are with the Institute of Mi-croelectronics, 117685 Singapore, Singapore (e-mail: ivan6978@hotmail.com;chihhang@ime.a-star.edu.sg; nara@ime.a-star.edu.sg).

Digital Object Identifier 10.1109/LED.2007.914103

Fig. 1. (a) Schematic showing simulated longitudinal stress distribution forstacked MOSFET structures. Gate length LG and spacer width are 50 nm and35 nm, respectively. The stress Sxx from the center of a MOSFET is taken.(b) 50-nm-thick SiN CESL with an intrinsic stress of −2.0 GPa and 10-nm-thick SiN CESL with an intrinsic stress of −6.5 GPa were considered. Whenthe gate pitch is reduced, the stress Sxx in the center of the channel is reducedin magnitude. The onset of rapid decrease in channel stress at a small gate pitchis delayed for a liner stressor with smaller thickness and higher intrinsic stress.

Currently, the highest reported compressive stress in SiN liner isaround 2.4–3.5 GPa [5], [6], and increasing the stress to highervalues will be especially important for enabling aggressive pitchreduction in future technology generations.

Diamond-like carbon (DLC) film is known to exhibit a veryhigh intrinsic compressive stress of up to 10 GPa [7], [8], sig-nificantly higher than the stress attainable with the current SiNCESL. Moreover, the permittivity of the DLC is lower than thatof the SiN, which can be an additional advantage. The mate-rial properties of the DLC are related to its composition, and,in particular, its sp3 or sp2 content. A DLC film with a highersp3 content demonstrates a more diamond-like feature as op-posed to graphite-like properties. The DLC film is known forits hardness and chemical inertness, although it is still possibleto etch the DLC film using either pure O2 [9] or a mixture ofAr and O2 plasma [10], which are commonly used in plasmaetching. In this letter, we report the first demonstration of a DLCliner stressor for strained p-channel silicon-on-insulator (SOI)transistor with a stress value far exceeding the currently knowncompressive SiN CESL. The very thin liner demonstrated herefor drive current enhancement is applicable for aggressivelyscaled technology nodes employing a small gate pitch.

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TAN et al.: A HIGH-STRESS LINER COMPRISING DLC FOR STRAINED p-CHANNEL MOSFET 193

Fig. 2. (a) XPS of the DLC film showing the carbon 1 s core level. Thespectrum is fitted with curves having peaks corresponding to sp3 -hybridizedcarbon (α), sp2 -hybridized carbon (β), and C–O (γ) bonds. The inset shows aTEM image of a p-channel SOI MOSFET having a LG of 70 nm and a high-stress DLC liner.

II. DEVICE FABRICATION

Eight inches SOI substrates with 30-nm-thick Si were usedfor the fabrication of p-channel FETs (p-FETs). After thresholdvoltage Vt adjust implant, SiO2 gate dielectric (∼3 nm) wasthermally grown, followed by poly-Si gate deposition, gate pre-doping, and SiO2 hardmask formation. Gate definition was per-formed to achieve gate length (LG ) down to 70 nm. This wasfollowed by source/drain (S/D) extension implant, the forma-tion of SiN spacer on SiO2 liner, and deep S/D implantation. Niwith a thickness of 7 nm was then sputter-deposited for salicida-tion. To improve the adhesion of the DLC film, 10 nm SiO2wasdeposited on the strained device (with DLC). For a fair com-parison, this was also done on the control device. Photoresistwas patterned, and for the strained devices, 27 nm DLC wasdeposited using a filtered cathodic vacuum arc (FCVA) system.The FCVA system is capable of producing films with a very highintrinsic compressive stress [11]. The intrinsic stress of the DLCwas characterized separately on blanket wafers by the measure-ment of wafer curvature. Compressive stress as high as 6.5 GPawas obtained. The DLC at the contact regions were removed us-ing a resist liftoff process, followed by the removal of SiO2usingdilute HF. Control devices were also fabricated where the step ofdepositing DLC was skipped. Liftoff process and oxide removalwere also done for the control devices although there is no filmbeing deposited. Electrical characterization was performed bydirect probing on the NiSi source, drain, and gate pads.

III. RESULTS AND DISCUSSION

Fig. 2 shows the X-ray photoelectron spectra (XPS) of thecarbon 1s core level of our DLC film. The square symbols rep-resent the measured XPS data while the solid line is obtainedby fitting the spectrum using three deconvoluted curves (dashedlines). Peaks α and β correspond to sp3-hybridized carbon andsp2-hybridized carbon atoms, respectively [12]. A third peak γcorresponds to the C–O bonds formed on the surface of the DLCsample due to the exposure in air [12]. The DLC film employedhere for device integration has a relatively high sp3 content of∼60%, estimated by taking the ratio of the area under the curve

Fig. 3. (a) ID –VG characteristics of strained (with DLC) and control (with-out DLC) p-channel MOSFETs measured at a VD of −0.1 and −1.2 V showingsimilar subthreshold characteristics. The mean of the threshold voltage |Vth | isslightly smaller for the strained devices. (b) ID –VD characteristics are plottedfor gate overdrives (VG –Vt ) of 0 to −1.2 V in steps of −0.2 V. A 74% enhance-ment in the drive current was observed for the strained device over the controldevice.

due to sp3-hybridized C to the total area under the C 1s curve.The inset in Fig. 2 shows a transmission electron microscopy(TEM) image of a p-channel SOI transistor with a DLC linerstressor. The thickness of the DLC film is about 27 nm. Goodadhesion between the DLC film and the bottom oxide layer wasobserved. The DLC film in Fig. 2 is one of the thinnest linerstressors reported so far. Despite the small thickness, enhance-ment in device performance is achieved, made possible due to itsextremely high intrinsic stress. While this letter does not realizedensely packed devices with narrow pitch, it is expected that thethin liner stressors demonstrated here would be compatible withnarrow pitch dimensions. It should be noted that DLC confor-mality can be further improved in future process developmentefforts as a more conformal DLC coverage may improve thechannel stress.

Fig. 3(a) shows a plot of ID –VG characteristics of the con-trol p-channel transistor and the strained p-channel transistorwith DLC liner stressor. The gate length is 80 nm. Compa-rable control of short-channel effects (SCE) can be observed,with a drain-induced barrier lowering (DIBL) and subthresh-old swing of 0.123 V/V and 126 mV/dec, respectively. TheID –VD characteristics of both the devices are shown in Fig. 3(b).The strained device with DLC liner stressor demonstrates 74%enhancement in saturation drive current ID sat over the controldevice at a gate overdrive of −1.2 V, while the enhancement inlinear drive current ID lin is 92%. The magnitude of the drivecurrent can be further improved by using a thinner gate dielec-tric and silicon–germanium S/D stressors. Since the presence ofthe DLC liner is the only difference between these two devices,the extremely large increase in drive current is attributed to theeffective transfer of compressive stress from the DLC film tothe transistor channel, which leads to hole mobility enhance-ment, as indicated by the plot of Ioff –ID sat in Fig. 4(a). Deviceswith DLC are observed to exhibit an increased ID sat of 70%at a given Ioff of 1 × 10−7A/µm. This is further supported byFig. 4(b), which shows a plot of average drive current againstLG for both control and strained devices. It can be observed that

194 IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 2, FEBRUARY 2008

Fig. 4. (a) Plot of Ioff versus ID sat illustrating a 70% ID sat enhancement forstrained p-FETs over control p-FET at Ioff of 1 × 10−7 A/µm. Ioff and ID satare defined at (VG –Vth ) = 0.2 and −1.0 V, respectively. (b) Plot of averagedrive current ID sat (in symbols) for both control and strained devices againstLG . Up to eight devices were measured for each LG . The vertical bars showthe range of the measured ID sat values. Larger enhancement of drive currentis observed for LG smaller than 100 nm. This is attributed to the larger straineffect and higher hole mobility in strained devices with smaller LG .

the enhancement of drive current for the strained devices over thecontrol devices increases rapidly as LG is reduced below about100 nm. This is attributed to the induced compressive stress inthe channel, which becomes larger in magnitude [13], [14] whenLG decreases.

IV. CONCLUSION

A strained p-channel SOI transistor with a DLC liner stres-sor was realized. Due to the high intrinsic compressive stress(6.5 GPa) of the DLC film, a transistor with a 27-nm-thickDLC liner shows 74% enhancement in drive current over a con-trol device without a DLC liner. The new DLC material allowsthe realization of device performance enhancement even withvery small liner stressor thicknesses. This could be useful in fu-ture technology generations, where small gate pitch dimensionswould be adopted for achieving high device packing density.

ACKNOWLEDGMENT

K.-M. Tan acknowledges a Graduate Scholarship from theNational University of Singapore and Chartered Semiconduc-tor Manufacturing, Singapore. T.-Y. Liow acknowledges an A∗

STAR Graduate Scholarship Award.

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