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A Heuristic to Determine Low A Heuristic to Determine Low Leakage Sleep State Vectors Leakage Sleep State Vectors

for CMOS Combinational for CMOS Combinational CircuitsCircuits

University of Michigan, IBMICCAD ‘03

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OutlineOutline

Introduction Previous Related Work Terminology Heuristic Approach Results Conclusions

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IntroductionIntroduction

Bellow .13 process leakage dominates power consumption Leakage power = exp(-q*Vt / K*T)

Leakage reduction methods Dual Vt partition

MTCMOS State assignment

Gate leakage current depend on input state

Low Vt logic module

sleep Virtual ground

high Vt

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Works on State AssignmentWorks on State Assignment

When clock disable circuits in standby mode while power still turn on

Maintain the last state when active V.S. assign new low leakage state when sleep

FF/Latch

CombinationalLogic

gatedclock

PI PO

PPI

sleep

sleep

clockassign “0” :

sleep

clocksleep

assign “1” :

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Terminology - CC0,CC1Terminology - CC0,CC1

Controllability – provide guidance in ATPG Difficulty of setting a signal to 0 or 1 as CC0,CC1 Use functionality to get controllability and its list

P0

P1

P2

P3

P4

N5

N6

N7

N8

Z0

Z1

C0

C1

C2

C3

C4

C5

net CC0 CC1N5 2:(1X1XX) 1:

(0XXXX)

N6 2:(XX11X) 1:(XXX0X)

N7 2:(X1X0X) 1:(X0XXX)

N8 2:(XXX01) 1:(XXXX0)

Z0 2:(00XXX) 2:(1X1XX)

Z1 2:(X0XX0) 2:(XXX01)

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Terminology – BIC,WICTerminology – BIC,WIC

Best and worst input condition (BIC)(WIC) NAND gate for example:

(x,0) state makes minimum leakage of NAND2 (1,1) state makes maximum leakage of NAND2

best condition(x0)

minimum leakageworst condition(11)

max leakage

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Terminology – BIC,WICTerminology – BIC,WIC

Use CC list to build constraint listnet CC0 CC1

N5 2:(1X1XX) 1:(0XXXX)

N6 2:(XX11X) 1:(XXX0X)

N7 2:(X1X0X) 1:(X0XXX)

N8 2:(XXX01) 1:(XXXX0)

Z0 2:(00XXX) 2:(1X1XX)

Z1 2:(X0XX0) 2:(XXX01)

P0

P1

P2

P3

P4

N5

N6

N7

N8

Z0

Z1

C0

C1

C2

C3

C4

C5

cell BIC(X0) WIC(11)

C0 xx0xx 1x1xx

C1 xxx0x xx11x

C2 xx11x x1x0x

C3 xxxx0 xxx01

C4 x1x0x 00xxx

C5 xxx01 x0xx0

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Terminology – D,C cellsTerminology – D,C cells

Dominated and conflicting cells P’s min cost state forces Q into min cost state P’s min cost state violates Q’s min cost statecell BIC(X0) WIC(11)

C0 xx0xx 1x1xx

C1 xxx0x xx11x

C2 xx11x x1x0x

C3 xxxx0 xxx01

C4 x1x0x 00xxx

C5 xxx01 x0xx0

dominated cell conflicting cell

- C2

- C2

- C0,C1,C4,C5

- C5

C1 C2

C1 C2,C3

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Terminology – Cost FunctionTerminology – Cost Function

Cost function

NAND2 penalty for example CLP(Nand2) = 0.5*(L01+L11-L00-L10)

WLP(Nand2) = L11-0.5*(L00+L10)

Cost(Ci) = ∑ (CLP(conflicting cells(Ci))) –

∑(CLP(dominated cells (Ci))) – CLP(Ci)

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Heuristic Approach (1/2)Heuristic Approach (1/2)

ControllabilityList

ConstraintList

Conflicting &Dominated cell

All cells in selection list

Iteration Selected Cell

Input

Vector

Selection list

0 - xxxxx C0, C1, C2, C3, C4, C5

1 C4 x1x0x C0, C3, C5

2 C0 x100x C3, C5

3 C3 x1000 -

mini costViolated

List

C2

C51.rm dominated cells2.store conflicting cells3.update list

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Heuristic Approach (2/2)Heuristic Approach (2/2)

For any undefined input signal i Set i to 1 or 0 based on cost_input(i) Cost_input(i) = ∑(WLP( WIC satisfied cells )) Attempt to minimize the occurrence of WIC

Low leakage input state is ready

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ResultResult

Max 5% degradation

Max 10% better

Random(mA)

Heuristic(mA)

Diff%

RuntimeSaving(x)

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ConclusionConclusion

Use controllability and functional dependency to solve input vector search efficiently

The results based on good heuristic can be very close to exhaustive search