A heterogeneous time-triggered architecture on ahybrid system-on-a-chip platform

Haris IsakovicInstitute of Computer EngineeringVienna University of TechnologyEmail: haris@vmars.tuwien.ac.at

Radu GrosuInstitute of Computer EngineeringVienna University of TechnologyEmail: radu.grosu@tuwien.ac.at

Abstract—There is a huge discrepancy between off-the-shelf(COTS) hardware architectures and requirements for embeddedindustrial applications. Industrial systems are getting more com-plex by the day, and an interaction of highly diverse componentswithin these systems is unavoidable. An implementation of suchsystems on COTS hardware is challenging. Platforms basedon single-core CPUs is becoming limited, and use of multi-core architectures yields safety risks, and overall inefficiency.Tailored architectures provide adequate service but they lackflexibility and therefore their economic justification is limited.Emerging technologies i.e., hybrid system-on-chip combined withnovel architectural concepts are filling blind spots between COTSarchitectures and embedded industrial applications.The paperpresents the implementation of an MPSoC architecture on ahybrid system-on-a-chip platform. This architecture providesunique capabilities for embedded applications, in particular, thepossibility to host mixed-criticiality and cross-domain applica-tions.

I. INTRODUCTION

Industrial embedded applications (such as, automotive,aerospace, railway, internet-of-things, industrial automation)are implemented either on general purpose COTS hardwareor on dedicated hardware components. In the former caseversatility and accessibility are main goals. In the second casethe focus is on solving of a specific problem. The designand production of computer hardware architectures is mainlyinfluenced by requirements of general purpose computing.The first computer architectures were based on single-coreCPUs, which evolved to multi-core CPUs as the performanceand efficiency limits of single-core were reached. Due tolimitations of safety and reliability requirements the industrialapplications are mainly implemented on single-core architec-tures. On a single-core CPU tasks are usually divided in timeand the system software guarantees interference free opera-tion. However, most multi-core processors are designed withno special consideration towards isolation of different tasks(e.g., all applications share components in non-deterministicfashion). As a consequence, a sufficient guarantees cannot beprovided for safety critical systems without significant loss ofperformance, for example, disabling all cores, except for one.The industrial applications are getting more complex by theday and are forced to migrate multi-core architectures in orderto meet the performance requirements, and the fact that CPUmanufacturers are abandoning single-core architectures. Thewhole process is yielding serious challenges.

In this paper an overlaying hardware architecture is pre-sented which utilizes advances in the design of state-of-the-art

field programmable gate array (FPGA) devices technology. Itis an adaptation of the hardware architecture described in [1],which proposes an alternative approach to COTS multi-corearchitectures. The legacy architecture was implemented on aplatform with limited performance capabilities. In this papera new implementation of the architecture is described, imple-mented on a novel hardware platform Arria V ST SoC fromAltera [2]. It is implemented on a SoC chip that combines apowerful FPGA device with a hard-coded processor. It elevatesthe performance capabilities of the overlaying architectureand provides new options for the system designers. The newimplementation of the architecture uses a modular interface-based approach to build a heterogeneous MPSoC with hard-coded processor component and a set of soft-coded processorcomponents.

The following section gives an overview of the designchallenges for the industrial embedded systems. In Section IIIthe implementation of the legacy architecture is described. Fur-ther, Section IV introduces the hybrid SoC technology. SectionV contains the implementation details of the architecture. InSection VI a short case study on two industrial uses cases isgiven, followed by sections with related work and future work.Final sections contain closing words and acknowledgments.

II. CHALLENGES IN INDUSTRIAL EMBEDDED SYSTEMS

As an answer to the growing complexity issues of com-puter systems, hardware vendors introduced a multi-processorsystem-on-a-chip (MPSoC) architectures. The goal is to inte-grate multiple systems on a single chip with the possibilitiesto share its infrastructure without interference, and to saveon physical space and energy consumption. Embedded indus-trial applications are currently facing a number of imminentchallenges and the MPSoC technology provides an alternativesolutions to these problems:

• Performance. A major problem for industrial embed-ded applications, especially for the applications withsafety and real-time requirements, is how to replacesingle-core CPUs with multi-core CPUs in orderto achieve better performance. Integration of safety-crtical applications on multi-core architectures is ahot topic both for designers and for the certificationauthorities [3]. The multi-core architectures providethe necessary performance increase for industrial ap-plications, but they provide very little support for theintegration of multiple safety-critical applications or

mixed-criticality applications in a way that the per-formance gain is preserved. Specifically, a sufficientspatial and temporal isolation of components cannotbe achieved.

• Time predictability. The difference between embeddedindustrial applications and general purpose applica-tions is that they are often under constraint of time.Also, co-ordination of different tasks is necessary toachieve the time constraints. Multi-core CPUs arenot designed with sufficient level of determinism dueto intensive use of shared resources towards betterperformance. Hybrid SoC architectures can be moldedinto a system with high level of determinism andsufficient performance.

• Power Consumption. Environmental challenges havelead the industrial community to make a significanteffort in lowering the energy consumption of computersystems. Reducing the number of physical computercomponents in a system reduces overall power con-sumption. Further, selective and modular operationof a system provides more room for optimization ofpower consumption of individual system components.

• Mixed-Criticality Integration. As the general popula-tion is getting more and more dependent on internetbased services (i.e., communication, personal orga-nization, navigation) and as systems provide bettercapabilities for partitioning and segregation it is ex-pected that non-critical functions will get integratedwith safety-critical and real-time systems. The MPSoCtechnology offers these abilities almost by default.

• Adaptation. Embedded industrial application are oftendeployed in harsh, inaccessible and stochastic envi-ronments (e.g., space, deep sea). It is essential that thecorresponding computer system is able to adapt to en-vironment changes without loss of functionality. If anunforeseen event brings a system into a failure state,the ability to adapt can prolong the life of a system,and ensure reliability until the system is returned to asafe state. An MPSoC is set of hardware components,where a component can be used to monitor and changea state of another component without influencing therest of the system.

• Heterogeneity. A specialized hardware like digitalsignal processor (DSP) or graphics processing unit(GPU) is much more efficient in handling some tasksthan a standard CPU. Heterogeneity ensures efficiencyby allowing applications to be mapped to the corewhose execution will ensure best requirements cover-age. Heterogeneity of its requirements. It also providesversatility and mixed-integration capabilities.

It is clear that all these challenges are highly connectedand mutually dependent, this is why a solution must beuniversal, rather then ad-hoc solving one problem at the time.New technologies provide capabilities to implement alternativehardware architectures and evaluate them on real-life scenarios.

III. ACROSS MPSOC

The ACROSS MSPSoC [1] is a many-core architectureimplemented completely in an FPGA. At the core of theMPSoC is a time-triggered network on chip (TTNoC). Itconnects eight independent host components based on soft-coded Nios2 processors. Each components (also called µ-Component) is fully functional embedded system with localmemory and set of input/output peripherals (IOs). The TTNoCuses encapsulated communication channels and special linkinginterfaces to interact with µ-Components. Four µ-Componentsare used as system components performing system, config-uration and maintenance functions (i.e., global time service,mass storage, monitoring services, IO services). Other four µ-Components are reserved for application software. The appli-cation components share system components and their servicesin full temporal and spatial isolation provided by TTNoC. TheMPSoC provides two levels of of fault-tolerance: The on- andthe off-chip fault-tolerance. Each component is a fault contain-ment unit and the MPSoC is considered as error containmentunit. The architecture was designed using a services-orientedapproach, and it offers three types of services: core services,optional services, and application-specific services. The coreservices handle platform related tasks (e.g., basic communica-tion). The optional services provide extended functionality tocore services and can be modeled on a specific requirementsset (e.g., security). The application specific services are userlevel services implemented on top of the core and optionalservices. The ACROSS MPSoC is implemented with a uniqueset of IO connections to allow cross-domain integration.

IV. HYBRID SYSTEM-ON-A-CHIP

This paper explores the capabilities of the state-of-the-artFPGA devices and their ability to serve as an alternative toCOTS multi-core processors. Specifically, a crossover devicebetween these two technologies is being explored. In this paperit will be called a hybrid SoCs. The hybrid SoC is a device thatcombines FPGA and hard-coded processor on a single chip.FPGA devices are used extensively in embedded applications,especially in signal processing and communication devices.Most frequently it is used as a secondary device for specifictasks in a system. An FPGA is a programmable hardware, itcan be used to emulate hardware functions or to execute soft-ware modeled in the hardware like logic. It provides a platformfor prototyping of hardware or a tool for software acceleration.Recent advancements in FPGA production technology enabledsignificant increase in the capacity and performance of theFPGA devices. Figure 1 shows how the FPGA technologyadvanced in recent years regarding basic logic blocks. Otherproperties of FPGA devices increased equivalently. This putsuse of FPGAs as an alternative hardware architecture in a widerspectrum of industrial embedded applications (i.e., ACROSSMPSoC see Section III).

The rapid FPGA development trend correlates with theintroduction of hybrid SoCs. The FPGAs are flexible andcan be used to implement almost any function, hardware orsoftware. However, the implementation of standard hardwarearchitectures on FPGA is performance limited. On the otherside standard hardware architectures lack flexibility. The useof both devices in an interlocked architecture is relativelycommon (e.g., [6], [7]). The integration of the same devices

Fig. 1. Development of FPGA devices in recent years in reference to numberof fundamental logic blocks [4], [5].

on a single chip provides more performance, lower latenciesand the possibility to directly augment one or the other deviceand build custom architectures. Most notable architectures areZynq from Xilinx [8], Cyclon V and Arria V form Altera [9],[2], and SmartFusion2 from MiroSemi [10].

The hybrid SoC architecture provides a new dimensionfor embedded designers. The advantages of combining bothdevices can be utilized in a joint system with a low latency.In this paper we present a custom built architecture whichintegrates both FPGA and CPU in a reliable and deterministicfashion. The prototype platform chosen for this purpose isAltera Arria ST SoC (see Figure 2).

A hard-coded CPU implemented on this platform is theARM Cortex A9 dual-core processor. It is a central part of asystem called a hard processor system (HPS). It also includesa direct interfaced 1 GB DD3 memory, 32KB of instructionand data L 1 cache per core, shared 512 KB L2 cachememory, QSPI flash memory and a generic set of IOs (e.g.,USB, UART, Ethernet, GPIOs etc.). The second componenton the chip is an Arria V FPGA. It is a medium capacityprogrammable fabric (460K LEs) device. The FPGA has twodirect interfaced 1 GB memory modules, an FPGA specificset of control and programming devices and a generic set ofIOs. The communication hub on the chip is a L3 interconnect,that connects HPS with the FPGA and board peripherals.The interconnect has three dedicated AXI bus bridges forthe communication between HPS and FPGA: HPS-to-FPGA,FPGA-to-HPS and a lightweight HPS-to-FPGA. These allowmutual exchange of resources and full cooperation betweentwo systems. The block diagram of the Altera Arria V STSoC development board is shown in Figure 2.

How does the hybrid SoC respond to the challenges inindustrial embedded applications? When it comes to perfor-mance, a recent survey reports that an embedded systemsruns on ≤ 500 Mhz processors in average [11]. The hybridSoC is able to match that on the HPS side and ensure evenbetter performance. The FPGA is able to provide additionaldedicated cores or components which can be used acceleratetasks. It also provides a platform to integrate diverse systemswithout physical or logical overlapping. This is essential formixed-critical and cross domain systems. Clustering of systemson a single chip ensures efficient power consumption. Theoperation of the two systems are independent and ensures theisolation required for safety critical applications. Soft-codedcomponents also allow full segregation even within FPGA. An

Fig. 2. Arria V ST SoC development board and a block diagram of thecorresponding architecture.

other aspect of hybrid SoC which supports modern embeddedapplications is the capability to reconfigure one or the othersystem on run-time. For the future adaptive systems thisenables more flexibility where even hardware configurationof the system could be completely changed during run-time.Recent reports are predicting a huge improvement in hybridSoC technology in the coming years. This ensures longevityof the solutions built using this technology [12].

V. TIME-TRIGGERED MULTI-PROCESSORARCHITECTURE ON HYBRID SOC

The evaluation of the ACROSS MPSoC in industrialdemonstrators has confirmed the predicted assumptions inachieving mixed-criticality and cross domain integration usingthis architecture as valid. The goal of the architecture presentedin this paper is to integrate high performance components,and build a basis for a more generic setup with the focuson a modular interface defined integration of components.The design of embedded applications often includes overdimensioning to ensure longevity of a product, especially inindustrial domains where the design and certification pro-cess requires extremely large efforts (e.g., avionics systems,aerospace, industrial automation). it is essential to evaluate thescaleability, portability and the platform dependence of thearchitecture.The integration of TTNoC-based architecture onhybrid SoC shows promising results for a large spectrum ofindustrial embedded applications.

Fig. 3. Block diagram of the deterministic MPsoC architecture on hybridSoC.

The ACROSS legacy architecture was designed to hosta specific set of applications and provide a specific set ofservices. A number of these services are platform dependent,so porting the whole architecture was unpractical. To translatethe architecture to the new platform a number of the com-ponents needed to be adapted. The communication backboneremained unchanged just with slight modifications to conformthe platform and current programming toolchain. The essentialparts of the communication backbone are: TTNoC, trustedinterface subsystems (TISSs) and trusted resource manager(TRM).

The TTNoC consists of fragment switches that enablerouting of traffic and global time propagation. Each fragmentswitch is a module with four bi-directional channels for mes-sages and additional signals for propagation of a system wideglobal time. The fragment switches are combined together tocreate a network-on-chip. The size of the NoC depends on thenumber of fragment switches and it is bounded.

The TISS is a communication interface between theTTNoC and a µ-Component. Although, it is basically a partof a µ-Component, it is required if the components is to beintegrated in the TTNoC. The TISS is connected with theCPU of a µ-Component via dual-ported memory, local tothe µ-Component, and interrupt signals for task triggering. Italso provides an instance of the system-wide global-time forthe µ-Component. The global time is an essential propertyof a deterministic architecture, as it enables time-triggeredcommunication, coordinated execution of tasks and improvedfault-tolerance capabilities for the components [13]. The TISSis also the host for the configuration files necessary for time-triggered communication and task triggering. These can beonly accessed and modified by the TRM component.

The TRM is the µ-Component responsible for maintenanceand configuration of TTNoC and corresponding TISSs. Itcontains a tick generator which provides the basis for thesystem wide global time. The second important task of theTRM is the configuration of TISSs. The TRM is the onlycomponent allowed to change the state of the configurationmemory of a TISS.

All the soft-coded components were completely rebuiltand integrated into the MPSoC. The goal of the currentimplementation of the MPSoC is to create a basis for aplatform and application independent architecture. Namely the

intention is to fully utilize Altera’s system integration toolQSyS [14] and build a system in fully modular way. TheNios2 components are therefore designed on a generic modelwith clearly defined interfaces. This allows easy adaption ofthe components to service or application specific requirements,and simple integration of new components to the system.

One of the advantages of the TTNoC architecture is theability to connect heterogeneous components. The CPU of thecomponent must be able to interface the dual-ported memoryand receive interrupt signals. The Arria V ST SoC allowsdirect coupling of IP modules implemented on FPGA with theHPS system over the aforementioned interfaces (see SectionIV). This enables direct integration of the HPS with the restof the MPSoC. The new component is also represented as asingle module in the integration tool, although it is composedfrom building blocks located on both on FPGA and HPS.The coupling requires two interfaces one for the data transfer,or interfacing the local port memory and the other one forthe routing of interrupt signals. Figure 4 shows the HPScomponent and the way it is connected to the TTNoC overTISS.

Fig. 4. Block diagram of the HPS connection to the TTNoC

The heterogeneous approach increases fault tolerance ca-pabilities by adding another layer of fault tolerance within achip. Although they are physically parts of the same chip HPSand FPGA modules are completely independent. So on theFPGA there is a soft fault tolerance between µ-Components.A hybrid fault tolerance using HPS, which can be observed asan of chip fault tolerant unit from the FPGA point of view.The MPSoC is capable of phase synchronized operation withanother MPSoC. This extends its abilities with and enablesoff-chip fault tolerance. The architecture provides shows otherpromising properties that need to be explored in the future.A static configuration of the architecture is currently usedto setup the system. Next step in this direction would be to

consider possibility of dynamic adaptation and reconfiguration.The hybrid SoC allows partial reconfiguration of the SoCduring run-time, this ability can be utilized by the overlayinghardware architecture. Further, the HPS component providesnew possibilities but it also adds to the complexity of thesystem. The HPS has relatively complicated memory hierarchyand it is essential to map an application based on its safetyrequirements and fault hypothesis with the capabilities of theHPS component. This is also important for standard multi-corearchitectures. Other applications of HPS component include aruntime monitoring and verification, which are essential forthe dynamic adaptation and reconfiguration.

The initial tests of the proposed hardware architectureshowed successful integration of the above mentioned compo-nents with the TTNoC. The modular approach provides abilityto extend or reduce the MPSoC’s number of components inan simple and efficient way. Full evaluation of the system is awork in progress, as well as the integration of the technologyin an industrial use case. The first step was to rebuild andadapt the hardware components on to new platform, and toensure the functionality of the communication backbone. Ad-ditional results will be provided in an extension of this paper.Next chapter provides a short overview of the architecture’simplications on industrial use cases.

VI. INDUSTRIAL EMBEDDED SYSTEMS CASE STUDY

The motivation behind the work presented in this papercomes from industrial embedded applications. The spectrumof applications for the proposed architecture is wide as it isshown in [1]. In this section provide an overview of a couple ofuse cases, and discuss how they can benefit from the propertiesof the presented architecture.

1) Automotive control units (xCU): The automotive in-dustry is represented with a high number of units per yearand it needs to be in a continuous state of innovation inorder to ensure an economic progress. A recent reports showthe automotive industry produced about 90M vehicles lastyear[15]. A survey shows that major drivers behind in theautomotive industry are fuel efficiency and safety. The samesurvey reports that four important upcoming innovations in theindustry are: electric and hybrid power-trains, internet commu-nication, car-2-car communication, car-2-oem communication,and predictive consumer analytics [16]. How does this reflecton the embedded systems within automotive industry? Theconclusion that embedded systems will have to be able tohost more applications, from different safety zones and keepthe level of safety guaranteed for all of them. How does theproposed architecture answer to this challenge? It is capable ofrunning both safety critical and non-critical applications at thesame time. The HPS component provides more than adequateperformance capabilities for the present day applications andand future applications. It provides a specific fault hypothesismodel two layers of on-chip fault tolerance, and a promisingapproach for off-chip architecture. The work presented in[17] shows how the similar architecture can be used as anautomotive xCU. The clustering of the xCU on an MPSoCis shown to be an efficient alternative to implementation ofautomotive applications on high-performance COTS multi-core architectures. Clustering of xCU in complete isolation onMPSoC provides obvious advantages. For example, consuming

less physical space reduces weight and power consumption.Which in effect reduces fuel consumption and increases overalleffectiveness.

2) Space on-board computers: Contrary to the automotiveexample the space sector has low unit numbers and completelydifferent innovation focus. The production of space equipmentrequires high amount of efforts, due to harsh environment andlimited ability to perform repairs and changes. The applica-tions in space are more mission critical then safety critical.Nevertheless, they face similar problems when it comes tohardware architectures citeberrojo2015scalable. Both, seek toreduce number of on-board computers, increase performancecapabilities at the same time, and ensure energy efficiency. Thespace applications also require high adaptation capabilities.The costs of deploying and producing such a system are large,therefore the lifespan of the product must be substantial, andall components must be fault-tolerant. The mechanisms likeadaptation provide the ability to prolong the life of the systemby enhancing it or reducing its functionality (e.g., by removingnon-essential parts a system can perform basic functions fora longer period). The proposed architecture offers integrationof multiple applications on a single chip, with several layersof fault-tolerance. The hybrid SoC ensures ability to changethe configuration if necessary of each device on runtime by theother one. The heterogeneous integration is also very importantfor the space sector, as its applications operate with largeamounts of physical signals that can benefit from dedicatedhardware components.

VII. FUTURE WORK

At this stage the work presented contains a hardwarearchitecture and rudimentary software support. In this chapterwe present some of the additional actions included in ourfuture work on this topic. As stated in the introduction thegoal is to evaluate scaleability of the system by experimentingwith different setups of the architecture. The heterogeneousapproach is already integrated in the architecture, but there isstill room to expand it by integrating additional componentsbased on other CPUs. One of the concrete examples is theintegration of the Leon3 SPARC soft-coded processor fromGeisler [18]. The Leon3 has a fault-tolerant version and it ishighly utilized in space domain embedded systems. The secondgoal is to ensure efficient portability to future generations ofthe platform as well as the platform portability. This wouldcontribute to a more general use of the architecture.

VIII. RELATED WORK

The MPSoC related research has produced a high numberof publications in recent years. With the introduction of hybridMPSoC the availability of these systems increased dramati-cally, and so has the interest of the community. The researchon MPSoC is also the vocal point of several major researchinitiatives in EU. Projects ACROSS [19][1], MultiPartes [20],ARAMIS [21], EMC2 [22] are all investigating the introduc-tion of multi-core and MPSoC architectures in the domain ofsafety critical and mixed-critical systems.

The automotive industry is a highly interesting domain forMPSoC platforms.The author in [23] provides a demonstrationof vehicle powertrain implementation using Xilinx Zynq [8]

platform. Although it is a dedicated solution for a single appli-cation it is still showing the extent of the MSPoC’s capabilities.The authors in [24] provide a mapping of AUTOSAR [25] tothe MPSoC based architecture. Another example of MPSoCapplication for automotive use case is presented in [26]. Thepaper provides a framework for dynamic allocation of task toMPSoC components. It can be noticed that the hybrid SoCis most frequently used as application oriented systems. Thecapacity of the hybrid MPSoC to be used as generic platformfor industrial embedded systems is still to be explored.

The use of hybrid MPSoC applications stretches on multi-ple industrial domains. The authors in [27] give a survey on us-ability of the hybrid SoCs in the avionics domain, specificallyon the Xilinx Zynq platform. In [28] the authors explore thecapabilities of the hybrid MPSoC platform to perform dynamicpartial reconfiguration. These are only some of the worksfocused around hybrid MPSoCs. The direction of developmentof major hardware vendors confirms this statement [12] [29].

IX. CONCLUSION

This paper presented a heterogeneous MPSoC architecturefeaturing a time-triggered network-on-chip implemented on ahybrid SoC platform. The advantages of the hybrid SoC areused to enhance an an earlier version of the MPSoC with thehard-coded component of ARM Cortex C9 processors. In ad-dition to the HPS Component other novel aspects are includedin the process. A generic modular design as the basis for modeloriented development, adaptation and dynamic reconfiguration.We discussed the benefits of this architecture, on a couple ofuse cases, and shown the potential of this approach. The hybridSoC technology is becoming more available every day, and itscapabilities are increasing accordingly. The proposed MPSoCuses this technology to build an architecture capable of hostingindustrial embedded applications with even most demandingrequirements.

ACKNOWLEDGMENT

This research has received funding from the ARTEMISJoint Undertaking (JU) under grant agreement n◦ 621429. Theauthors would like to acknowledge the work performed in theproject founded by ARTEMIS JU under the ID ARTEMIS-2009-1-100208 (project ACROSS). Also this work is madepossible due to generous contribution of TTTech, as theygranted access to their IP essential for the work presented inthis paper. The responsibility for the content rests with theauthors.

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