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MPSoC

MPSoC Programming Solution

“CoreManager” hardware unit for:Dependency checkingTask scheduling Local memory management of PEs

C programmable No synchronization interrupts OS scheduling easedOperating System

Process

Thread Thread

t1 t2

t3

t4 t5

t6

t1 t2

t3 t4

t6

t5

CP CoreManager

TU Dresden Slide 1Heterogeneous MPSoC with Hardware Supported Dynamic Task Scheduling for SDR

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cessor 1

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cessor 3

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TU Dresden Slide 2Heterogeneous MPSoC with Hardware Supported Dynamic Task Scheduling for SDR

Heterogeneous MPSoC: ‘Tomahawk’

Vector FixedPoint DSP

Scalar FloatingPoint DSP

Core Manager

10 mm

10 mm

ControlProcessor

Scratchpad Memory

5.9 mm²~280 mW

3.8 mm², ~85 mW

2.5 mm²~30 mW

3.3 mm², ~27 mW

100 mm² @ 130 nm UMC; 40 GOPS, 1.5 W @ 175 MHz

LDPC DecoderFilter ASIP

Peripherals

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TU Dresden Slide 3Heterogeneous MPSoC with Hardware Supported Dynamic Task Scheduling for SDR

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1 2 3 4 5 6

5000 Cycles, 0%

5000 Cycles, 50%

2500 Cycles, 0%

2500 Cycles, 50%

Software Scaling Results

0% or 50% probability of dependence between tasks, 4kB data transfers (in and out)

Hardware task scheduling = power and performance efficient solution for MPSoC programming problem

Scalability depends on: Task-to-Scheduling time ratio Inter-Task dependency

Baseband signal processing: Task time ~102 – 104 cycles SW scheduling:

~1000 cycles/task HW accelerated scheduling:

~60 cycles/task

Number of Cores

Spe

edU

p