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A Grand Challenge for CMOS Scaling:Alternate Gate Dielectrics
Robert M. WallaceDepartment of Materials Science
University of North [email protected]
2© 2002 R.M.Wallace
So where is UNT?
3© 2002 R.M.Wallace
Outline• Performance expectations
– “New” Materials– SIA Roadmap
• Materials Considerations for Gate Dielectrics– Barrier Height and Permittivity– Thermodynamics and Stability– Dielectric Film Morphology and Structure– Gate Material Compatibility– Deposition Method– Reliability
• Future Directions
4© 2002 R.M.Wallace
CMOS Periodic Table1970’s
IA IIA IIIB IVB VB VIB VIIB VIII Ib IIb IIIA IVA VA VIA VIIA VIIIA
H He
Li Be B C N O F Ne
Na Mg Al Si P S Cl Ar
K Ca Sc Ti V Cr Mn Fe Co Ni Cu Zn Ga Ge As Se Br Kr
Rb Sr Y Zr Nb Mo Tc Ru Rh Pd Ag Cd In Sn Sb Te I Xe
Cs Ba La Hf Ta W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn
Fr Ra Ac
Ce Pr Nd Pm Sm Eu Gd Tb Dy Ho Er Tm Yb Lu Lu
Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lw Lw
5© 2002 R.M.Wallace
CMOS Periodic Table1980’s
IA IIA IIIB IVB VB VIB VIIB VIII Ib IIb IIIA IVA VA VIA VIIA VIIIA
H He
Li Be B C N O F Ne
Na Mg Al Si P S Cl Ar
K Ca Sc Ti V Cr Mn Fe Co Ni Cu Zn Ga Ge As Se Br Kr
Rb Sr Y Zr Nb Mo Tc Ru Rh Pd Ag Cd In Sn Sb Te I Xe
Cs Ba La Hf Ta W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn
Fr Ra Ac
Ce Pr Nd Pm Sm Eu Gd Tb Dy Ho Er Tm Yb Lu Lu
Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lw Lw
6© 2002 R.M.Wallace
Periodic Table for ULSIIA IIA IIIB IVB VB VIB VIIB VIII Ib IIb IIIA IVA VA VIA VIIA VIIIA
H He
Li Be B C N O F Ne
Na Mg Al Si P S Cl Ar
K Ca Sc Ti V Cr Mn Fe Co Ni Cu Zn Ga Ge As Se Br Kr
Rb Sr Y Zr Nb Mo Tc Ru Rh Pd Ag Cd In Sn Sb Te I Xe
Cs Ba La Hf Ta W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn
Fr Ra Ac
Ce Pr Nd Pm Sm Eu Gd Tb Dy Ho Er Tm Yb Lu Lu
Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lw Lw
7© 2002 R.M.Wallace
Explosion of New Materials!
From Semiconductor International, Feb. 2001; Tegal
8© 2002 R.M.Wallace
The Devices
A: Gate StackB: Source/Drain – ExtensionC: IsolationD: Channel
E: WellsF: Capacitor G: Si Starting MaterialH: Contact
Typical Chip Cross Section
Global
Intermediate
Local
Passivation
Low-k Dielectric
Etch Stop
Diffusion Barrier
Cu conductor with barrier
Pre-metal dielectric
W plug contact
Wire
Via
• Increasing complexity/functionality• Low cost• New materials required• Time to Market Shorter
Performance Expectations: CMOS Scaling
After ’99 SIA Roadmap
9© 2002 R.M.Wallace
Complementary Metal Oxide Semiconductor (CMOS) Technology
p substrate
n+ n+ p+ p+
nFET pFET
n tub
gate dielectric
gate electrode
10© 2002 R.M.Wallace
Current CMOS Gate Stack Strategies
Gate
Si
Upper interfaceGate DielectricLower interfaceChannel Layer
• Gate Materials– Poly-Si– Poly-SiGe – Metals/ Metal-Oxides, Nitrides
• Upper interface– Nitrided Oxides
• Gate Dielectric – Ultrathin Oxides– Plasma Oxynitrides– NO Stack, JVD Nitrides, N implants– Stable High-κ material ?
• Lower Interface– SiO2
– Nitrided Oxides
• Conventional CMOS ⇒ RTA to ~1050°C• Replacement Gate CMOS ⇒ T << 1050°C
11© 2002 R.M.Wallace
Semiconductor Industry Association 1997-2001 Roadmap
Firs t Year of IC Production 1999 2001 2003 2006 2009 20121997
Gate die lectric
Gate e lectrode
Sidewall spacer
THERMAL/THIN FILMSSilicon oxide
Dual dopedpoly with s ilic ide
Alternate gate
SiOxNy
Selective Tl s ilic ide
Alternates idewall material
high κ
SiOxNy
2001
Research Required Under Development Pre-Production
12© 2002 R.M.Wallace
Semiconductor Industry Association 1997 Roadmap• 2001 IRTS: Tox scaling aggressive
Tox = (εox/εdiel)Tdiel
Table 22 Thermal/Thin Films Gate Etch and Doping Technology RequirementsYear of First
Product ShipmentTechnologyGeneration
1997250 nm
1999180 nm
2001150 nm
2003130 nm
2006100 nm
200970 nm
201250 nm
Equivalent oxidethickness Tox(nm)
4–5 3–4 2–3 2–3 1.5–2 < 1.5 < 1.0
Thickness control(% 3σ)
± 4 ± 4 ± 4 ± 4–6 ± 4–8 ± 4–8 ± 4–8
Sidewall spacerthickness (nm)
100–200 72–144 60–120 52–104 20–40 7.5–15 5–10
= 2001
13© 2002 R.M.Wallace
Semiconductor Industry Association 1999 Roadmap 2001
14© 2002 R.M.Wallace
Summary of Published Results - TI
Papers of our work at TI• Hf-silicates: Wilk and Wallace, Appl. Phys. Lett. 74, 2854 (1999).• Zr-silicates: Wilk and Wallace, Appl. Phys. Lett. 76, 112 (2000). • Summary: Wilk, Wallace and Anthony, J. Appl. Phys. 87,484 (2000).
• Demonstrated tox < 18 Å with Hf6Si31O65 (κ ~ 11) directly on Si
• Demonstrated J ~ 1 x 10-6 A/cm2 @ 1 V with HfSixOy, ZrSixOy
• Hf and Zr silicate films investigated are amorphous, homogeneousand stable directly on Si up to at least 1050°C
• Since our first publication on silicates (May 99), numerous confirmations• UT-Austin (CVD, PVD), NC-State (PVD)• Evolving very fast!
• See the review in J. Appl. Phys. 89 (2001) 5243.
15© 2002 R.M.Wallace
Stability of Silicates on Si: Si cap
Si(100)
a-Si
HfSixOy
(a)
30 Å
As-Depositedtop Si at 25ºC
Si(100)
HfSixOy
(b)poly-Si
30 Å
After AnnealN2/1050ºC/20 sec
Wilk, Wallace and Anthony, JAP 87, 484 (2000)
16© 2002 R.M.Wallace
“New” Materials: Previous Work on HfO2 and ZrO2
• CVD growth of HfO2 and ZrO2 performed• DRAM Capacitor dielectric focus (relatively thick films)• Al, Mo and poly-Si electrodes were used• Large hysteresis observed ⇒ mobile ion transport (Oxygen well known)• Crystalline phases always observed ⇒ enhanced leakage• Surface preparation methods resulted in native oxides• Dit ~ 1x1012/cm2
1. M. Balog, M. Schieber, S. Patai and M. Michman, J. Cryst. Growth 17, 298 (1972)2. M. Balog, M. Schieber, M. Michman and S. Patai, Thin Solid Films 41, 247 (1977)3. M. Balog, M. Schieber, M. Michman and S. Patai, Thin Solid Films 47, 109 (1977)4. M. Balog, M. Schieber, M. Michman and S. Patai, J. Elec. Chem. Soc. 126, 1203 (1979)5. J. Shappir, A. Anis and I. Pinsky, IEEE Trans. Electron Dev. ED-33, 442 (1986)
17© 2002 R.M.Wallace
High-κ Materials Research Trend“New” Materials
2001: 22000: 21999: 31998: 41997: 0
TiO
2/Ta
2O5
Ta-M
-O
Al2
O3
HfO
2/H
f-Si-O
ZrO
2/Zr
-Si-O
Hf/Z
r-Al-O
Hf/Z
r-Si-A
l-O
Lant
hani
des
19971998
19992000
20010
2
4
6
8
10
12
14
# of studies
IEDM
+ V
LSI
18© 2002 R.M.Wallace
Recent HfSiO(N) Patents
19© 2002 R.M.Wallace
High-κ IP (Mainly Integration)
20022001
20001999Transistor
Capacitor0
1020
30
40
50
60
70
US
Pate
nts
High-k Patent Activity“New” Materials2002: 2 2001: 62000: 41999: 1 ?
20© 2002 R.M.Wallace
Transistor Figure of MeritStage Delay
Time
Vol
tage
τClock
τDelay
ICV
ICV
ICdVdt
dtdVCCV
dtdI
dtdQCVQ
dddelay ==⇒=⇒
==≡⇒
=
max
)(
τ
gatepn
FOMτττ ++
≡ 2 ,
τ is a measure of the the pull-up and pull down delay for NMOS and PMOSτgate « τn or τp
21© 2002 R.M.Wallace
Transistor Figure of MeritStage Delay and Fanout
in out
Vdd
Vs
Inverter stage NAND gate Logic Fanout
[Hz] ~2
11 CVI
IIVC
FOM
pd
nd
ddTOT
+
≡
ssors)microprocefor 3~( Fanout""
ctinterconne local junction escapacitanc parasitic
≡
+=+==
+=+=
F
CCC
CWCFLCFCC
ijp
pinvgpgateTOT
22© 2002 R.M.Wallace
Transistor Figure of MeritDependence on tox
maximum. has
~~
:0 and 0Let (d)
~1
~
:0 and 0Let (c)
~~
:0 and 0Let (b)
ith constant w~
:0 and 0Let (a)
2
00
,
0
,
0
,0
,0
FOMt
DBtAtC
vRW
tW
tCFL
vV
VVVVC
IFOM
RC
FOMt
tBA
C
tvWRFL
vV
VVVVFC
IFOM
RC
FOMt
BtAC
WtC
FL
vV
VVVVC
IFOM
RC
tFLv
VVVV
VFCIFOM
RC
ox
oxox
satsoxoxp
g
sat
dd
satDtGS
ddtot
d
sp
ox
oxox
satsg
sat
dd
satDtGS
ddgate
d
sp
ox
oxoxp
g
sat
dd
satDtGS
ddtot
d
sp
ox
g
sat
dd
satDtGS
ddgate
d
sp
⇒↓⇒
++
+
+
−−=⇒
≠≠
⇒↓↓⇒
+
+
−−=⇒
≠=
⇒↑↓⇒
++
−−=⇒
=≠
⇒−−
=⇒
==
αεεαεε
αεε
αεε
tox
FOM
(a)
No parasitics
(b)
Parasitic Capacitance only
(c)
Parasitic Resistance only
(d)
Parasitics included
23© 2002 R.M.Wallace
Gate Oxide “Thinning”
Device scale shrinking ⇒ device area decreasing
For transistors: ID ~ Cox(VG - Vth)2
Where: Cox = (εoxA) / tox; εox= κεo; κ = dielectric constant
But: VG – Vth limited for scaled devices and T ≥ 20°C
⇒ decrease tox or increase ⇒ Improve ID ⇒ Maximize Cox κ
Decrease tox ⇒ gate oxide thinning
⇒ Increase Direct Tunneling (leakage)
⇒ Defect sensitivity and reliability
24© 2002 R.M.Wallace
Direct Tunneling: Leakage
Tunneling through SiO2
• |VOX| < ΦM : Direct TunnelingVOX
Vgate ΦSiO
δΦM : Metal/SiOX barrier height
ΦSiO: SiOx/Si barrier height
VOX: Voltage drop across SiOx
δ : Band Bending voltage drop
Vgate : applied gate voltage
VB
CB
e-VOX
Thinning
• |VOX| > ΦM : F-N TunnelingMetal SiO2 Si
ΦM
25© 2002 R.M.Wallace
Gate Oxide Thinning: Leakage Current
Tunneling Leakage Current at Applied Gate Voltages
Gate Voltage (V)
0 1 2 3 4 5 6 7 810-7
10-6
10-5
10-4
10-3
10-2
10-1
100
101
102
103
10-8
10-7
10-6
10-5
10-4
10-3
10-2
10-1
100
101
102
Assumes 0.1 cm2 (or less) total gate area
50 W
100 mW
Gat
e C
urre
nt D
ensi
ty (A
/cm
2 )
Standby Power C
onsumption (W
)
Oxide Thicknessh5.6 nmg 3.5 nm53.0 nm62.5 nm
IBM (1995), Hu (1994)
26© 2002 R.M.Wallace
Recent studies: Scaled SiO2 Planar Transistor
Timp et al., IEDM Tech. Dig., p. 55 (1999).
27© 2002 R.M.Wallace
Gate Oxide Thinning: Leakage Current and Drive Current
See: Timp et al., IEDM Tech. Dig. (1997)
28© 2002 R.M.Wallace
Gate Oxide Thinning: Leakage Current and high-κ dielectrics
Gate Voltage (V)0 1 2 3 4 5 6 7 8
10 mW
Gat
e C
urre
nt D
ensi
ty (A
/cm
2 )Standby Pow
er Consum
ption (W)
High-κ withtox = 15 Å
15 Å oxide
1 µW
Assumes 0.1 cm2 (or less) total gate area
10 -110 010 110 210 3
10 -2
10 -3
10 -4
10 -5
10 -6
10 -7
10 -210 -110 010 110 2
10 -3
10 -4
10 -5
10 -6
10 -7
10 -8
29© 2002 R.M.Wallace
High-κ Leakage Current Reductionleakage current
15 Å SiO2
Gate (poly-Si)
Si Well
e-e-
source drain
Vapp
channel
high low 50 Å High-κ
Si Well
e-
e-
source drain
Gate (poly-Si)Vapp
channel
High-κ film ⇒ thicker gate dielectric
⇒ lower leakage with same performance
30© 2002 R.M.Wallace
Device scale shrinking ⇒ device area decreasingFor transistors: ID ~ Cox(VG - Vth)2
Where: Cox = (εoxA) / tox; εox= κεo; κ = dielectric constant⇒ Improve ID ⇒ Maximize Cox ⇒ decrease tox or increase κ
Gate Oxide “Thinning”
• Increased Leakage⇒ Option for microprocessors⇒ Not for low power (portable) applications
⇒ Increase εox ⇒ replace SiO2 with new material⇒Increase physical thickness for low power applications⇒Increase performance for microprocessors
• Decrease tox ⇒ gate oxide thinning⇒ Increase Direct Tunneling (leakage)⇒ Defect sensitivity and reliability
• Alternatives: New device designs
How to decide which High-κ material is best?
31© 2002 R.M.Wallace
Gate Oxide Thinning: Ultimate Limits?
• Total capacitance limited by• Gate-Electrode• Dielectric• Inversion
• Limit of tox ~ 0.5nm predicted
See: Momose, et al., Trans. Elect. Dev. 43 (1996)1233H.Iwai in Proc. Electrochem. Society, Vol. 2000-2 (2000) 3
32© 2002 R.M.Wallace
Outline
• Performance expectations
• Materials Considerations for Gate Dielectrics
• Future Directions
33© 2002 R.M.Wallace
Materials Considerations for Gate Dielectrics
• Barrier Height and Permittivity
• Thermodynamics and Stability
• Dielectric Film Morphology and Structure
• Interface Quality
• Gate Material Compatibility
• Deposition Method
• Reliability
34© 2002 R.M.Wallace
Frequency dependence of εCMOS
ElectronicIonic
35© 2002 R.M.Wallace
High-κ Stack vs. Single Layertox = tSiO + (εox/εdiel)tdiel
Si
SiO2
30 Å (κ = 25)
5 Å (κ = 3.9)
metal gate
(1)tox(1) = 10 Å
Si
SiO2
poly-Si gate
40 Å (κ = 16)
(2)tox(2) = 10 Å
High-κLayer
InterfacialLayer(SiO2)
• tphys(1)< tphys(2) = 40 Å ⇒ lower tunneling current• More interface traps for (1)?• Moderate increase in dielectric constant for (2)• Stable single layer ⇒ retains poly-Si compatibility
36© 2002 R.M.Wallace
Leakage Current: ε vs. EG (and ∆EC)Tunneling through Dielectrics
ΦM
Gate Dielectric Si
∆ΕC
ΕCΕF
ε
EG
• J ~ exp (-∆EC)• Assume that ∆EC~EG• Want high ∆EC, tradeoff with ε
37© 2002 R.M.Wallace
Gate Dielectric Properties: Barrier Height and Permittivity
Material Dielectric Band Gap ∆Ec (eV)Constant (κ) Eg (eV) to Si
SiO2 3.9 8.9 3.2Si3N4 7 4.75 2.4Al2O3 8.5 - 11 6.95 - 8.8 2.08Y2O3 15 5.6 2.3CeO2 26 5.5 (a)Ta2O5 26 4.5 0.3La2O3 27-30 4 2.3TiO2 80 3.5 1.2HfO2 22 - 24 5.7 1.13 - 1.5ZrO2 25 5.5-5.7 1.5
HfSixOy 6.4-12 ~6 1.5ZrSixOy 8 - 12 4.4 0.8 - 1.5
(a) no value reported
Robertson, J.V.S.T. B18 (2000) 1785
-6
-4
-2
0
2
4
6
Ener
gy (e
V)SiO2
4.4
3.5
1.1
2.4
1.8
0.3
3.0
-0.1
2.3
Si3N4Ta2O5
BaTiO3
BaZrO3
ZrO2
Al2O3
Y2O3 ZrSiO
4.9
2.82.3
2.6 3.4
1.51.5
3.43.3
1.4
3.4
0.8
Si HfO2
-6
-4
-2
0
2
4
6
Ener
gy (e
V)SiO2
4.4
3.5
1.1
2.4
1.8
0.3
3.0
-0.1
2.3
Si3N4Ta2O5
BaTiO3
BaZrO3
ZrO2
Al2O3
Y2O3 ZrSiO
4.9
2.82.3
2.6 3.4
1.51.5
3.43.3
1.4
3.4
0.8
Si HfO2
(b) corrected
(b)44
• Dielectric Constant κ ~ 1/EG ⇒ 1/∆EC
• For T≥20°C applications, ∆EC ≥ 1 eV
38© 2002 R.M.Wallace
Recent Results: Photoelectron Spectroscopy
Thin film vs. bulk measurements
Miyazaki, JVST B19 (2002) 2212, from PSCI 2001Hiroshima University
39© 2002 R.M.Wallace
Electron transport - TheoryNC STATE UNIVERSITY
Tox = 2 nmκSiO2 = 3.9κSiOxNy = 5.7κSi3N4 = 7.5κD1= 25κD2 = 30
Single LayerandHigh-κ Stack
• Single layer and stack reduces tunneling current• Barriers introduced by stack approach• Injection polarity dependence
Vogel, et al., IEEE Trans. Elec. Dev. 45, 1350 (1998).
40© 2002 R.M.Wallace
NC STATE UNIVERSITY
High-κ Stack (theory)
Tox = 2 nmκSiO2 = 3.9κD1= 25
• Barriers introduced by stack approach• Injection polarity dependence• Increase in voltage ⇒ barrier changes
Vogel, et al., IEEE Trans. Elec. Dev. 45, 1350 (1998).
41© 2002 R.M.Wallace
Materials Considerations
• Barrier Height and Permittivity• Thermodynamics and Stability• Dielectric Film Morphology and Structure• Interface Quality• Gate Material Compatibility• Deposition Method• Reliability
42© 2002 R.M.Wallace
Gate Dielectric Properties:Thermodynamics and Stability
Material Dielectric Band Gap ∆Ec (eV) ∆HF
Constant (κ) Eg (eV) to Si (eV/O atom)SiO2 3.9 8.9 3.2 -4.68Si3N4 7 4.75 2.4 -------Al2O3 8.5 - 11 6.95 - 8.8 2.08 -5.76Y2O3 15 5.6 2.3 -4.93CeO2 26 5.5 (a) -5.02Ta2O5 26 4.5 0.3 -2.09La2O3 27-30 4 2.3TiO2 80 3.5 1.2 -4.86HfO2 22 - 24 5.7 1.13 - 1.5 -5.77ZrO2 25 5.5-5.7 1.5 -5.66
HfSixOy 6.4-12 ~6 1.5 -5.24ZrSixOy 8 - 12 4.4 0.8 - 1.5 -5.21
(a) no value reported
• Al, Hf, Zr and La oxides/silicates• Moderate-κ for Al-oxides and silicates• Predicted to be thermodynamically stable on Si
43© 2002 R.M.Wallace
After Beyers, J. Appl. Phys. 56, 147 (1984)and Wang and Mayer, J. Appl. Phys. 64, 4711 (1988)
Thermodynamic Stability of Silicates (700 - 900ºC)
Ta SiTaSi2Ta2Si
SiO2
O
Ta2O5
Chatterjee et al, ‘99 IEDM, p. 777
gate
Ta2O5
Si 50 Å
Taylor et al., JACS 121, 5220 (’99)
Ti SiTiSi2Ti5Si3 TiSi
TiO2 SiO2
O
Ti2O3TiO
TiO2
Si 50 Å
gate
Wilk et al., JAP 87, 484 (‘00)
Zr SiZrSi2Zr2Si ZrSi
ZrO2
O
SiO2ZrSiO4
Si(100)
Hf-Si-O
gate
40 Å
44© 2002 R.M.Wallace
La vs. Hf silicates: stability
• XRD analysis for onset of crystallization
• Increased SiO2preserves amorphicity
• La: >70% SiO2• Hf: >80% SiO2• After 1000C (4 min)
– La-silicate: κ~14 – Hf-silicate: κ~10
NC STATE UNIVERSITY
A. Kingon, et al., Nature 406 (2000) 1032
45© 2002 R.M.Wallace
IBMLa-Silicates
SiO2
La2Si2O7
• PVD of 2nm LaOx/2.3 nm SiO2 + 5×10-3 Torr O2 @ 850 C
• SiO2 layer limits capacitance, but promotes superior Dit
• VFB > 1200 mV• La-silicate: κ~30 (ignoring
SiO2 layer)
Copel, et al., APL 78 (2001) 1607
46© 2002 R.M.Wallace
NC STATE UNIVERSITY
Al2O3 Gate Dielectrics: PVD• Interface reaction kinetics results in silicate formation
Si
AlSixOy
Al2O3
See: Klein, et. al, Appl. Phys. Lett. 75 (1999) 4001.
47© 2002 R.M.Wallace
Stability: Reactions at Interfaces
37 A
As deposited
RTA N2 180s
1100 oC N2 F/A
UNT - unpublished• Sub-oxide formation at interfaces• Crystallization
Y Kim, et al., IEDM 2001 (Int’l Sematech, ASM)
48© 2002 R.M.Wallace
Thermal stability studies: Motivation
Critical regions for impurity diffusion in MOS transistors
12
3
4Gate Dielectric
3
1. Channel: mobility degradation and therefore impact electrical performance
2. Gate: Silicide formation
3. Source and Drain: enhanced leakage
4. Sidewalls: compromised isolation
Impurity concentration (cm-3)
Drift mobility of Si at 300 K *
* From S. M. Sze Physics ofSemiconductors devices (1981)
49© 2002 R.M.Wallace
Hf and Zr stability studies:Sample preparation flow diagram
Silicon waferHF-last
H H H H H H H H H H
H-terminated surface
PVD, CVD
~ 5 nm dielectric film
Anneals:6min N2
1100-700 C or 1050 RTA
30-180s
≤ 3.2 nm MSixOy [M] ~ 0
H-terminated Si surface + remnant Zr or Hf
ToF SIMSXPSRBSSEMHRTEM
Characterization
49% HF 20s
Zr/Hf incorporationin Si: diffusion length
50© 2002 R.M.Wallace
“Knock-on” study: sputter crater technique comparison
Silicon substrate
Pre-cleaning700 eV O2 1s
Sputter crater formationwith 700 eV O2
Single crater ToFSIMS Setup
Single-crater sputter technique
• Single-crater sputtering acquisition induces more “knock-on” effects Depth profile distortion
•Every high energy (12 keV) Ga probe cycle produces more “knock-on”
Probe Beam12 KeV Ga+ (35o)
51© 2002 R.M.Wallace
“Knock-on” study: sputter crater technique comparison
Multi-crater ToFSIMS
Multi-crater sputter technique
• Independent crater formation with different crater depths (≤20nm) reduces this knock-on effect
• Only 1 Ga probe cycle per crater reduced “knock-on”
Silicon substrate
Pre-cleaning700 eV O2 1s
Sputter crater formationwith 700 eV O2Probe Beam
12 KeV Ga+ (35o)
Craters
52© 2002 R.M.Wallace
InterdiffusionMulticrater ToFSIMS depth profiling
Depth (nm)
0 5 10 15 20
Hf c
once
ntra
tion
(at/c
m3 )
1e+16
1e+17
1e+18
As deposited 30 s
As deposited30 s180 s
Crater
Reg. Sputt.
180 s
Hf-silicate + 1050 C, N2(APL 79 (2001) 4192)
Depth (nm)0 5 10 15 20 25
Zr c
once
ntra
tion
(at/c
m3 )
1015
1016
1017
1018
1019
1020As dep/etched1000 oC 1100 oC
108
109
1010
1011
1012
1013
2
LD
RTA 180 sRTA 90 sRTA 30 s
Zr-silicate + 1050 C, N2(APL 79 (2001) 2958)
Zr c
once
ntra
tion
(at/c
m)
• Care must be taken in depth profile measurements• Zr interdiffusion observed• For DLTS, see Lemke, Phys. Sol. St 122 (1990) 617
53© 2002 R.M.Wallace
Materials Considerations
• Barrier Height and Permittivity• Thermodynamics and Stability• Dielectric Film Morphology and Structure• Interface Quality• Gate Material Compatibility• Deposition Method• Reliability
54© 2002 R.M.Wallace
Crystalline vs. Amorphous Gate DielectricPoly-Si
Gate Dielectric
Poly-SiO2interface
SiO2-Si interface
Si Substrate
Poly-crystalline Amorphous
• Robust, thermal SiO2 the benchmark• Avoids orientation/grain size dependence of polarizibility• Avoids enhanced leakage or diffusion through grain boundaries• New single crystal dielectrics require Epitaxial approach
AmorphousAdvantages
55© 2002 R.M.Wallace
Gate Dielectric Properties:Dielectric Film Morphology
(a) no value reported
Material Dielectric Band Gap ∆Ec (eV) ∆HF CrystalConstant (κ) Eg (eV) to Si (eV/O atom) Structure(s)
SiO2 3.9 8.9 3.2 -4.68 amorphousSi3N4 7 4.75 2.4 ------- amorphousAl2O3 8.5 - 11 6.95 - 8.8 2.08 -5.76 amorphousY2O3 15 5.6 2.3 -4.93 cubicCeO2 26 5.5 (a) -5.02 cubicTa2O5 26 4.5 0.3 -2.09 orthorhombicLa2O3 27-30 4 2.3 hexagonal, cubicTiO2 80 3.5 1.2 -4.86 tetrag. (rutile, anatase)*HfO2 22 - 24 5.7 1.13 - 1.5 -5.77 mono., tetrag., cubic*ZrO2 25 5.5-5.7 1.5 -5.66 mono., tetrag., cubic*
HfSixOy 6.4-12 ~6 1.5 -5.24 amorphousZrSixOy 8 - 12 4.4 0.8 - 1.5 -5.21 amorphous
• Thermal budget considerations to avoid nanocrystal formation• Conventional CMOS process flow vs. Replacement Gate process
56© 2002 R.M.Wallace
Sharp
ZrO2:Al Gate Dielectrics: PVD
See: Ma, et. al, IEDM Symp. Tech. Dig., (1999).
57© 2002 R.M.Wallace
Dopant Penetration
B Penetration upon RTA
Suppression from N incorporation
Al2O3
Park, et al. APL 77 (2000) 2207 (Hyundai)
58© 2002 R.M.Wallace
Onishi, et al, VLSI (2001) UTHfO2
Dopant PenetrationZrO2
Koyama, et al, IEDM (2001)Toshiba
B Penetration upon RTA
Suppression from N incorporation
59© 2002 R.M.Wallace
Enhanced Leakage and Grain Boundaries?• Well known effect for Ta2O5
• see Oerhlein, et al. JAP 55 (1984) 3715• see Nishioka, et al., IEEE TED 34 (1987) 1957
From Zhu, et al., IEDM 2001 (Yale, JPC, IBM)
60© 2002 R.M.WallaceGusev, et al., IEDM 2001 (IBM)Buchanan, et al. IEDM 2000 (IBM)
Enhanced Leakage and Grain Boundaries?
61© 2002 R.M.Wallace
Materials Considerations
• Barrier Height and Permittivity• Thermodynamics and Stability• Dielectric Film Morphology and Structure• Interface Quality• Gate Material Compatibility• Deposition Method• Reliability
62© 2002 R.M.Wallace
The Benchmark: Amorphous SiO2(and current results for high-k materials)
• Interface State Density: Dit<5×1010/cm2 (>1011)• Flatband Voltage Shift: ∆VFB<20 mV (>300 mV)• Hysteresis: δVFB<20 mV (>20 mV)• Hard Breakdown: EBD>10MV/cm• C-V Dispersion: none• Leakage (Tunneling) Current: <10-4A/cm2@VDD
63© 2002 R.M.Wallace
Fixed Charge in High-κ dielectrics• Positive fixed charge frequently observed in dielectrics• Al-based dielectrics exhibit negative fixed charge
Ideal C-V
Ideal C-V
V
V0 +_
VFB
VFB
+Qf
-Qf
C
High frequency C-V
EV
EC
EF
EI
Vacuum Level
EF
qΦM qΦB
qχ
metal dielectric p-type semiconductor
Eg
qΨB
64© 2002 R.M.Wallace
Controlling flatband shiftsIBM
Gusev, et al., IEDM 2001 (IBM)
• Nitridation of interface to control VFB shifts• Tradeoff with capacitance
65© 2002 R.M.Wallace
Charge Trapping
Gusev, et al., IEDM 2001 (IBM)
66© 2002 R.M.Wallace
Mobility and Soft Phonons:Fundamental Limitation?
• High-k materials have highly polarizable bonds • Coupling to soft surface-optical phonons• Coupling strength proportional to:
0
10 2
1 1 ;SOs ox s ox
s oxSO TO
s ox
ωε ε ε ε
ε εω ωε ε
∞ ∞ ∞
∞
∞ ∞
− + +
+= +
h
• Some screening of phonons possible by using thin SiO2 interfacial layers
See Fischetti, et al., JAP 90 (2001) 4587 (IBM)
67© 2002 R.M.Wallace
Materials Considerations
• Barrier Height and Permittivity• Thermodynamics and Stability• Dielectric Film Morphology and Structure• Interface Quality• Gate Material Compatibility• Deposition Method• Reliability
68© 2002 R.M.Wallace
Metal Gate Issues
vacuum
Ec
Ev
1.1 eV
ΦM TiN
n Vt
p Vt
Single Midgap Metal
Si Ec
Ev
ΦMΦM Pt
1.1 eV
Dual Metals
SiAl
n Vt
p Vt
• Metals eliminate poly depletion and B penetration• Midgap metals have Vt ~ 0.5 eV - too high (VDD ⇒ 1 V)• Dual metals achieve low Vt - processing?• Near term dielectrics must be compatible with poly-Si(Ge)• Near term dielectrics must also be compatible with metals
69© 2002 R.M.Wallace
Metal Gates?
• Poly-Si predicted to be phased out beyond 70nm node– Poly-Si properties (Work function Φ) controlled by implantation doping– But Poly-Si depletion ⇒ effective increase in tox
– Channel autodoping by outdiffusion of poly-Si (B) dopants
• Dual Metal Gates– Compatible with any alternative gate dielectric– Replacement Gate Process Flow: a possibility?– Cost?– For NMOS: EF~EC
– For PMOS: EF ~EV
70© 2002 R.M.Wallace
Metal Gates and Work FunctionH. Matsuhashi and S. Nishikawa Jpn. J. Appl. Phys. Vol 33 p. 1293 (1994).
S. M. Sze, “Physics of Semiconductor Devices” p. 397 (1981).
WN
MoN
p+ poly-Si
n+ poly-Si
TaN
TiN
TaN
WN
TiNWNMoN
MoN
Ta
Ti
W
Ta
Mo
Mo
W
Ti
TaTiNW
Wor
k Fu
nctio
n (e
V)
Mo
3.8
4.0
4.2
4.4
4.6
4.8
5.0
5.2
5.4
As Deposited After 400C After 800CTexas Instruments
71© 2002 R.M.Wallace
Metal Implantation and AlloysN Implantation of MoLu, et al., IEDM 2000;
Ranade, et al.MRS 2000(UC Berkeley)
Ru-Ta AlloysZhong, et al., IEDM (2001) (NCState)
72© 2002 R.M.Wallace
Materials Considerations
• Barrier Height and Permittivity• Thermodynamics and Stability• Dielectric Film Morphology and Structure• Interface Quality• Gate Material Compatibility• Deposition Method• Reliability
73© 2002 R.M.Wallace
Deposition Methods• Physical Vapor Deposition (PVD)
– Sputtering, evaporation, ablation, etc.– Convenient for materials screening– Appears to provide superior results– Planar, Line-of-sight process, damage– Not likely to be used in ULSI gate process
• Chemical Vapor Deposition (CVD)– Common in ULSI processing– Potential for thin layers by self-limiting growth (ALD) – Requires control of precursor chemistries– Throughput for ALD?
• Epitaxial Methods (MBE, etc.)– Permits single crystal, high-k dielectric systems– Requires submonolayer control– Poor throughput by ULSI standards– UHV Tools and Maintenance Costs
74© 2002 R.M.Wallace
Atomic Layer Deposition
• Superb thickness control and uniformity
• Growth rate linear with # cycles
• Highly conformal CVD process
• Proven for large area display technology
• Manufacturable for CMOS throughput?
• Restricted to binary oxides?
• Precursors for high-κ metals not certain
75© 2002 R.M.Wallace
IBM
Al2O3 Gate Dielectrics: ALCVD
See: Gusev, et. al, Appl. Phys. Lett. 76 (2000) 176.
76© 2002 R.M.Wallace
IBM
ZrO2 Gate Dielectrics: ALCVD
• Initial oxide layer good ZrO2
• No initial oxide poor ZrO2
See: Copel, et. al, Appl. Phys. Lett. 76 (2000)
77© 2002 R.M.Wallace
SrTiO3 Gate Dielectrics: MBEMotorola
See: Eisenbeiser, et. al, Appl. Phys. Lett. 76 (2000) 1324.
Excellent Results• tox of ~0.8 nm for a film 11 nm thick• Dit ~6.4×1010/cm2 eVLimitations• Requires UHV for deposition• Anti-phase boundary concerns• Low throughput• High-κ Perovskites require metal gate
78© 2002 R.M.Wallace
Singapore
Y-stabilized ZrO2
• Laser MBE grown• Commensurate
interface with some misfit dislocations
• Tox=1.46 nm, κ~16
Wang, et al., APL 78 (2001) 1604
79© 2002 R.M.Wallace
Materials Considerations
• Barrier Height and Permittivity• Thermodynamics and Stability• Dielectric Film Morphology and Structure• Interface Quality• Gate Material Compatibility• Deposition Method• Reliability
80© 2002 R.M.Wallace
Reliability
• Requires established materials system• Voltage acceleration nuances for SiO2 only
recently understood • Requires proper area scaling• Requires statistical significance• Expectation: equivalent to SiO2 or better.
81© 2002 R.M.Wallace
Desirable Advanced Gate Dielectric PropertiesPhysical Properties
• κ ~ 15 - 60
• Conduction Band Offset: ∆EC ~ 1 eV(high band gap)
• Thermally stable next to Si
• Remain amorphous during processing
• Form high-quality interface with Si
• Block Boron Penetration
Electrical Properties
• tox < 10 Å
• J < 10-4 A/cm2 @ VDD
• Dit < 5 x 1010 cm-2
• VFB & hyster. < 20 mV
• no C-V dispersion
82© 2002 R.M.Wallace
Outline
• Performance expectations
• Materials Considerations for Gate Dielectrics
• Future Directions
83© 2002 R.M.Wallace
Future Directions
• Narrowing near term gate dielectric solutions based on scientific understanding
• Extensive reliability studies of materials• Cross correlations of materials properties and electrical
measurements• Explore applications to other device technologies• New device designs and the associated materials issues• Research required on long term solutions for tox<0.5nm
84© 2002 R.M.Wallace
Summarylow κ!• SiO2 has only one disadvantage:
• High-κ has only one advantage: high κ!
• Follow “materials considerations” to arrive at best high-κ choice
• Interface quality most crucial property• Must make transistors as true test
85© 2002 R.M.Wallace
AcknowledgementsUniversity of North Texas (www.mtsc.unt.edu) • Manuel Quevedo-Lopez - Grad Student• Dr. Swarnagowri Addepalli - Postdoc• Prof. Bruce Gnade• Prof. Mohammed ElBounani
Texas Instruments• Dr. Luigi Colombo• Dr. Mark Visokay• Dr. Antonio Rotondaro
• Agere Systems: Glen D. Wilk
• Semiconductor Research Corporation• Texas Advanced Technology Program• DARPA