CMOS down scaling toward sub-10 nm

　Hiroshi Iwai

Tokyo Institute of Technology

Yokohama, Japan

Outline of my talk

4. Summary and Conclusions

2. Current downscale scheme and its problems

1. Downscaling and its possible limit

3. Examples of expected difficulties and some solutions

1. Downscaling and its possible limit

Integrated Electronic Circuit• Electronics:

Most important invention in the 20th century

• Electronic circuits in 100 years

Vacuum tube ULSI

History of Electronic Devices

Transistor Concept

IC

Vacuum tube 1st Electronic circuits

Solid-State Circuits

Silicon TechnologyLSI

2000

70

60

50

30

20

10

1900

TriodeDiode

MOSFETMISFET

bipolarICSi-MOSFET

1st Transistor

VLSI

LSI

CMOS

30 years

ULSI

20 years

10 years

Low Power

High Integration

Low PowerHigh speedHigh integration

Low PowerHigh speedHigh integration

Lee De Forest

1906: Vacuum Tube : Triode

J.E.LILIENFELD

J. E. LILIENFELD

DEVICES FOR CONTROLLED ELECTRIC CURRENT

Filed March 28, 1928

1960: First MOSFET by D. Kahng and M. Atalla

1970,71: 1st generation of LSIs　

DRAM Intel 1103　 MPU Intel 4004　

Downsizing of the components

1900 1950 1960 1970 2000

VacuumTube

Transistor IC LSI ULSI

10 cm cm mm 10 m 100 nm

In 100 years, the feature size reduced by one million times

10-1m 10-2m 10-3m 10-5m 10-7m

Importance of Downsizing

Capacitance reductionPower reduction

Speed increase

High integration Function increase

Parallel processing

Downsizing:

Sneed increase

magnification

6 m NMOS LSI in 1974

Layers

Source/Drain diffusion

Gate oxide

Si substrate

Field oxide

Poly Si gate electrode

Interlayer dielectrics

Aluminum interconnects

Passivation

Materials

Si, SiO2

BPSGPSGAl

Atoms

Si, O, Al,P, B

(H, N, Cl)

Si substrate

Field SiO2

ILD (InterlayerDielectrics)

Al interconnects

Passivation (PSG)

(SiO2 + BPSG)Si substrate

Field SiO2

ILD (InterlayerDielectrics)

Al interconnects

Passivation (PSG)

(SiO2 + BPSG)

Poly Si gate electrode

Gate SiO2

Source / Drain

Poly Si gate electrode

Gate SiO2

Source / Drain

magnification

magnification

magnification

W via plug

W contact plug

CoSi2

Low k ILD

Ultra-thin gate SiO2

0.1 m CMOS LSI in 2002Large number of layers, Many kinds of materials and atoms

Downscaling is important.

Then, what will be the limit in downscaling?

Prediction of downsizing limit

Vacuum tube era ： even m size could not be imaginedSince Si IC started

Late 1970’s 1m: SCE

Early 1980’s 　 　　 0.5m: S/D resistance

Early 1980’s 　 　 0.25m: Direct-tunneling of gate SiO2

Late 1980’s 　 　　　 0.1m: ‘0.1m brick wall’(various)

Today 50nm: ‘Red brick wall’ (various)

Today 10nm: 　 　　　　　　　 Fundamental?

Period Expected Cause limit(size)

VLSI textbook

For this reason, even those circuits optimized for operation at the lowest possible supply voltages still require a VDD of = 0.5 volts. Devices in 1978 operate with a VDD of approximately five volts and minimum channel lengths of approximately six microns. Therefore, the kind of scaling we have envisioned here will take us to devices with approximately one-half micron channel lengths and current densities approximately ten times what they are today. Power per unit area will remain constant over that range. Smaller devices might be built but must be used without lowering the voltage any further. Consequently the power per unit area will increase. Finally, there appears to be a fundamental limit 10 of approximately quarter micron channel length, where certain physical effects such as the tunneling through the gate oxide and fluctuations in the positions of impurities in the depletion layers begin to make the devices of smaller dimension unworkable.

Ultimate limitation

10 -5

10 -4

10 -3

10 -2

10 -1

100

101

102

1970 1990 2010 2030 2050

Year

MPU LgJunction depthGate oxide thickness

Direct-tunneling limit in SiO2

ITRS Roadmap(at introduction)

Wave length of electron

Distance between Si atoms

Siz

e (

m),

Vol

tage

(V)

Min. V supply

10 nm

3 nm

0.3 nm

ULTIMATELIMIT

There will be a practical limit before the ultimate limit.

Reasons: Cost , Yield, Reliability, Performance, etc.

However, no one knows the practical limit. It is too early to give up.

photo resist

polysilicon

photo resist

substratepolysilicon

photo resist

polysilicon

Shape of Photo resist and Polysilicon

Resist ashing Dec, 1993

0.0 0.4 0.8 1.2 1.6 2.00.00

0.21

0.42

0.63 Vg = 2.0 V

Vg = 1.6 V

Vg = 1.2 V

Vg = 0.8 V

Gate Length = 40 nmD

rain

Cu

rren

t [m

A/µ

m]

Drain Voltage [V]

Id-Vd Characteristics

Dec. 1993

TEM photograph of 1.5 nm gate oxide

1.5 nm gate oxide MOSFETs Dec 1994

Cross-sectional　 TEM　 image　 of　 1.5　 nm　 gate　oxide　[5].

Si

O

Si-Si: 0.314 nm

0.26

2 nm

0.162 nm

10-2

10-6

10-4

10-8

10-10

10-12

0

0.8

0.4

1.2

0 1.50.5 1.0 0 0.4 0.8 1.2 1.6

1000

600

400

Drain Voltage [V]

Dra

in C

urr

ent

[mA

/m

]

Dra

in C

urr

ent

[mA

/m

]

Drain Voltage [V]

Tra

nsc

ond

uct

ance

[m

S/m

m]

Vd = 1.5 V

Vd = 0.05 V

Vd = 1.5 V

Vd = 0.05 V

Vg = 1.5 V

1.25 V

1.0 V

0.75 V

0.5 V

0.25 V

gm max =1020 mS/mm

1.5 nm gate oxide MOSFET

Lg = 0.07 m

Acceleration of downsizing in ITRS

Year

1999

2001

1994

0.1

1

10

CP

U C

lock

Fre

qu

ency

(G

Hz)

90 95 00 05 10 15 20

Year

1999

2001

199419941994

0.1

1

10

CP

U C

lock

Fre

qu

ency

(G

Hz)

90 95 00 05 10 15 2090 95 00 05 10 15 20100

101

102

103

1990 1995 2000 2005 2010 2015 2020

Lg

(n

m)

Year

Acceleration

1999

2001

1994

2007?

Unknownregion

2003?

ITRS accelerated every year!!

Sub-10 nm CMOS would be in production in 2008

Roadmap (prediction) of ITRS itself is necessary.

2005?

(gate length)

Already15 nm gate length CMOS

B.Yu et al. IEDM’01 p.937

Limiting factor for sub-10 nm CMOS

Depletion layer formation

Direct-tunneling current

High S/D extensionresistance

Inversion layer capacitance

Impurity non-uniformity

Direct-tunnelingcurrent

Fringing capacitance

H. Kawaura et al., Ext. Abst. SSDM, pp. 20 - 21 (1999)

Sub-10-nm-gate EJ-MOSFET

B. Doris et al., “Extreme scaling with ultra-thin SOI channel MOSFETs”, IEDM Tech., Dig., pp.267 - 270, San Francisco, December, 2002

6nm gate length p-MOSFET

What is the biggest problem now?

Probably, Power increase for a chip operation and Cost increase for next generation lithography including mask making

Year of introduction Transistors

4004 1971 2,250

8008 1972 2,500

8080 1974 5,000

8086 1978 29,000

286 1982 120,000

386™ processor 1985 275,000

486™ DX processor 1989 1,180,000

Pentium® processor 1993 3,100,000

Pentium II processor 1997 7,500,000

Pentium III processor 1999 24,000,000

Pentium 4 processor 2000 42,000,000

P. P. Gelsinger, “Microprocessor for the New Millennium: Challenges, Opportunities, and New Frontiers,” Dig. Tech. 2001 ISSCC, San Francisco, pp.22-23, February, 2001

Microprocessors Trend

Today: 2002 (Intel)

Lg sub-70 nm

Tox 1.4 nm

f 2.53 GHz

P several 10 W

2008 (Intel)

Lg sub-25 nm

Tox 0.7 nm

f 30 GHz

P 10 kW

N 1.8B

Heat Generation

2002 年　　 10W/cm2 Hot Plate

2006 年　　 100W/cm2 Nuclear Reactor

2010 年　　 1000W/cm2 Rocket Nozzle

2016 年　　 10000W/cm2 Sun Surface

MIPS 1M MIPS (TIPS)

Past: 1972 (Intel)

Lg 10,000 nm

Tox 1200 nm

f 0.00075 GHz

(75 kHz)

Thus, supply voltage reductionand thuslow voltage technology will be very important

2. Current downscale scheme and its problems

Downscaling merit

Drive current

Power per chip

Integration (# of Tr)

Scaling K

Id = vsatWgCo (Vg-Vth)

N

K-1K2K (K-1 )2=

Switching speed KK/K= K

Id per unit Wg = Id / Wg= 1

Wg (tox –1)(Vg-Vth)= Wgtox

-1(Vg-Vth)= KK-1K=Kin saturation

Co: gate C per unit area

Cg = ooxLgWg/tox

Id per unit Wg

Clock frequency

K

1

Id

K

Id/m

f 1/K f = 1/K

N /K2

P

Gate capacitance Cg K

Chip area Achip

Lg, Wg

Tox, Vd

Geometry &Supply voltage

K

KK/K = K

= CgVd/Id

Scaling

K2

fNCV2/2

What will be real Downscaling ?

Lg, Wg, tox, Vd K?

K?Id

K?

f 1/K?

N /K2? P

1?Id/m

K?Cg

Achip

Is K the same for all the parameters?

Past downscaling trend

10 -3

10 -2

10 -1

10 0

10 1

10 2

1970 1980 1990 2000

MPU Lg (m)X

j (m)

Minimum logic Vdd (V)

Id/m(mA/m)

tox (m)

10 -3

10 -1

10 1

10 3

1970 1980 1990 2000

chip size （ mm2 ）

Number of tr

ansistors

（Mtra

nsistors

）power (W

)

MIP

Sclock frequency (MHz)

Id/m

Id

1 101

10-1K (10 –2) f 1/K(10 2) 103

P 10 1) 105

N /K2(10 5) 104Achip 101

Change in 30 years

Lg K 10 -2

tox K(10 –2) 10-2

Vd K(10 –2) 10-1

Idealscaling

RealChange

Idealscaling

RealChange

Idealscaling

RealChange

= fNCV2

Past 30 years scaling

N, f increaseMerit:

Demerit: P increase

Vd scaling insufficient

Additional significant increase in Id, f, P

Experimental data taken from conferences (Lg-Ion)

Year

8000 3000 2000 100 101000Lg(nm)

10 -2

10 -1

10 0

1970 1980 1990 2000 2010 2020

I on (

mA

/

m)

Toshiba’94’(IEDM94)

Lucent’99(IEDM)

IBM ’99 (SOI)(IEDM99)

30

2030

NEC’ 99 (EJ-MOSFET (SSDM))：　with ITRS scaling parameters (almost)

：　thicker gate insulator than ITRS

Intel’01(Si Nanoelectronics)

Toshiba’93(IEDM)

AMD’01(VLSI)Intel’00(IEDM)

LETI’00 (SSDM)Past tre

nd(Toshiba a

nd others)

ITRS’01

AMD’01(IEDM)

Intel’01(Press)

2040

Toshiba’96(IEDM)

Intel’01(IEDM)

1

IBM’02: PMOS(IEDM)

B. Doris et al., “Extreme scaling with ultra-thin SOI channel MOSFETs”, IEDM Tech., Dig., pp.267 - 270, San Francisco, December, 2002

6nm gate length p-MOSFET

Possible causes for smaller Ion

1. Non-optimized MOSFET structure/parameters

1a. Higher Vth to prevent SHE and to secure good Ioff

1b. Larger S/D extension resistance

Solution: Channel engineering

Solution: S/D engineering

2. Possible mobility degradation for ultra-thin gate dielectrics

Solution: mobility enhancement technique

+ maybe Gate electrode FB engineering

3. Examples of expected difficulties and some solutions

SHE suppression for Zero threshold voltage

Difficulty in halofor small dimension

Better for retrograde Non-doped Si epi-channel

Zero VthLow channel doping Difficult for SCE suppression

Retrograde is better

Another choice is gate electrode fb control

T. Ohguro et al., Symp. on VLSI Tech., pp.21-22, June, 1995

halo

S D

Halo will be overlapped.

T. Ghani et al., Symp. on VLSI, p.174, June, 2000

Gate　leakage　current　density　vs.　Tox　equivalent.

DielectricConstant

3.9 SiO2

~7 Si3N4

5 ~ 6 Si3N4/SiO2 (NO) Stack

~10 Al2O3

10 ~ 20 ZrSixOy, HfSixOy, LaSixOy (Silicate)

ZrAlxOy, ZrNxOy, (Alminate, Nitride)

15 ~ 30 ZrO2, HfO2, La2O3, Pr2O3, Gd2O3,Y2O3

~ 30 Crystal Pr2O3

Dielectrics

High-k Gate Dielectric Candidates

The reason why high-k gate insulator films increase short-channel effects

In　case　of　high-k,　　lateral　electric　fields　　are　strong　in　high-k　insulator.

(a) In case of SiO2

(b) In　case　of　high-k

Gate

DrainSource

Substrate

ε r =　3.9

Gate

DrainSource

Substrate

ε r =　3.9

DrainSource

Substrate

Gateε r =　390

-2 0 2 40

0.01

0.02

0.03

0.04

0.05

r = 390 Vth=

-1.35V

I d　

(mA

)

Vg 　 (V)

Lg =0.04μm

Vd =　0.1V

EOT　=　2nm

Short channel effects in case of using high-k meterials

r = 3.9

Vth= 0.4V

Simulated Results

VLSI　2001 IEDM2001 IWGI2001 VLSI　2002

Reported High-k Materials other than Si3N4

HfO2

ZrO2

Al2O3

AlN

Hf-silicate

AlTiOLa2O3

Pr2O

3

Zr-silicate

Ta2O5

HfO2HfO2HfO2

ZrO2

Zr-silicate HfAlO

ZrO2

ZrONZr-silicate

Al2O3ZrAlOZrONZrO2

HfONHfAlOHfSiON

Al2O3

Lanthanoide　Oxide(Nd2O3,Sm2O3,Gd2O3,　Dy2O3)

HfSiON

SiN

20

10

(From　Advanced　Program)

(1)Interfacial layer formation (2)Micro crystal growth(3)Lateral oxidation at gate edge (4)Lower mobility(5)Fixed charge, Flatband shift (6)Higher density of interface states(7)Boron penetration(8)Contamination from precursor for CVD

Problems in High-k

Interfacial Layer Growth, Micro Crystal Growth, Lateral oxidation

Si　Substrate

Interfacial　Layer

ZrO2

Sub-oxideHfO2

Poly-Si

Si Substrate

Interfacial Layer Growth, Micro Crystal Growth

Lateral oxidation

Yudong Kim et al., IEDM Tech. Dig., pp.455-658, 2001

Ohshima et al., The Japan Society of Applied Physics (The 62nd Autumn Meeting, 2001), P.632

Mobility Degradation

E.P Gusev et al., IEDM Tech. Dig., pp.451-454, 2001

Atomic Layer Deposition of HfO2

HfCl4　(g)

HfO2　

HfCl4　+　2H2O(g)　→　HfO2　+　4HCl(g)

Involvement of Cl in HfO2

ITRS2001 for Gate Dielectric

Al

La2O3

Si

Cross-sectional　TEM　image

t phys = ZnmEOT = 0.6nm

EOT vs. Leakage Current

10-10

10-6

10-2

102

0.5 1.0 1.5

La2O3

Lu2O3

Dy2O3

Pr2O3

Gd2O3

EOT (nm)

Reported Data

Cur

rent

Den

sity

(A

/cm

2 )

|Vg| = 1 (V)

HfO2NH3+HfO2HfSiONAl2O3+HfO2ZrO2Zr-SilicateNH3+ZrO2Al2O3Zr-Al-Si-OPr2O3Nd2O3Sm2O3Gd2O3Dy2O3La2O3Ta2O5SiO2Nitrided SiO2

Reported DataThis Work

Poly Si

Gate SiO2

Depletionlayer

Inversionlayer

Depletion layer

Gate SiO2

Inversionlayer

Positive bias

Effective thickness

Poly Si

Gate SiO2

Depletionlayer

Inversionlayer

Depletion layer

Gate SiO2

Inversionlayer

Positive bias

Effective thickness

Depletion　 in　 poly-Si　 gate　 and　 Inversion　capacitance

Problems in Shallow Junction

Rch Rsw

Rsd

Rcon

Rmm

M. Koyanagi., IWJT Abst., pp. 1-6, 2000

(1) Higher resistance in extension region(2) Shallow doping method(3) Re-distribution during activation annealing

0

500

1000

1500

2000

0 20 40 60 80 100

B+RTAB+SpikeBF2+RTABF2+SpikeGILD or LTASPESiGe S/DLTPB+LTPPLAD SPEPLAD RTP

She

et R

esis

tanc

e (

/sq)

Junction Depth (nm)

D.Lenoble et al., IWJT Abst., pp.29-34, 2001M.C.Ozturk et al., IWJT Abst., pp.77-82, 2001C.Laviron et al., IWJT Abst., pp.91-94, 2001Bin.Yu et al., IEDM Tech. Dig., pp.509-512, 1999

: :

SiGe SiGe

Comparison of ITRS and Published Shallow Junction Data

ITRS’99

ITRS’01

C.Laviron et al., IWJT Abst., pp. 91-94, 2001

0 -1.5 -2.0

100

200

300

400

500

00 -1.5 -2.0

100

200

300

400

500

Ser

ies

resi

stan

ce [

-m

]

Vg [V]

0

SPDD

LDD

S4D

GATE

Leff

SiN Spacer Silicided Si-Sidewall

TiSi2

Source Drain

Si

GATE

Leff

SiN Spacer Silicided Si-Sidewall

TiSi2

Source Drain

Si

T. Yoshitomi et al., VLSI Tech. Dig., pp.11-12, 1995

Raised Source/Drain at Extension

・ Small narrow line effect

・ Low contact resistance both for p- and n-silicon

・ Low sheet resistance

・ Low silicon consumption during silicidation

・ Low film mechanical-stress on silicon

・ High solubility of B for SiGe poly gate

・ Low silicidation temperature

Salicide: Why NiSi

Comparison of TiSi2, CoSi2 and NiSi

Preamorphization

As I/I

Ti silicide

s [

/sq

.]

1

10

100

1000

0.1 1.0

TiSi2 (Conventional process)

CoSi2NiSi

Line width [µm]10.0

TiSi2 (Pre-amorphization)

0.1 m

Agglomeration

CoSi2 NiSi TiSi2

Comparison of NiSi and CoSi2 (Id-Vd, Id-Vg)

Qi Xiang et al., Symp. on VLSI Tech., pp76-77 (2000)

Mobility Enhancement by Strained Channel

S. Takagi et al., Symp. on VLSI Tech. Dig., pp.210-211, 2000

1

10

100

2005 2010 2015year

tSi-P

tSi-F

Lg, tBOX-FXj

nm

tSi-P Silicon final device layer thickness (Partial Depleted)

tSi-F Silicon final device layer thickness (Fully Depleted)

tBOX-F Buried oxide (BOX) thickness (Fully Depleted)

Xj Drain extension

Lg MPU Physical gate length (nm)

SOI

Sub 70nm

Node 65 nm25 nm

Lg

25 nm9 nm

tSi-P

50.5 nm18.5 nm

tSi-F

10.5 nm4 nm

tBOX-F

20 nm9 nm

Xj

13.5 nm5 nm

Si

BOX

Si tSi-F Xj

tBOX-F

Partial depleted Fully depleted

Problems of fully depleted for downsizing

SCE suppression tSi-F, tBOX-F thin

•Mobility degradation

•S/D extension R increase

4. Summary and Conclusions

There should be more than several roadmaps depending on applications

Challenge(Unknown )

Ultimate limit

Development(for production)

Research(Tr confirmed)

Production 100 nm

Year2000 05 10 15 20

0.3 nm

30 40 50

10 nm

20 nm30 nm60 nm

Lg

High perform

ance

Low power

Mobile, low cost

6 nm3 nm

1 nm

0.6 nm

2 nm

(Atom distance)

Problems of downsizing will be solved by introducing new materials, structures, and processes.

It’s too early to give up silicon device.

Si devices are the smallest devices currently available in the market, and there is no other candidates smaller than Si in future as well.

1M 4M 16M 64M 256M 1G

BL

WL

Cell Plate

Planar

STC I STC IICylinder Multi-Cylinder (+COB) High

High film

Stack

Trench Trench

Sub. Plate

Stack Trench SOI/Trench ?

Generation

Fin Multi-Fin

CellStructure

HSG(COB)HSG(COB)

Higher aspect ratio

4G　 ～Cylinder Pedestal

Buried Strap

Fig. 33 : DRAM cell structure change.

　

G a t e in s u la t o rS iO 2 S iO x N y

S i 3 N 4 , A l 2 O 3 , T a 2 O 5 , T iO 2 , Z r O 2 , H f O 2 , Y 2 O 3 , L a 2 O 3 , G d 2 O 3 , S c 2 O 3 , ( Z r , H f , L a , T i ) - S iO 4 , L a A lO 3 , Z r T i O 4 , ( Z r , S n ) T i O 4 , S r Z r O 4 , L a A l 3 O 4 , B a Z r O 3 , S r B i 2 T a 2 O 9 , P b ( Z r ,T i ) O 3

I n t e r c o n n e c tA l , A l - S i , A l - S i - C u , A l - C u W , T iN

C u , W , A l - C uT a , T a N , T a S iN , T iN ,W N , W S iN , C o P , C o W PS i 3 N 4

I n t e r la y e r

S iO 2 , S iB x P y O z , S iP y O z

S i 3 N 4

( S iO 2 ) x ( S iO 3 F 2 ) 1 - x , S iO 1 .5 H 0 .5 , C , S iO 1 .5 ( C H 3 ) 0 .5 , a - C : F , ( C F 2 C F 2 ) n

x

O

OO

O F 3 CO

O

O

O

C F 3

1 - x

O C F 3

F 3 C ON N

yN N

1 - yx

O

OO

O F 3 CO

O

O

O

O

O

C F 3

1 - x

O C F 3

F 3 C ON N

O C F 3

F 3 C ON N

yN N

1 - y

C O

C O

C O

C ON N

n

C O

C O

C O

C ON N

n nC F 2

C F 2

nC F 2

C F 2

P o ly im id e P a r y le n e - N

nC F 2

C F 2

nC F 2

C F 2

P a r y le n e - F

S i

C H 3

S iOC H 3

C H 3

C H 3

S i

C H 3

S iOC H 3

C H 3

C H 3

B C B F lu o r in a t e d p o ly im id e

S /DP , A s , B , T iS i 2 C o S i 2

P , A s , S b , B , G a C o S i 2 N iS i

G a t e E le c t r o d eS i , M o S i 2 , W S i 2 , T iS i 2 , C o S i 2

S i , S iG e , C o S i 2 , N iS i , T a , Z r , H f , T i , T a N , W N , P t , I r , N i

　

Fig. 41 : Various new materials to be considered for future ULSI.

From now, not only the downsizing, but also integration of many different functional sub-chips on a silicon chip will become very important.

Questions for sub-10 nm CMOS

Transistor operation was confirmed. Transistor level:

Drain current was not sufficiently high.

Integration level:

Chip performance?

Cost?

Reliability and yield?Power consumption and heat generation?

Limiting factors

Power consumption and heat generation?

No direct limit for downsizing

1. Low supply voltage, and high-k, low-k, junction tech.

2. CAD , New system architecture, New Algorism

If no suppression of power, then wait!

Let us suppress the performance!

New technology development will solve to certain level.

Mosquito!

Cost?

No direct limit for downsizing

Tremendous increase in R&D and production cost.

If no suppression of cost, then wait!

Let us suppress the performance and integration!

Alliance between companies for production.Solution:

Collaboration of industry, academia, government.

Resource for Money, Human, Land

Progress of Passenger Airplane Speed

10

100

1,000

10,000

1900 1920 1940 1960 1980 2000

Spe

ed o

f pas

seng

er a

irpla

ne　

[ km

/ h

]

Year

Velocity of Sound

Concorde

B747

CometⅠ

DC-3

Wright Brothers

More than 100 billion stars are involved

100 Gbit DRAM is the Galaxy.

DRAM trend already began to slow downFrom 1Gbit generation.

Progress of Large Ship Tonnage

10

To

nn

age

Year1850 1900 1950 2000

Wood

Ferric

Queen Marry

Queen Elizabeth

Idemitsu-maru

Nisseki-maru

Steel Oil TankerGross

tonn

age

Weig

ht

tonn

age

Great Eastern Gross

tonn

age

6

105

104

103

Grenoble, MINATECH

State University of New York, Albany

NTL, Taiwan KAIST, Korea

Huge facilities in universities under schedule in 2 years

Area:1000-3000 m2

Budget: 100 – 300 Euro/USD

300 mm wafer

Reliability and Yield?

No direct limit for downsizing

Particle, defects, Hot carrier, ESD affects on

Smaller geometry, and thinner film, New material, complicated structure (3D)?

Hard breakdown, or hard failure is reducing forThinner film, because of tunneling leakage. (bypass)

Failsafe design in system side is in progress

Concerns

Process induced damage: ion-implantation for S/D

64k DRAM: 1980

By ESD, gate oxide wasbroken down

Performance will limit?

Maybe or may not be around at 10 nm.

If limit in downsizing, Then, consider to increase the performance by other method.

Chip embedded chip (CEC) Tech

Solution:

More intelligent system architecture, algorism.

Performance will limit?

Maybe or may not be around at 10 nm.

8000 3000 2000 100 101000Lg(nm)

10 -2

10 -1

10 0

1970 1980 1990 2000 2010 2020

I on(m

A/

m

)

Toshiba’94’(IEDM94)

Lucent’99(IEDM)

IBM ’99 (SOI)(IEDM99)

30

2030

NEC’ 99 (EJ-MOSFET (SSDM))：with ITRS scaling parameters (almost)

： thicker gate insulator than ITRS

Intel’01(Si Nanoelectronics)

Toshiba’93(IEDM)

AMD’01(VLSI)Intel’00(IEDM)

LETI’00 (SSDM)Past tre

nd(Toshiba a

nd others)

ITRS’01

AMD’01(IEDM)

Intel’01(Press)

2040

Toshiba’96(IEDM)

Intel’01(IEDM)

1

IBM’02: PMOS(IEDM)

8000 3000 2000 100 101000Lg(nm)

10 -210 -2

10 -110 -1

10 010 0

1970 1980 1990 2000 2010 2020

I on(m

A/

m

)

Toshiba’94’(IEDM94)

Lucent’99(IEDM)

IBM ’99 (SOI)(IEDM99)

30

2030

NEC’ 99 (EJ-MOSFET (SSDM))：with ITRS scaling parameters (almost)

： thicker gate insulator than ITRS

Intel’01(Si Nanoelectronics)

Toshiba’93(IEDM)

AMD’01(VLSI)Intel’00(IEDM)

LETI’00 (SSDM)Past tre

nd(Toshiba a

nd others)

ITRS’01

AMD’01(IEDM)

Intel’01(Press)

2040

Toshiba’96(IEDM)

Intel’01(IEDM)

1

IBM’02: PMOS(IEDM)

Progress of Passenger Airplane Speed

10

100

1,000

10,000

1900 1920 1940 1960 1980 2000

Spe

ed o

f pas

seng

er a

irpla

ne　

[ km

/ h

]

Year

Velocity of Sound

Concorde

B747

CometⅠ

DC-3

Wright Brothers

Test

Test

Test

client

Interconnects

Complete

DRAM

Microprocessor

Flash

SRAMDSP

Analog 　 RFSensor

Photo DetectorLaser

Chip　embedded　chip(CEC)　technology　for　SOC.

Integration of different functional chip on a chip becomes important

Brain Ultra small volumeSmall number of neuron cellsExtremely low power

Real time image processing

(Artificial) Intelligence

3D flight control

Sensor

InfraredHumidity

CO2

Mosquito

CMOS is the smallest device among othercandidates.

Production: Lg = sub 100 nm, tox = 1.4 nm

Research: Lg = 6 nm, tox = 0.7nm

If CMOS faces the downsizing limit,other devices will also face the limit at thesame size or even larger size.

30 years ago: Production: tox = 100 nm

I have been participate in ‘NANO TECH’ for30 years, and now move to PICO TECH.

Lg = 6nm is the length of only 20 Si atoms

Tox = 0.7 nm is only the length of 2 Si atoms

Thus, the downsizing limit is not very far.

Regardless of the downsizing limit, Si CMOSwill be the main device at least for 50 years.

Integration of other functional chips on the Si will be more importnt.

Conclusion

Downscaling of Si devices hasbeen accelerated every year .

Problems of downscaling will be solved by introduction of new materialsstructures and processes.

Chip　integration　

Downsizing

Previous

From

　Now

Nano　area

10 nm

Research Trend

Integration of different multi-functional sub-chip on a Si chip becomes important from now.

Now Nano or Pico CMOS is within the project range of near future research.