A Four Function Arithmetic Logic Unit

A Four Function Arithmetic Logic Unit

EE 365 Project 2

10-28-2004

Chris Ouellette

Joshua Smith

Table of Contents3I.Objective

4II.Approach

4III.Functional Design

4A.Inverter

5B.AND

5C.OR

6D.XOR

7E.Multiplexer

9F.Arithmetic Logic Unit, 1-bit width

11IV.Timing Considerations

11A.Timing Delay Research

12B.Verification of Design

12V.Further Design Timing Testing

14VI.Conclusions

15VII.Future Design

Table of Figures

3Figure 1 - 1-bit ALU Design

5Figure 2 - Inverter Timing Analysis

6Figure 3 - AND Timing Analysis

7Figure 4 - OR Timing Analysis

8Figure 5 - XOR Timing Analysis

9Figure 6 - MUX Timing Analysis (Dataflow)

9Figure 7 - MUX Timing Analysis (Behavioral)

10Figure 8 - 1-bit ALU Architecture Design

11Figure 9 - 1-bit ALU Timing Analysis

13Figure 10 - 1-bit ALU, with delay considerations

13Figure 11 - 1-bit ALU output error

14Figure 12 - 1-bit ALU, inputs constant

15Figure 13 - 1-bit ALU, select bits constant

Table of Tables4Table 1 - Inverter Truth Table

5Table 2 - AND Truth Table

6Table 3 - OR Truth Table

7Table 4 - XOR Truth Table

8Table 5 - MUX Truth Table

11Table 6 - 1-bit ALU Truth Table

12Table 7 - Timing Delay Summary

I. Objective

This paper outlines the design and testing procedures of a four function Arithmetic Logic Unit (ALU) of 1-bit width. A design schematic is shown below:

Figure 1 - 1-bit ALU Design

The design has two inputs, A and B, and two select bits S1 and S0 to select between the four functions (AND, OR, XOR, NOT(A)). A multiplexer is utilized in selecting the appropriate output to pass through to the entity output, D.

This project will make use of various techniques of modeling circuits in VHDL including dataflow, behavioral, and structural languages. In specific, the AND gate is created using a concurrent conditional signal assignment, the OR is created with concurrent selected signal assignments, the XOR uses a process statement (behavioral code), and the inverter is written in dataflow. The 4:1 MUX was written in two ways, one using behavioral code, and the other using dataflow. These two architecture definitions will be tested independently to verify that they get the same results.

In addition to considering the functional accuracy of the design, timing delays will also be considered for the circuit to see how propagation delay might effect the accuracy of the circuit design. This analysis will be done as a worst case scenario, as the highest possibly timing delay for a given entity (i.e. AND) will be used, and will be used for both low to high and high to low signal transitions.II. Approach

The design and test will be done in two parts. In the first part, each component of the logic network will be designed and tested individually and as a whole, without considering timing delays. After the ALU has been verified for accuracy by comparison between expected values and truth tables, then timing delay will be added to the VHDL code and the design will be re-tested to see the impact of the propagation delay on the output from the ALU.Each component is tested in detail because of new design techniques being tested in this paper. By verifying that each component works as expected, a greater certainty can be placed on the conclusion that the ALU as a whole works after testing.

III. Functional Design

A. Inverter

The inverter is a gate that simply negates the value of its input. Below is the truth table for the inverter.

InputOutput

01

10

Table 1 - Inverter Truth TableAs you can see from the truth table the output is negated meaning that an input of 1 becomes and output of 0 and visa versa. The VHDL was written in dataflow language. This can be seen in the appendix. Below is the timing diagram of this gate. Since there are only two possible states for this gate (input high or input low), all possible states are tested:

Figure 2 - Inverter Timing Analysis

This figure has a 1-to-1 correspondence with the truth table. When the input is low, the output is high, and vice versa. This leads us to believe that the inverter is functioning correctly and can be incorporated into higher level designs. B. AND

The AND gate is a little more complex then the inverter in that it compares two bits together and based on the bits outputs a 1 or a 0. Below is the truth table of an AND gate.

Input(1)Input(0)Output

000

010

100

111

Table 2 - AND Truth TableFrom the truth table we can see that the output is only 1 when the inputs are both 1. The AND gate was written using concurrent conditional signal assignment statements within the architecture. Conditional signal assignment is similar to the if statement in C++. In the case of the and gate, if both of the inputs are 1 then the output is 1, otherwise the output is 0. Below is the timing diagram for the AND gate.

Figure 3 - AND Timing Analysis

The timing diagram shows a 1-to-1 correspondence between the signal high and low logic levels and the truth table presented. This leads us to believe that the conditional signal assignment code was properly constructed to model an AND gate.C. ORThe OR gate works such that when either input is 1 the output is 1. This gate was written using concurrent selected signal assignment statements. The selected signal assignments are similar to a switch in C++. That is one signal is chosen as a switch and then outputs are assigned for each input. Usually the inputs of interest are listed and assigned output values and a different value is assigned when others. The truth table and timing diagram for an OR gate are given below.

Input(1)Input(0)Output

000

011

101

111

Table 3 - OR Truth TableThe timing diagram follows displaying high and low logic levels for the OR gate designed using selected signal assignments.

Figure 4 - OR Timing AnalysisBy comparing the logic levels displayed in the timing diagram and the OR gate truth table we can see that there is a 1-to-1 correspondence between the two. This leads us to believe that the OR gate was correctly represented using the selected-signal assignment statement.D. XOR

The XOR gate is an inequality tester. If the input values are not equal than it outputs a 1. This component was written using a process statement. The process statement can be used anywhere a concurrent statement can be used. It has two states. One is when the process is running where it is evaluating the expressions within it or it can be suspended. That is, when the signals listed in the sensitivity list change their value, the process wakes up and re-evaluates its outputs. In the case of the XOR gate both inputs must be in the sensitivity list because one case will be left out if only one input is listed. For example, using the table below, if input(1) were listed and not input(0), if input(1) was held high as input(0) changed from high to low, the output would remain zero because the process would not wake-up during this change. However, if input(1) change from high to low while input(0) was held high, this design (as stated) would accurately reflect the change. Thus, to account for all cases, both inputs must be listed in the sensitivity list. Below is the truth table for the XOR gate.

Input(1)Input(0)Output

000

011

101

110

Table 4 - XOR Truth TableThe timing diagram for the XOR gate is shown below:

Figure 5 - XOR Timing AnalysisThe timing diagram shows a 1-to-1 correspondence of cases between the truth table and its logic levels. This leads us to believe that the XOR was properly designed using the process statement.E. Multiplexer

A mux works like a routing device. If a particular input is desired to be passed through to the output the 4:1 mux in this design uses two select bits (S) to choose that input. The mux has been written in two different ways. One is using a data flow technique, case-select (similar to a switch). This lists a series of possible cases that the select bits can be, and assigns an output based on the select bits. This assignment can be arbitrary. The way we chose to order assignment for this project is shown in the truth table below.

S(1)S(0)Input to Select

00C(0) - AND

01C(1) -OR

10C(2) - XOR

11C(3) -NOT

Table 5 - MUX Truth TableThe second way that it was written in was using a case statement within a process statement. The case statement just works like it sounds. It will make the output be a specified value when a certain case is met. Again if the select bits are 00 then make the output A.

Testing the design of the 4:1 mux is more difficult than testing the design of simple 2-input gates because there is a greater number of possibilities for inputs: two select bits and four input bits create a large amount of possible combinations. However, a few representative cases have been developed. We hope these cases show possible situations where the MUX design could fail, and show its correct representation of output. The same inputs were given to both designs to cross check the output, since they should be functionally the same.

Figure 6 - MUX Timing Analysis (Dataflow)

Figure 7 - MUX Timing Analysis (Behavioral)

Comparing these timing diagrams we can see that there is a 1-to-1 correspondence between the two, meaning that for the cases listed they are functionally the same. Consider one of the timing diagrams. In the first case, the select bits are 00 meaning to pass through input C(0). This input is 1 in this case, therefore output d is 1. Note that the order of the bits is C(3) is the MSB and C(0) is the LSB. The second and fifth cases confirm this order of significance. The other cases confirm that the output of the 4:1 mux is the selected input bit of C passed through to D. This leads us to believe that the mux is functioning correctly, for both architectures.

F. Arithmetic Logic Unit, 1-bit width

The goal of this part of the project is to develop and test a functional ALU as described in Part I. Thus far, we have shown the process we have used for developing parts to be used in the ALU. In this part, the parts are integrated through structural language in VHDL by instantiating each part and then mapping the ports together with appropriate wires needed for connections. Slightly modifying the original schematic, the following diagram shows how the ALU was wired together, including new signal names:

Figure 8 - 1-bit ALU Architecture Design

Since there are only 4 inputs to this logic network, it is relatively easy to do a brute force test of the logic network, testing and verifying every combination (16 combinations). Below is a summary truth table of the possible inputs and outputs of the logic network.ABS1S0D

00000

00010

00100

00111

10000

10011

10101

10110

01000

01011

01101

01111

11001

11011

11100

11110

Table 6 - 1-bit ALU Truth Table

The outputs in this table were determined by considering the logic network, and the input being selected for pass through by the mux. The input values for A, B, S1, and S0 were used in the testbench. The timing diagram for the testbench is shown below.

Figure 9 - 1-bit ALU Timing Analysis

Comparing the expected output values for each of the inputs in the table and the timing diagram, we see a 1-to-1 correspondence. Since each component that the ALU consists of was tested and verified individually before being incorporated into the ALU, we believe that the correct outputs from the ALU are proof that the design of the ALU is correct as described in the project description.IV. Timing Considerations

In the last section of this report we considered only the functional design and test of a 1-bit wide ALU. However, this design did not account for timing delays inherent in real-world circuits. In this section we will add timing consideration to our logic design and re-test the ALU to see the impact of the timing propagation delay, if any.A. Timing Delay ResearchIn order to add timing delays to our logic network, assumptions needed to be made regarding each of the circuits logic networks/gates. We have assumed for simplicity a worst-case scenario where the propagation delay for each of the gates and the mux is tpd=max(tpHL,tpLH). Information for each of the components was found at www.ti.com.

Device:Use timing for:tpd (ns)

AND gate74F086.6

OR gate74ALS3214

XOR gate74LS8630

Inverter74LS0415

4:1 Mux74ALS15321

Table 7 - Timing Delay SummaryB. Verification of DesignUsing the timings from the above section and applying them to the components of the ALU we will be able to verify that the design is also correct with timing considerations included. This means that the design takes into account the propagation delays from the components such that there is no overlapping of signal changes. Below is a timing diagram showing the errors that occur when the timing delays are taken into account. In this case, the wait period of the ModelSim test bench was 10ns, causing the inputs to change every 10ns. Since it takes significantly longer for the outputs to change because of propagation delay, the wait period needs to be set to a longer length. Below is a timing plot example of the errors encountered when the wait period is 10ns.

Figure 10 - 1-bit ALU, with delay considerationsAs has been highlighted in the timing diagram, there was an error with the circuit. No output was displayed until after over 110ns because of the timing delay. We will need to consider the worst case scenario for the wait period time so that the output will correctly reflect the inputs as the inputs and select bits change. However, it is still possible that if inputs and select bits are changing simultaneously that an error can occur, as described below.V. Further Design Timing Testing

In the project specification, the output of the circuit for the following conditions were asked to run the timing simulation of our circuit for the following conditions: At t = 0 ns: S1 = 0, S0 = 0, A = 0, B = 1 and At t = 100 ns: S1 = 1, S0 = 0, A = 0, B = 0. This was done by setting the PERIOD in the testbench for the ALU to 100ns, and then having the inputs change as specified. Below is a timing diagram of the output of this test.

Figure 11 - 1-bit ALU output error

There is a couple interesting features to this timing diagram. First, notice the U value for the output for t=0 to t=28ns. This delay in the output is caused by the fact that for the signal to go through the AND gate (6.6ns) and then through the MUX (21ns) it takes approximately 28ns from the time the signals were first asserted. The second part of interest is the errornous blip after the w_s goes to 10 from 00 and B=1. During this time interval, the output should be 0 because 0 XOR 0 is 0. This blip is caused by propagation delay. This blip occurs because of the differences in timing delays of the different inputs to the MUX, and the delay of the MUX itself. At t=100ns, both inputs and select bits are changed. This becomes time zero for the transition of the MUX inputs, and for the MUX to change which input it is selecting. The input that the MUX is changing to select is the XOR, the delay from the time that the select bits change to when that input becomes the output is 21ns. This coincides with the time that the output signal goes high (when it shouldnt). Since the signal from the XOR is still 0 XOR 1, the output is high. After another 9ns, the XOR has finished evaluating the new input and its output of 0 is passed to the now currently selected input of the MUX (a total of 30ns has elapsed since the inputs and select bits changed). Now there is another delay period because it takes the MUX 21ns to transition its current high state to a low state as dictated by the XOR. This occurs at time 151ns, or 51ns after the initial transition took place. After this time has passed, the correct logic output (0) is output from the circuit.

This is the hazard of the circuit design as it is: when both the input and select bits are changed at the same time there exists a possibility for the output of the circuit to change to a value that was not intended while all of the internal components reach their new logic state.

It is interesting also to look at the timing diagrams for cycling through all the possible values for the input bits. This is shown below in two different scenarios. In the first scenario, the select bits cycle through 4 possible values while the inputs remain constant and the select bits remain constant while the input values are varied.

Figure 12 - 1-bit ALU, inputs constantThe diagram shows that if the select bits and the input bits are not changed at the same time the correct values for the circuit can be obtained. For example, with A=0 and B=1, S=00 (AND) is 0, S=01 (OR) is 1, S=10 (XOR) is 1, and S=11 (NOT A) is 0. Note that while the outputs are as expected, they are still slightly delayed from when the select bits changed.

Below is the second scenario where the inputs are varied and the select bits are held constant.

Figure 13 - 1-bit ALU, select bits constantThis diagram shows that the circuit can also handle the changing of the inputs without running into any errors. Note again the delay that exists when the output needs to change.Observing the fact that there were problems with extraneous output in the circuit, extra caution would need to be taken with the design if input and select bits were to change at the same time. If this were the case, the situation should be analyzed functionally (as it was described in this section) and also should be simulated for verification. VI. Conclusions

In this project we have used various modeling techniques in VHDL to create a 1-bit wide four function Arithmetic Logic Unit. We developed and tested the design functionally first and then tested the design with consideration to timing (propagation of delay). The functionality of the circuit encountered no errors during simulation. Timing delays were considered which resulted in some erratic behavior. However, this behavior was easily analyzed and as the circuit is designed this output is expected. This was due to inputs switching too late or the mux switching too early, meaning that the correct values could not be output/evaluated within the time allotted. This fact is the most significant part of the design of this circuit. Knowing that the delay of the circuit will cause problems we can design ways to fix the problems that occur because of the inherent delays of each of the components.

VII. Future Design

The functionality and issues associated with the design proposed have been analyzed. Since there are issues with inputs and the ALU function changing simultaneously, adding a synchronous element to the circuit in order to control the flow of input signals could prevent some of the problems associated with the design._1124792556.vsdMultiplexer

S1S4

D

C2

C1

ENB

1

Multiplexer

A

B

S1

S0

D

C0C1C2C3

S1 S0