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JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.2, APRIL, 2014 http://dx.doi.org/10.5573/JSTS.2014.14.2.235
Manuscript received Nov. 27, 2013; accepted Feb. 22, 2014
Department of Electrical, Electronic, and Computer Engineering,
Sungkyunkwan University, Suwon 440-746, Korea.
D. Heo is with Electrical Engineering and Computer Science
Department, Washington State University, Pullman, WA 99164 USA.
E-mail : [email protected]
A CMOS Envelope Tracking Power Amplifier for LTE
Mobile Applications
Junghyun Ham1, Haeryun Jung
1, Hyungchul Kim
1, Wonseob Lim
1,
Deukhyoun Heo2, and Youngoo Yang
1
Abstract—This paper presents an envelope tracking
power amplifier using a standard CMOS process for
the 3GPP long-term evolution transmitters. An
efficiency of the CMOS power amplifier for the
modulated signals can be improved using a highly
efficient and wideband CMOS bias modulator. The
CMOS PA is based on a two-stage differential
common-source structure for high gain and large
voltage swing. The bias modulator is based on a
hybrid buck converter which consists of a linear stage
and a switching stage. The dynamic load condition
according to the envelope signal level is taken into
account for the bias modulator design. By applying
the bias modulator to the power amplifier, an overall
efficiency of 41.7 % was achieved at an output power
of 24 dBm using the 16-QAM uplink LTE signal. It is
5.3 % points higher than that of the power amplifier
alone at the same output power and linearity.
Index Terms—Envelope tracking, power amplifier,
CMOS power amplifier, bias modulator, hybrid buck
converter, long term evolution
I. INTRODUCTION
Wireless communication systems have evolved with
more complex modulation techniques and wider signal
bandwidth for higher data rate. For the modulated signals
that have high peak-to-average ratio (PAPR) and wide
signal bandwidth, power amplifiers (PAs) are required to
operate on an output power back-off condition and to
comply with very stringent linearity specification. Such a
back-off operation in output power level significantly
degrades efficiency of the PA. Various techniques have
been studied to mitigate this efficiency degradation
problem [1-22].
Among several techniques, the envelope tracking (ET)
technique has been in great interest due to its high
efficiency and moderate linearity characteristics. A block
diagram of the ET PA is shown in Fig. 1(a). Basically,
ET PA consists of a PA and a bias modulator. The bias
modulator dynamically supplies the bias voltage to the
PA according to the envelope signal. Then, high
efficiency can be maintained even at significantly
backed-off output power levels from the peak power
level, as shown in Fig. 1(b).
Several bias modulators have been proposed for the
ET techniques. Low drop-out regulators and switching
regulators are not good choice for the bias modulator due
to low efficiency and narrow bandwidth, respectively [3,
4]. The hybrid bias modulators, which have a highly
efficient switching stage and a broadband linear stage,
have been popular for the ET applications [6-22]. The
switching stage supplies most of the current which are
around very low frequency including DC. The linear
stage supplies rest of the current to the PA as a drain bias.
The linear stage also compensates for the ripple current
from the switching stage.
Because of high efficiency and high power density
characteristics, compound processes, such as GaAs HBT
236 JUNGHYUN HAM et al : A CMOS ENVELOPE TRACKING POWER AMPLIFIER FOR LTE MOBILE APPLICATIONS
or SiGe BiCMOS, have been dominantly used to design
PAs for wireless communication applications. Therefore,
the bias modulators, which are generally designed using
CMOS process, have been generally applied to those PAs
using GaAs HBT or SiGe BiCMOS processes for higher
performance [13-20]. However, the PAs based on CMOS
process has great advantages in lower cost and higher
integration in spite of its relatively poor performances
[23-25].
In this paper, both PA and bias modulator are designed
and implemented using a standard 0.18-µm CMOS
process. The PA has a two-stage differential common-
source structure for obtaining sufficient gain and
applying ET technique. A hybrid buck converter for the
bias modulator, which consists of a linear stage and a
switching stage, is optimized for the dynamic load
condition according to the envelope level. The measured
performances of the CMOS ET PA will be presented and
compared to the previously published PAs with
efficiency enhancement methods.
II. CMOS POWER AMPLIFIER DESIGN
A schematic of the CMOS PA is depicted in Fig. 2(a).
For sufficient gain, the PA consists of two differential
stages which have common-source configuration. The
PA has off-chip transformers at input and output. Each
transformer has a loss of 0.2 dB at the operating
frequency of 0.78 GHz. The PA integrated circuit (IC)
was implemented using a Magnachip’s standard 0.18-µm
CMOS process. Its microphotograph is shown in Fig.
2(b). The size of the chip, including pads, is 0.84 X 0.59
mm2. The PA IC was mounted on a printed circuit board
(PCB) based on FR-4 for evaluation as shown in Fig.
2(c).
For the measurements of the gain and efficiency, a
0.78 GHz single-tone signal was applied to the PA with
various supply voltages from 3.3 to 0.5 V to the drain of
the 2nd stage. The 1st stage has a fixed bias of 3.3 V. As
shown in Fig. 3(a), a power gain of 27 dB and a power-
added efficiency (PAE) of 46 % were achieved at an
output power of 27 dBm with a drain bias of 3.3 V. As
decreasing the bias voltage from 3.3 to 0.5 V, peak
power levels drop but significant PAE improvement was
observed at the back-off region. The gain is still higher
(a)
(b)
Fig. 1. Envelope tracking power amplifier (a) block diagram,
(b) efficiency curves.
(a)
(b)
(c)
Fig. 2. The CMOS PA (a) schematic, (b) chip
microphotograph, (c) evaluation board.
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.2, APRIL, 2014 237
than 20 dB at a bias voltage of 0.5 V.
To measure the third-order inter-modulation distortion
(IMD3), a two-tone signal with a center frequency of
0.78 GHz and a tone-spacing of 5 MHz was excited. The
measured IMD3 performances with various bias voltages
to the drain of the 2nd stage are shown in Fig. 3(b).
According to the bias voltages, the output power,
satisfying an IMD3 of –30 dBc, drops as well. From
these measurement results, we can assign variable bias
voltages with respect to the input envelope signal for
maximum efficiency improvement while not generating
excessive nonlinearity.
III. BIAS MODULATOR DESIGN
The bias modulator which is based on a hybrid buck
converter consists of a wideband linear stage using a
class-AB buffer and a highly efficient switching stage, as
shown in Fig. 4. The variable output voltage of the bias
modulator is supplied to the drain of the PA’s 2nd stage.
Hence, the load condition of the bias modulator
dynamically changes according to the envelope signal.
To properly evaluate the bias modulator, applying the PA
as the load is the most accurate way. However, that needs
considerable computation time on simulation or is prone
to cause convergence error [15].
To save simulation time, we calculated a mean or
expected value of the load resistance of the bias
modulator using a probability density function (PDF) of
envelope signal. A dynamic load resistance for the bias
modulator can be extracted from the designed PA using
the bias voltage and current to the PA, as shown in Fig. 5.
The probability density function (PDF) of the envelope
signal for the 16-QAM LTE up-link with a signal
bandwidth of 5 MHz is also shown. As shown, the
resistance changes from 30 to 10 Ω depending on the
envelope voltage. And it looks relatively constant for the
envelope signal of more than 1.0 V. The expected load
resistance is calculated as follows.
(a)
(b)
Fig. 3. The measured performances of the PA IC with various
supply voltages to the drain of the second stage (a) power gain
and PAE, (b) IMD3.
Fig. 4. A circuit diagram of the bias modulator based on a
hybrid buck converter.
Fig. 5. A load resistance of the bias modulator extracted from
the designed PA and a PDF of the envelope signal for the 16-
QAM LTE up-link with a signal bandwidth of 5 MHz.
238 JUNGHYUN HAM et al : A CMOS ENVELOPE TRACKING POWER AMPLIFIER FOR LTE MOBILE APPLICATIONS
,max
,min
( ) ( ) ,env
env
V
Exp env PA env envV
R p V R V dV= ⋅∫ (1)
where p(x) is a PDF of x. RPA is a dynamic load
resistance extracted from the PA. As a result, the
calculated RExp of 11.8 Ω is obtained and used in design
of the bias modulator.
Since most of the current from the bias modulator to
the PA is supplied from the switching stage, the
efficiency of the switching stage is very important for the
overall efficiency of the bias modulator. Efficiency of the
switching stage is expressed as follows [21].
, ,/ ( ),sw out out loss FET loss indP P P Pη = + + (2)
where Pout is an output power of the switching stage,
Ploss,FET is a loss of the switch, and Ploss,ind is a loss of the
inductor. They are given by
2 ,out sw loadP I R= ⋅ (3)
2 2
, , ,
2 ,
loss FET cond sw source on p sink on n
sw tot DD
P P P I r I r
f C V
= + = ⋅ + ⋅
+ ⋅ ⋅ (4)
2
, ,loss ind sw DCRP I R= ⋅ (5)
where Isw is an output current of the switch and Rload is a
load resistance of the bias modulator. Pcond is a
conduction loss and Psw is a switching loss. Isource and Isink
are the sourcing and sinking current of the switch,
respectively. ron,p and ron,n are on-resistances of the
PMOS and NMOS of the switch. fsw is a switching
frequency and Ctot is a total input capacitance of the
switch. VDD is a supply voltage and RDCR is a DC-
resistance of the inductor.
Both the on-resistances and the total input capacitance
of the switch increase the switching loss. The switch size
needs to be optimized because the on-resistances and the
total input capacitance are inversely and directly
proportional to the switch size, respectively. For a load
resistance of 12 Ω and a switching frequency of 2 MHz,
the optimized switch size for efficiency is 20 mm X 0.3
µm and 10 mm X 0.35 µm for the PMOS and NMOS
FETs, respectively.
From [14] and [21], the switching frequency of the
hybrid bias modulator is given by
.
( ),
2
sen out DD out
sw
DD hys
R V V Vf
V NLV
−= (6)
where Rsen, VDD, N, L, and Vhys are a sense resistor, a
supply voltage, a current mirroring ratio, an inductance,
and a hysteresis of the comparator, respectively.
Inductance directly affects the switching frequency and
other parameters, such as the current loop bandwidth,
ripple voltage, and slew-rate of the switching stage.
Therefore, the inductance must be carefully optimized
for overall efficiency of the bias modulator [13, 14, 17].
To find an optimum value of the inductor, a number of
simulations have been carried out with various inductors
at the load of the switching stage. The resultant optimum
value of the inductance for the best efficiency and
acceptable level of ripple current is 5.8 µH.
The bias modulator was designed and fabricated using
a Magnachip’s 0.18-µm CMOS process. The fabricated
IC is shown in Fig. 6(a). The chip size is 1.55 X 0.7 mm2
including pads. The chip was mounted on FR-4 PCB, as
shown in Fig. 6(b), and tested with a supply voltage of
3.3 V for the 16-QAM up-link LTE signal with a signal
bandwidth of 5 MHz.
Fig. 7(a) shows the measured waveforms of the
envelope output voltage and the switch output voltage
with a load resistance of 12 Ω and an inductance of 5.8
µH for the 16- QAM LTE up-link signal with a signal
bandwidth of 5 MHz. The envelope output voltage was
shaped to have a range of from 0.5 to 3.2 V so that the
(a)
(b)
Fig. 6. The bias modulator (a) chip microphotograph, (b)
evaluation board.
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.2, APRIL, 2014 239
average output power of the bias modulator is 25.8 dBm.
Switching frequency is observed to be about 2.1 MHz
from the measured waveforms.
Fig. 7(b) shows the measured efficiency according to
the inductances for an output power of 25.8 dBm. As the
inductance decreases, the ripple current gets larger but
loss of the inductor becomes smaller. The linear
amplifier consumes more power to compensate for the
ripple current. As the inductance increases, a loss of the
inductor becomes larger. An inductance of 5.8 µH was
chosen for the best tradeoff.
Fig. 7(c) shows the measured efficiency versus various
load resistances. At a load resistance of 12 Ω, an efficiency
of 69 % was obtained. Fig. 7(d) shows the measured
efficiency according to the output power for a load
resistance of 12 Ω. The measured performances of the
implemented bias modulator are summarized in Table 1.
Table 1. Performance summary of the bias modulator
Parameters Values
Supply voltage 3.3 V
Output voltage range 0.1 – 3.2 V
Unit-gain bandwidth 50 MHz
Output current 0 – 650 mA
Efficiency
(Rload=12 Ω, VOUT=3.0 V) 84 %
Efficiency
(Rload=12 Ω, LTE 16-QAM 5 MHz,
Vrms=1.9 V)
69 %
IV. ET PA CONFIGURATION AND
MEASUREMENTS
The test bench for the CMOS ET PA is shown in Fig.
8. A baseband signal and an envelope signal for the 16-
QAM LTE up-link are generated using Agilent’s
Advanced Design System (ADS) and are downloaded
(a) (b)
(c) (d)
Fig. 7. The measured performances of the bias modulator for the 16-QAM LTE up-link signal (a) waveforms, (b) efficiency
according to the inductances for an Rload of 12 Ω, (c) efficiency according to the load resistances for an inductance of 5.8 µH, (d)
efficiency according to the output power level for an inductance of 5.8 µH and an Rload of 12 Ω.
240 JUNGHYUN HAM et al : A CMOS ENVELOPE TRACKING POWER AMPLIFIER FOR LTE MOBILE APPLICATIONS
into the two signal generators. The envelope signal is
oversampled using a sampling clock of 92.16 MHz using
MATLAB for more precise delay adjustment between
the RF path and envelope path.
The voltage waveforms of the envelope signal at the
input and output of the bias modulator are monitored
using an oscilloscope. The channel power, adjacent
channel leakage power ratio (ACLR), and error vector
magnitude (EVM) are measured using Agilent’s Vector
Signal Analyzer of VAS89600. The 16-QAM LTE up-
link signal with a PAPR of 7.3 dB, a signal bandwidth of
5 MHz, and a center frequency of 0.78 GHz was used for
the measurements. A single supply voltage of 3.3 V was
used for both the bias modulator IC and PA IC.
The voltage waveforms of the envelope signal at the
input and output of the bias modulator are monitored
using an oscilloscope. The channel power, adjacent
channel leakage power ratio (ACLR), and error vector
magnitude (EVM) are measured using Agilent’s Vector
Signal Analyzer of VAS89600. The 16-QAM LTE up-
link signal with a PAPR of 7.3 dB, a signal bandwidth of
5 MHz, and a center frequency of 0.78 GHz was used for
the measurements. A single supply voltage of 3.3 V was
used for both the bias modulator IC and PA IC.
When the original envelope signal is directly applied
to the drain terminal of the PA, the PA generates
substantial amplitude modulation to amplitude
modulation (AM-AM) and amplitude modulation to
phase modulation (AM-PM) distortions. Various
envelope shaping methods have been proposed to prevent
(a)
(b)
Fig. 8. The test bench for the ET PA (a) configuration, (b) photograph.
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.2, APRIL, 2014 241
this linearity issue [26]. The shaping functions for
various average output power levels, utilized for the ET
PA, are shown in Fig. 9. Due to the low knee voltage of
the MOSFET, an offset voltage of as low as 0.4 V was
used for the shaping functions. The selected shaping
functions can effectively improve the efficiency at even
backed-off power region while the ET PA complies with
the E-UTRA’s ACLR specifications. Fig. 10(a) shows
the measured gains and PAEs of the ET PA and PA alone.
For an average output power of 24 dBm, the PAE of the
ET PA is 41.7 % which is 5.3 % higher than that of the
PA alone. The PAEs of the ET PA are improved through
a wide power range and a maximum improvement of
10.3 % is observed at an output power of 17 dBm. The
gain of the PA decreases from 27 dB to 24.7 dB due to
the ET operation.
Fig. 10(b) shows the measured E-UTRA ACLR and
EVM performances for the ET PA. At an output power
of 24 dBm, an ACLR of -30 dBc and an EVM of 4.5 %
were achieved for both the ET PA and the PA alone. The
measured PSDs are presented in Fig. 10(c) for an average
output power of 24 dBm. The performances of the ET
PA compared to the PA alone are summarized in Table 2.
The measured performances of the ET PA are
compared to the previously published PAs with ET
techniques in Table 3. Even though the proposed ET PA
circuits were designed only using a standard CMOS
process, the performances are comparable to those of the
ET PAs whose PAs were designed using compound
semiconductor processes.
Fig. 9. Envelope shaping functions.
(a)
(b)
(c)
Fig. 10. Measured performances of the ET PA versus the PA
alone: (a) PAE and gain, (b) ACLR and EVM, (c) PSDs.
Table 2. Performance summary for the ET PA and the PA
alone using the 16-QAM LTE up-link signal
Parameters PA alone ET PA
Pout (dBm) 24 24
Gain (dB) 27.1 24.7
PAE (%) 36.4 41.7
ACLR (dBc) -30.8 -30
EVM (%) 4.3 4.5
242 JUNGHYUN HAM et al : A CMOS ENVELOPE TRACKING POWER AMPLIFIER FOR LTE MOBILE APPLICATIONS
V. CONCLUSIONS
In this paper, the ET PA ICs based on a standard 0.18-
µm CMOS process is presented. The PA is designed and
optimized to have a two-stage differential common-
source structure for high gain, high power, high
efficiency, and better ET operation. For the bias
modulator, the switching amplifier is optimized under
consideration of a dynamic load condition.
The implemented CMOS ET PA circuits are evaluated
using a 16-QAM LTE up-link signal with a signal
bandwidth of 5 MHz and a PAPR of 7.3 dB at a center
frequency of 0.78 GHz. A measured PAE of 41.7 % at an
average output power of 24 dBm was achieved using the
ET PA, while the PA alone exhibited 5.3 % lower PAE at
the same condition. Applying the optimized envelope
shaping function, almost no linearity degradation from
the performance of the PA alone was observed for the ET
PA at high output power region. The full CMOS based
ET PA in this work exhibited comparable output
performances to the previously published ET PAs even
using the PAs based on compound semiconductor
processes.
ACKNOWLEDGMENTS
This work was supported by the National Research
Foundation of Korea Grant funded by the Korean
Government (NRF-2011-220-D00084). The chips were
fabricated through the IC Design Education Center.
REFERENCES
[1] Y. Yang, J. Cha, B. Shin, and B. Kim, “A fully
matched n-way Doherty amplifier with optimized
linearity,” IEEE Trans. Microw. Theory Tech., vol.
51, no. 3, pp. 986–993, Mar. 2003.
[2] J. Lee, D. Kim, J. Burm, and J. Park, “Integratable
micro-doherty transmitter,” Journal of
Semiconductor Tech. and Science, vol. 6, no. 4, pp.
275–20, Dec. 2006.
[3] P. Reynaert and M. S. J. Steyaert, “A 1.75-GHz
polar modulated CMOS RF power amplifier for
GSM-EDGE,” IEEE J. Solid-State Circuits, vol. 40,
no. 12, pp. 2598–2608, Dec. 2005.
[4] V. Pinon, F. Hasbani, A. Giry, D. Pache, and C.
Garnier, “A single-chip WCDMA envelope
reconstruction LDMOS PA with 130 MHz
switched-mode power supply,” in IEEE Int. Solid-
State Circuits Conf. Tech. Dig., Feb. 2008, pp.
564–565.
[5] J. Kitchen, W. Chu, I. Deligoz, S. Kiaei, and B.
Bakkaloglu, “Combined linear and Δ-modulated
switched-mode PA supply modulator for polar
transmitters,” in IEEE Int. Solid-State Circuits Conf.
Tech. Dig., Feb. 2007, pp. 82–83.
[6] B. Sahu and G. A. Rincón-Mora, “A high-
efficiency linear RF power amplifier with a power-
tracking dynamically adaptive buck-boost supply,”
IEEE Trans. Microw. Theory Tech., vol. 52, no. 1,
pp. 112–120, Jan. 2004.
Table 3. Performance comparison of the ET PA
Ref. Freq.
(GHz)
VDD
(V)
Pout
(dBm)
PAE
(%)
Gain
(dB)
EVM
(%)
ACLR
(dBc) Modulation Technology
[10] 1.88 3.3 24.2 38.6 24.6 3.64 - WiBro 16-QAM
5 MHz
PA: 2 µm InGaP/GaAs
BM: 0.13 µm CMOS
[14] 1.88 3.3 23.9 34.3 27.9 2.98 - WiMAX 64-QAM
5 MHZ
PA: 2 µm InGaP/GaAs
BM: 0.13 µm CMOS
[15] 1.85 5.0 28.9 42.2 24.5 2.69 - LTE 16-QAM
10 MHz
PA: 2 µm InGaP/GaAs
BM: 0.13 µm CMOS
[16] 1.75 4.2 24.2 43.0 19.5 4.8 - LTE 16-QAM
5 MHz 0.35 µm SiGe BiCMOS
[17] 1.90 4.2 24.0 41.0 15.0 4.9 - LTE 16-QAM
5 MHz 0.35 µm SiGe BiCMOS
[19] 1.74 5/3.4 27.0 39.8 28.3 3.81 -35.7 LTE 16-QAM
10 MHz
PA: 2 µm InGaP/GaAs
BM: 0.18 µm CMOS
[20] 1.80 5/3.4 26.0 34.0 9.0 3.2 -32.5 LTE 16-QAM
10 MHz 0.18 µm CMOS
This work 0.78 3.3 24.0 41.7 24.7 4.5 -30 LTE 16-QAM
5 MHz 0.18 µm CMOS
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.2, APRIL, 2014 243
[7] F. Wang, A. H. Yang, D. F. Kimball, L. E. Larson,
and P. M. Asbeck, “Design of wide-bandwidth
envelope-tracking power amplifiers for OFDM
applications,” IEEE Trans. Microw. Theory Tech.,
vol. 53, no. 4, pp. 1244–1255, Apr. 2005.
[8] T. Kwak, M. Lee, and G. Cho, “A 2 W CMOS
hybrid switching amplitude modulator for EDGE
polar transmitters,” IEEE J. Solid-State Circuits,
vol. 42, no. 12, pp. 2666–2676, Dec. 2007.
[9] B. J. Minnis, P. A. Moore, P. N. Whatmough, P. G.
Blanken, and M. P. van der Heijden, “System-
efficiency analysis of power amplifier supply-
tracking regimes in mobile transmitters,” IEEE
Trans. Circuits Syst. I, vol. 56, no. 1, pp. 268–279,
Jan. 2009.
[10] J. Choi, D. Kang, D. Kim, and K. Kim, “Optimized
envelope tracking operation of Doherty power
amplifier for high efficiency over an extended
dynamic range,” IEEE Trans. Microw. Theory
Tech., vol. 57, no. 6, pp. 1508–1515, Jun. 2009.
[11] P. Y. Wu and P. K. T. Mok, “A two-phase
switching hybrid supply modulator for RF power
amplifiers with 9% efficiency improvement,” IEEE
J. Solid-State Circuits, vol. 45, no. 12, pp. 2543–
2556, Dec. 2010.
[12] Y. Li, J. Lopez, D. Y. C. Lie, K. Chen, S. Wu, T. Y.
Yang, and G-K Ma, , "Circuits and System design
of RF polar transmitters using envelope-tracking
and SiGe power amplifiers for mobile WiMAX,"
IEEE Trans. Circuits Syst. I, vol. 58, no. 5, pp. 893-
901, May 2011.
[13] F. Wang, D. F. Kimball, D. Y. Lie, P. M. Asbeck,
and L. E. Larson, “A monolithic high-efficiency
2.4-GHz 20-dBm SiGe BiCMOS envelope tracking
OFDM power amplifier,” IEEE J. Solid-State
Circuits, vol. 42, no. 6, pp. 1271–1281, Jun. 2007.
[14] J. Choi, D. Kim, D. Kang, and B. Kim, “A polar
transmitter with CMOS programmable hysteretic-
controlled hybrid switching supply modulator for
multistandard applications,” IEEE Trans. Microw.
Theory Tech., vol. 57, no. 7, pp. 1675–1686, Jul.
2009.
[15] D. Kim, D. Kang, J. Choi, J. Kim, Y. Cho, and B.
Kim, “Optimization for envelope shaped operation
of envelope tracking power amplifier,” IEEE Trans.
Microw. Theory Tech., vol. 59, no. 7, pp. 1787–
1795, Jul. 2011.
[16] Y. Li, J. Lopez, P.-H. Wu, W. Hu, R. Wu, and D. Y.
C. Lie, “A SiGe envelope-tracking power amplifier
with an integrated CMOS envelope modulator for
Mobile WiMAX/3GPP LTE transmitters,” IEEE
Trans. Microw. Theory Tech., vol. 59, no. 10, pp.
2525–2536, Oct. 2011.
[17] Y. Li, J. Lopez, C. Schecht, R. Wu, and D. Y. C.
Lie, “Design of high efficiency monolithic power
amplifier with envelope-tracking and transistor
resizing for broadband wireless applications,” IEEE
J. Solid-State Circuits, vol. 47, no. 9, pp. 2007–
2018, Sep. 2012.
[18] D. Kim, D. Kang, J. Kim, Y. Cho, and B. Kim,
“Highly efficient dual-switch hybrid switching
supply modulator for envelope tracking power
amplifier,” IEEE Microw. Wireless Compon. Lett.,
vol. 22, no. 6, pp. 285–287, Jun. 2012.
[19] J. Kim, D. Kim, Y. Cho, D. Kang, B. Park, B. Kim,
"Envelope-tracking two-stage power amplifier with
dual-mode supply modulator for LTE applications,"
Microwave Theory and Techniques, IEEE IEEE
Trans. Microw. Theory Tech., vol.61, no.1, pp.543,
552, Jan. 2013.
[20] D. Kang, B. Park, J. C. Zhao. Kim, D. Kim, J. Kim,
Y. Cho, S. Jin, H. Jin, and B. Kim, “A 34% PAE,
26-dBm output power envelope tracking CMOS
power amplifier for 10-MHz BW LTE
applications,” in IEEE MTT-S Int. Microw. Symp.
Dig., 2012, pp. 17–22.
[21] M. Hassan, L. E. Larson, V. W. Leung, and P. M.
Asbeck, “A combined series-parallel hybrid
envelope amplifier for envelope tracking mobile
terminal RF power amplifier applications,” IEEE J.
Solid-State Circuits, vol. 47, no. 5, pp. 1185–1198,
May 2012.
[22] M. Hassan, E. L. Larson, V. W. Leung, D. F.
Kimball, and P. M. Asbeck, "A wideband
CMOS/GaAs HBT envelope tracking power
amplifier for 4G LTE mobile terminal
applications," IEEE Trans. Microw. Theory Tech.,
vol. 60, no. 5, pp. 1321-1330, May 2012.
[23] G. Liu, P. Haldi, T.-J. K. Liu, and A. M. Niknejad,
“Fully integrated CMOS power amplifier with
efficiency enhancement at power back-off,” IEEE J.
Solid-State Circuits, vol. 43, no. 3, pp. 600–609,
Mar. 2008.
[24] I. Aoki, S. Kee, R. Magoon, R. Aparicio, F. Bohn, J.
244 JUNGHYUN HAM et al : A CMOS ENVELOPE TRACKING POWER AMPLIFIER FOR LTE MOBILE APPLICATIONS
Zachan, G. Hatcher, D. McClymont, and A.
Hajimiri, “A fully-integrated quad-band
GSM/GPRS CMOS power amplifier,” IEEE J.
Solid-State Circuits, vol. 43, no. 12, pp. 2747–2758,
Dec. 2008.
[25] S. Back, C. Park, and S. Hong, “A fully integrated
5-GHz CMOS power amplifier for IEEE 802.11a
WLAN applications,” Journal of Semiconductor
Tech. and Science, vol. 7, no. 2, pp. 98–101, Jun.
2007.
[26] B. Kim, J. Kim, D. Kim, J. Son, Y. Cho, J. Kim,
and B. Park, “Push the envelope: design concepts
for envelope-tracking power amplifiers,” IEEE
Microw. Mag., vol. 14, no. 3, pp. 68-81, Apr. 2013.
Junghyun Ham was born in Seoul,
Korea, in 1980. He received the M.S.
degree in electrical and computer
engineering from Hanyang University,
Seoul, Korea, in 2009 and is currently
working toward the Ph. D. degree in
the department of electronic and
computer engineering from Sungkyunkwan University,
Suwon, Korea. From 2009 to 2011, He was with LG
Electronics, Seoul, Korea, where he was involved in the
development of the high efficient power amplifier for
mobile handset applications. His research interests
include high efficient RF transmitters, high-speed DC-
DC converters, and CMOS RF power amplifiers.
Hearyun Jung was born in Seoul,
Korea in 1990. She received the B.S.
degree in the department of electronic
engineering from Kwangwoon
University, Seoul, Korea, in 2012.
She is currently working toward the
M. S. degree in the department of IT
convergence from Sungkyunkwan University, Suwon,
Korea. Her current research interests include RFIC
design, hybrid bias modulator, DC-DC converter, and
high efficiency CMOS power amplifiers.
Hyungchul Kim was born in
Chuncheon, Korea, in 1983. He
received the Ph.D. degree in
electronic and computer engineering
from Sungkyunkwan University,
Suwon, Korea in 2014. His research
interests include RF power amplifier
design, RFID tag IC design, low-power analog/mixed
signal circuit design and power converter design.
Wonseob Lim received the B.S.
degree in the department of Electronics
and Communication Engineering from
Hanyang University, Ansan, Korea in
2012. He is currently working toward
the M. S. degree in the department of
electronic and computer engineering
from Sungkyunkwan University. His current research
interests include class-D amplifier, high efficiency power
amplifier, DAC, digital filter and mixed signal circuit
design.
Deukhyoun Heo (S’97–M’00, IEEE)
received the B.S.E.E. degree in
electrical engineering from
Kyoungpuk National University,
Daegu, Korea, in 1989, the M.S.E.E.
degree in electrical engineering from
the Pohang University of Science and
Technology (POSTECH), Pohang, Korea, in 1997, and
the Ph.D. degree in electrical and computer engineering
from the Georgia Institute of Technology, Atlanta, in
2000. In 2000, he joined the National Semiconductor
Corporation, where he was a Senior Design Engineer
involved in the development of silicon RFICs for cellular
applications. Since Fall 2003, he has been an Associate
Professor with the Electrical Engineering and Computer
Science Department, Washington State University,
Pullman. He has authored or coauthored approximately
120 publications, including 40 peer-reviewed journal
papers and 80 international conference papers. He has
primarily been interested in RF/microwave/opto
transceiver design based on CMOS, SiGe BiCMOS, and
GaAs technologies for wireless and wireline data
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.2, APRIL, 2014 245
communications, batteryless wireless sensors and
intelligent power management system for sustainable
energy sources, adaptive beam formers for phased-array
communications, low-power high data-rate wireless links
for biomedical applications, and multilayer module
development for system-in-package solution. Dr. Heo has
been a member of the Technical Program Committee of
the IEEE Microwave Theory and Techniques Society
(IEEE MTT-S) International Microwave Symposium
(IMS) and the International Symposium of Circuit and
Systems (ISCAS). He has served as an associate editor
for the IEEE TRANSACTIONS ON CIRCUITS AND
SYSTEMS —PART II: EXPRESS BRIEFS (2007–2009)
and has served as an associate editor for the IEEE
TRANSACTIONS ON MICROWAVE THEORY AND
TECHNIQUES. He was the recipient of the 2000 Best
Student Paper Award presented at the IEEE MTT-S IMS
and the 2009 National Science Foundation (NSF)
CAREER Award.
Youngoo Yang was born in
Hamyang, Korea, in 1969. He
received the Ph.D. degree in
electrical and electronic engineering
from the Pohang University of
Science and Technology(Postech),
Pohang, Korea, in 2002. From 2002
to 2005, he was with Skyworks Solutions Inc., Newbury
Park, CA, where he designed power amplifiers for
various cellular handsets. Since March 2005, he has been
with the School of Information and Communication
Engineering, Sungkyunkwan University, Suwon, Korea,
where he is currently an associate professor. His research
interests include power amplifier design, RF transmitters,
RFIC design, integrated circuit design for RFID/USN
systems, and modeling of high power amplifiers or
devices.