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A 25-Gb/s FIR Equalizer Based on Highly Linear All-Pass Delay Stages in 28-nm LP CMOS

F.Loi 1, E. Mammei 2, F. Radice 3, M. Bruccoleri3, S. Erba 2, M. Bassi 1, A. Mazzanti 1,

1DIII, University of Pavia – Italy, 2STMicroelectronics, Pavia – Italy,

3STMicroelectronics, Cornaredo - Italy

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•  Introduction •  FIR noise and linearity requirements •  Highly linear Delay-Line •  Design and measurements •  Conclusions

Outline

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DFE

+CHANNEL

Driver/FIRRXTX

FFE

FFE in high speed serial link

•  CTLEs: -  Simplicity ✓ -  Low power ✓ -  Limited flexibility ✗

•  Finite Impulse Response filter (FIR): -  Complexity ✗ -  Power dissipation ✗ -  High flexibility ✓

•  FIR advantages:

-  Able to remove the pre-cursor ISI -  Compatible with simple adaptation algorithm (LMS) -  Optimally adapted in conjuction with DFE

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gm0

Td

VGARL

Vin

Vout Buffer

gm1 gm2 gm3

Td Td

Proposed FIR equalizer

•  Target •  Nyquist attenuation recovery ≥ 20dB •  Bit Rate 25 Gb/s •  SNR ≥ 30dB

•  Proposed solution •  4 taps continuos-time analog delay-line •  FIR coefficients set by transconductors with shared RL •  VGA and buffer used for measurements

H(f ) = ci ⋅e− j (2πf ⋅i ⋅Td )

i=0..3∑

ci = gmi ⋅RL

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1

-1

0

1

-1

0

Noise and voltage swings

•  Gain and HF boost trade each other •  Considering nout, high voltage swing required to keep high SNR

Gain (GLF ) = cii=0..3∑

HF boost = (−1)i cii=0..3∑

H(f ) = ci ⋅e− j (2πf ⋅i ⋅Td )

i=0..3∑

f → 0

f ~ 1 2Td

gm0

Td

RL

Vin

Voutgm1 gm2 gm3

Td Td

nout+

Vin Vout

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1

-1

0

1

-1

0

Noise and voltage swings

gm0

Td

RL

Vin

Voutgm1 gm2 gm3

Td Td

nout+

Vin Vout

•  nout = 1.5 mVrms à Vout > 100 mVpk-pk for 30 dB SNR

•  20 dB HF boost with |ci| ≤ 0.6 leads to GLF = -17 dB

à Vin ≥ 700 mVpk-pk

High compression point key for SNR and signal integrity

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0.2 0.4 0.6 0.8 1 1.2020406080

100

Vin/V1dB−CP

Eye

Ope

ning

[%]

VerticalHorizontal

time, [UI]

−1 −0.5 0 0.5 1−1

01

time, [UI]

−1 0 1

−101

Input Amp. << V1dB-CP

Input Amp. > V1dB-CP

Impact of FIR filter compression Channel loss: 14 dB

x x x xc0 c1 c2 c3

Vin TdDelay cell

Td Td

Vout

Channel

Eye opening penalty when FIR is beyond the linear region

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0.2 0.4 0.6 0.8 1 1.2020406080

100

Vin/V1dB−CP

Eye

Ope

ning

[%]

VerticalHorizontal

Impact of FIR filter compression Channel loss: 34 dB

time, [UI]

−1 0 1−2

0

2Input Amp. << V1dB-CP

time, [UI]

−1 0 1−2

0

2Input Amp. > V1dB-CP

Highly linear FIR even more important when DFE is considered

x x x xc0 c1 c2 c3

Vin TdDelay cell

Td Td

Vout

Channel

VoutDFE

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y(s)x(s)

=1− sτ1+ sτ

GD(ω) = − ∂ϕ∂ω

=2τ

1+ (ωτ )2

•  All-pass filter realized with LP/HP filter and feedforward path

•  Bandwidth independent from group delay (GD) •  Group delay with roll-off after 2τ ω > 1 τ

x(s) y(s) x(s) y(s)++ - ++

-First-order low-pass filter First-order high-pass filter

Analog delay block diagram

“Mammei et al. JSSC 2014” Proposed solution

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Analog delay circuit diagram

•  gm1+ RC/RL load form the LP/HP filter •  Same transfer function but very different compression performance •  Maximum voltage swing on first transconductor •  RL load shorts low frequency distorsion

Adder

R+ +

- -

+ +

- -

Z(s)

+ +

- -

Vin Vin/2

Vin/2

gm gm

gm

RC load RL load

Vin Vout

Circuit with RL load shows much better 1dB-CP  

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Compression point analysis

Adder

R+ +

- -

+ +

- -

Z(s)

+ +

- -

Vin Vin/2

Vin/2

gm gm

gm

RC load RL load

Vin Vout

Vin/2iout = gmV + gm3V3 iout = gmV + gm3V3

A1dB−CP = 0.145 gm2.25 gm3

A1dB−CP = 0.145 gm0.25 gm3

•  RC Load •  RL Load

~ 9 dB better 1dB-CP with RL load  

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1 dB C.P. vs Frequency

•  Simulations confirm the prediction •  1dB-CP decreases with frequency •  High frequency channel loss makes this not problematic

4 8 12 16 20 24 28−30

−25

−20

−15

−10

−5

0

Frequency [GHz]

1dB

C.P

.

RLRC

9 dB ~4 dB @ Ny

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Circuit design

RP+ +

- -

+ +

- -

+ +

- -

gm1 gm2

gm3

Vin Vout

LPR L

Vin

Vbias

Iout

CPAR COUT

•  Parasitic capacitance COUT limits the bandwidth •  Shunt peaking LP to achieve ~ 18 GHz bandwidth •  Output network (RP+LP+COUT) contributes to total group delay •  CPAR leads to an overshooting in group delay

gm1R = 2 gm2,3RP = 1

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1 100

10

20

30

Frequency [GHz]

GroupDelay[ps] •  Red path: 15 ps LF GD

•  Blue path: 9 ps LF GD

•  Blue curve roll-off suppress the total overshooting

Group delay contributions

RP+ +

- -

+ +

- -

+ +

- -

gm1 gm2Vin Vout

LPR L

gm3

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Tap amp, VGA and buffer

+Iout -Iout

+V

•  Degenerated differential pair for 1dB-CP > -5 dBV

•  Programmable positive/negative gain with 6-bits resolution

VGAVin BufferFIR

0 - 10 dBVout

•  VGA: cascade of 3 diff. pairs with peaking inductors

•  VGA consumption 4 mW •  Buffer to drive output pad and

50 Ohm (10 mW)

Programmable amplifier VGA and buffer

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• CMOS 28nm LP by STMicroelectronics

• Core area: 0.065 mm2

• Supply Voltage: 1 V • Power: 25 mW

Test chip

310 µm

220 µm

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Measurement setup

•  Backplane: -20 dB @ 12.5 GHz •  BERT: Anritsu MP1800A

1 10�60

�50

�40

�30

�20

�10

0Channel response

Mag

nitu

de [d

B]

Frequency [GHz]

0 1 2 3 4 5 6 7 8 9 10 11 12

Am

plitu

de [V

]Time [UI]

0.4

0.3

0.2

0.1

0

-0.1

a

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�0.5 �0.25 0 0.25 0.510

�12

10�10

10�8

10�6

10�4

Time [UI]

BER

Bathtub

Output Eye Diagram

-100

0

-200

300

200

100

Am

plitu

de [m

V]

-300

�

•  Input amplitude ~ 900 mVpk-pk •  Output amplitude ~ 380 mVpk-pk •  50% H-Opening @ BER<10E-12

Input Eye Diagram

-100

100

-300

500

300

Am

plitu

de [m

V]

-500

Eye diagrams and bathtub

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State of the art JSSC 2012 JSSC 2012 This work

Technology 45 nm SOI CMOS

65 nm CMOS 28 nm LP CMOS

Supply 1.1 V 1.6 V 1 V DataRate 17 Gb/s 40 Gb/s 25 Gb/s Att. @ Ny 21 dB 19 dB 20 dB

BER 10-9 10-12 10-12 Power diss 32 mW 55.2 mW 25 mW

Area 0.07 mm2 - 0.065 mm2 H. Opening 39 % < 32 % 50 %

Power/DataRate 1.9 mW/Gb/s 1.4 mW/Gb/s 1 mW/Gb/s

Proposed equalizer shows the widest eye opening and best power consumption

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•  An analog FIR filter has been presented for 25 Gb/s backplane equalization

•  Novel active all-pass sections are proposed to realize a 4-taps continuos time delay-line with excellent 1dB compression point

•  Measurements on a 28-nm LP CMOS test-chip prove data equalization on a channel with 20 dB loss at Nyquist

•  The equalizer accomodates large input signal (>1V) without compression leading to high SNR and very good horizontal eye opening

Conclusions

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The authors are grateful to STMicroelectronics for technical

contributions and silicon access and to Anritsu-Italy for precious support in chip

measurements.

Acknowledgments