Session RMO3B-2

A 38-Gb/s 2-tap Transversal Equalizer

in 0.13-µm CMOS using a Microstrip

Delay Element

George Ng and Anthony Chan Carusone

Dept. of Electrical & Computer Engineering

University of Toronto

10 King’s College Rd., Toronto, Ontario,

M5S 3G4, Canada

Outline

• Motivation

• 2-tap FIR equalizer topologies

• Circuit design

• Measurement results

• Conclusion

2RFIC – Atlanta June 15-17, 2008

Motivation

• Frequency dependent channel losses results

in inter-symbol interference (ISI) at receiver

• A simple 2-tap finite impulse response (FIR)

equalizer can be used to compensate the

channel losses

FIR EqualizerCoax Channel

3RFIC – Atlanta June 15-17, 2008

2-Tap FIR Equalizer

Discrete Filter

Traveling Wave Filter

Transversal Filter

b0

b1

IN OUT

τ

b0 b1

RT

2

2

IN

OUT

RT

b0 b1

τIN

OUT

RT

RT

4RFIC – Atlanta June 15-17, 2008

b0 b1

RT

2

2

IN

OUT

RT

Traveling Wave Filter

• Compensates for

reflections due to

termination

impedance mismatch

• Difficult to get gain

due to output side

delay element

5RFIC – Atlanta June 15-17, 2008

b0 b1

τIN

OUT

RT

RT

Transversal Filter

• Cannot easily

compensate for

termination mismatch

reflections

• Offers gain

advantage due to co-

location of tap

outputs

6RFIC – Atlanta June 15-17, 2008

Microstrip Passive Delay Line

• “U” shape simplifies

routing to taps

• Easier to

accommodate metal

fill rules

• Higher bandwidth

than lumped L-C

delay line

7RFIC – Atlanta June 15-17, 2008

OUT

RT

b0

IN

RT

b1

VCTRL1

VDD

50 Ω 50 Ω

IN

2.9 mm long

50 Ω mstrip transmission line

46 x 1 x 0.12 mm

30 x 1 x 0.12 mm

VCTRL2

73 pH 73 pH

73 pH

73 pH 50 Ω

OUT

M1 M3 M2

2-Tap Transversal Equalizer

Line InductorLength = 60 umWidth = 1.5 umInductance = 73 pH

8RFIC – Atlanta June 15-17, 2008

0 20 40 60 80 100-55

-50

-45

-40

-35

-30

-25

-20

Frequency (GHz)

|S1

1|

(dB

)

Unloaded Microstrip Line

9RFIC – Atlanta June 15-17, 2008

0 10 20 30 40 50-25

-20

-15

-10

-5

0

Frequency (GHz)

(dB

)

S21

S11

S22

2-Tap without Line Inductors

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S22 = - 7.1 dB

S11 = - 5.4 dB

0 10 20 30 40 50-25

-20

-15

-10

-5

0

Frequency (GHz)

(dB

)

S21

S11

S22

2-Tap with Line Inductors

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S22 = - 10 dB

S11 = - 13 dB

Simulated Peaking

0.6 0.7 0.8 0.9 1 1.1 1.20

2

4

6

8

10

VCTRL2

(V)P

ea

kin

g (

dB

)

Peaking at maximum frequency

versus peaking control voltage

(VCTRL2)

S21 versus frequency

0 10 20 30 40 50 60-10

-8

-6

-4

-2

0

2

Frequency (GHz)

|S2

1|

(dB

)

VCTRL2

= 0.8 V

VCTRL2

= 0.9 V

VCTRL2

= 1.2 V

12RFIC – Atlanta June 15-17, 2008

Die Photo

1.5 mm

0.26 mm

GND

VC

TRL1

IN

GND

GND

OUT

GN

D

VC

TRL2

GN

D

VD

DUMC 0.13-µm CMOS process

13RFIC – Atlanta June 15-17, 2008

MICROSTRIP TRANSMISSION LINETAPS

S-Parameter Matching

0 5 10 15 20 25-40

-35

-30

-25

-20

-15

-10

-5

Frequency (GHz)

|S1

1|,

|S2

2|

(dB

)

S11 measured

S11 simulated

S22 measured

S22 simulated

Maximum PeakingNo Peaking

14RFIC – Atlanta June 15-17, 2008

0 5 10 15 20 25-40

-35

-30

-25

-20

-15

-10

-5

Frequency (GHz)|S

11|,

|S2

2|

(dB

)

S11 measured

S11 simulated

S22 measured

S22 simulated

Eye Diagrams – 38 Gb/s

0 5 10 15 20 25-25

-20

-15

-10

-5

0

Frequency (GHz)(d

B)

Channel Loss @ 19 GHz: 14.3 dB

(one-half bit-rate)

Channel Type: 6-ft SMA &

3-ft 50-GHz cable

Unequalized Eye

15RFIC – Atlanta June 15-17, 2008

Eye Diagrams – 38 Gb/s

Unequalized Channel Eye Equalized Eye

VDD = 1.2 V

VCTRL1 = 0.82 V

VCTRL2 = 0.88 V16RFIC – Atlanta June 15-17, 2008

Eye Diagrams 30 & 36 Gb/s

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30 Gb/s

36 Gb/s

Linearity

-35 -30 -25 -20 -15 -10 -5 0 5-80

-70

-60

-50

-40

-30

-20

-10

0

10

Input Power (dBm)

Ou

tpu

t P

ow

er

(dB

m)

Fundamental

HD2

HD3

Mode No peaking

Input Tone (GHz) 2

Input Ref. 1 dB Comp. Pt. (dBm) 1.8

THD @ Comp. Pt. (dB) -27.5

18RFIC – Atlanta June 15-17, 2008

Measurement Summary

Specification Measured Result

Process UMC 0.13-mm CMOS

Nominal Operating Supply (V) 1.2

Nominal IDD (mA)

Nominal ICTRL2 (mA)

12 (no peaking),

17 (max peaking)

0 (no peaking),

8 (max peaking)

Maximum Power Consumption (mW) 30 mW

14 mW (tap 1)

16 mW (tap 2)

S11 (peaking off) (dB) > -9.2 dB up to 26.5 GHz

S22 (peaking off) (dB) > -10 dB up to 26.5 GHz

Maximum equalized channel attenuation (dB) 14.3

Maximum equalized bit-rate (Gb/s) 38

Input ref. 1-dB compression point (no peaking) (dBm) 1.8

19RFIC – Atlanta June 15-17, 2008

Conclusion

• Presented a 2-tap transversal FIR equalizer

• Utilizes “U” shaped microstrip transmission line

to achieve baud-tap spacing

• Series “line inductors” maintain constant input

and output impedance up to 30 GHz

• Demonstrated equalization of 38-Gb/s data

stream with 14.3 dB of channel attenuation

20RFIC – Atlanta June 15-17, 2008

Acknowledgments

• Gennum Corporation for IC fabrication

• Broadcom Corporation for financial

support

RFIC – Atlanta June 15-17, 2008 21

Questions?

22RFIC – Atlanta June 15-17, 2008