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SUBMITTED BY: RACHIT SHARMA EI/08/8532

8051 microcontroller.ppt

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Page 1: 8051 microcontroller.ppt

SUBMITTED BY:RACHIT SHARMAEI/08/8532

Page 2: 8051 microcontroller.ppt

• The embedded system is a combination of computer hardware, software additional electrical & mechanical parts

• A computer is used in such devices primarily as a means to simplify the system design and to provide flexibility.

• Embedded systems employ the use of a RTOS (Real-Time Operating System).

INTRODUCTION TOEMBEDDED SYSTEM

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• Consumer electronics• Telecommunication• Automobile• Medical instrumentation• Industrial control equipment• Defense• Communication satellite• Data communication• Internet appliances

APPLICATONS OFEMBEDDED SYSTEMS

 

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• A microcontroller is a computer-on-a-chip.

• Micro suggests that the device is small, and controller tells you that the device might be used to control objects, processes, or events.

• Another term to describe a microcontroller is embedded controller, because the microcontroller and its support circuits are often built into, or embedded in, the devices they control.

INTRODUCTIONTO MICROCONTROLLER

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• Complete, highly-integrated microcomputer– CPU, RAM, ROM, IO

• Port 0– 8-bit bidirectional I/O port OR– multiplexed low-order address and data

bus bytes• Port 1

– 8-bit bidirectional I/O port• Port 2

– 8-bit bidirectional I/O port OR– high-order address byte

• Port 3– 8-bit bidirectional I/O port OR– various special-function signals

8051 MICROCONTROLLER

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8051 MICROCONTROLLER Interface Signals

PO/AD[7-0]

P1

P2 / A[15-8]

P3.2 /INT0*P3.3 /INT1*

P3.4 / T0P3.5 / T1

P3.6 / WR*P3.7 / RD*

WriteRead

Timer 1Timer 0

Interrupt 1Interrupt 0

Port 0 or Lo Addr/Data

Port 1

Port 2 or Hi Addr

Port 3/Special Functions:

8

8

8

P3.0 /RXDP3.1 /TXD

Serial Input PortSerial Output Port

PSENALE /PROG*Addr Latch Ena/Program

Program Store Enable[Bus Timing]

[Int]

[I/O]

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• 8 bit CPU with registers A and B 

• 16 bit program counter(PC) and data pointer(DPTR) 

• 8 bit program status word(PSW)

• 8 bit stack pointer

• Internal ROM of 0(8031) to 4K(8051)

• Internal RAM of 128 Bytes

• 4 register banks 00-1f

• 16 bytes(bit addressable) 20-2f

• 80 bytes of general purpose data memory 30-7f

• 32 I/O pins arranged as four 8 bit ports (P0 – P3)

• 2 16-bit timer/counters: T0 and T1

• Full duplex serial data receiver/transmitter: SBUF

• Control registers: TCON, TMOD, SCON, PCON, IP and IE

• 2 external and 3 internal interrupt sources

• Oscillator and clock circuits

8051 ARCHITECTURE

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INTERNAL RAM

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• Accumulator• “R” registers• B register• Data Pointer (DPTR) – 16-bit

register• Program Counter (PC) – 16-

bit register• Stack Pointer (SP)

BASIC REGISTERS

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• Simply stated, the MOV instruction copies data from one location to another.

• It has the following format

MOV destination, source• This instruction tells the CPU to move (copy) the source

operand to the destination operand, without changing the content of the source operand.

• Examples:• MOV A,#55h ; load 55h into register A• MOV R0,A ; copy contents of A into R0• MOV R3, #95h; load value 95h into R3• MOV A,R3 ;copy content of R3 into A

MOV INSTRUCTION

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• The ADD instruction has the following format:

ADD A, source ; Add the source operand to A

• This tells the CPU to add the source byte to reg A and put the result in reg A

ADD INSTRUCTION

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• An "addressing mode" refers to how you are addressing a given memory location.

• In summary, the addressing modes are as follows, with an example of each:

• Immediate Addressing MOV A,#20h• Direct Addressing MOV A,30h• Indirect Addressing MOV A,@R0• External Direct MOVX A,@DPTR• Code Indirect MOVC A,@A+DPTR

• Each of these addressing modes provides important flexibility.

ADDRESSING MODES

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• Immediate addressing is so-named because the value to be stored in memory immediately follows the operation code in memory. That is to say, the instruction itself dictates what value will be stored in memory.

MOV A,#20h • This instruction uses Immediate Addressing

because the Accumulator will be loaded with the value that immediately follows; in this case 20 (hexadecimal).

• Immediate addressing is very fast since the value to be loaded is included in the instruction. However, since the value to be loaded is fixed at compile-time it is not very flexible.

IMMEDIATE ADDRESSING

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• Direct addressing is so-named because the value to be stored in memory is obtained by directly retrieving it from another memory location. For example:

MOV A,30h • This instruction will read the data out of Internal RAM

address 30 (hexadecimal) and store it in the Accumulator. • Direct addressing is generally fast since, although the

value to be loaded isn't included in the instruction, it is quickly accessible since it is stored in the 8051s Internal RAM.

• It is also much more flexible than Immediate Addressing since the value to be loaded is whatever is found at the given address--which may be variable.

• Also, it is important to note that when using direct addressing any instruction which refers to an address between 00h and 7Fh is referring to Internal Memory. Any instruction which refers to an address between 80h and FFh is referring to the SFR control registers that control the 8051 microcontroller itself.

DIRECT ADDRESSING

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• Indirect addressing is a very powerful addressing mode which in many cases provides an exceptional level of flexibility.

MOV A,@R0 • This instruction causes the 8051 to

analyze the value of the R0 register. The 8051 will then load the accumulator with the value from Internal RAM which is found at the address indicated by R0.

• Indirect addressing always refers to Internal RAM; it never refers to an SFR.

INDIRECT ADDRESSING

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• External Memory is accessed using "External Direct" addressing.

• There are only two commands that use External Direct addressing mode:

MOVX A,@DPTRMOVX @DPTR,A

• As you can see, both commands utilize DPTR. • In these instructions, DPTR must first be loaded

with the address of external memory that you wish to read or write. Once DPTR holds the correct external memory address, the first command will move the contents of that external memory address into the Accumulator.

• The second command will do the opposite: it will allow you to write the value of the Accumulator to the external memory address pointed to by DPTR.

EXTERNAL DIRECT ADDRESSING

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• External memory can also be accessed using a form of indirect addressing.

• This form of addressing is usually only used in relatively small projects that have a very small amount of external RAM. An example of this addressing mode is:

MOVX @R0,A • Once again, the value of R0 is first read

and the value of the Accumulator is written to that address in External RAM. Since the value of @R0 can only be 00h through FFh the project would effectively be limited to 256 bytes of External RAM.

EXTERNAL INDIRECT ADDRESSING

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• Consists of a series of assembly language instructions.

• Instruction consists of four fields: [label1:] mnemonic [operands]

[;comment]• Label field allows the program to

refer to a line by name.• Comment field must begin with a

semicolon

STRUCTURE OF ASSEMBLY LANGUAGE

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• The DB directive is the most widely used data directive in assembler.

• Used to define the 8-bit data.• When DB is used, the numbers can be

decimal, binary, hex or ASCII formats.• The only directive that can be used to define

ASCII strings larger than two characters.

ORG 500HDATA1: DB 39HDATA2: DB “2591” ;ASCII NUMBERS

ORG 518HDATA3: DB “Computer Engineering”

DB

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• ORG: Used to indicate the beginning of the address.

• EQU: Used to define a constant without occupying a

memory location. e.g. Count EQU 25

• END: Indicates the end of the source file.

ASSEMBLER DIRECTIVES

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• Addresses D0h, Bit-Addressable• The Program Status Word is used to store a

number of important bits that are set and cleared by 8051 instructions.

• The PSW SFR contains the carry flag, the auxiliary carry flag, the overflow flag, and the parity flag.

• Additionally, the PSW register contains the register bank select flags which are used to select which of the "R" register banks are currently selected.

PSW(Program Status Word)

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• Section of RAM used by the CPU to store information temporarily.

• Information can be data or an address.

• The CPU needs this storage area since there are only a limited number of registers.

STACKS

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• The register used to access the stack is called the SP (stack pointer) and is 8-bits wide (00h-ffh).

• When the 8051 is powered up the SP contains the value 07.– This means that RAM location 08 is the

first location used for the stack.– Final location is 1F (20h -> used for bit-

addressable memory)• Storing of a CPU register in the stack is

called a PUSH.• Loading the contents of the stack back into

a CPU register is called a POP.

ACCESSING STACKS

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• Ram locations 08 – 1F used for the stack.

• If more than 24 bytes of stack required, then the SP must be changed to point to RAM locations 30h-7Fh using the instruction

MOV SP,#xx• Also may need to shift SP if a

given program needs register bank1,2 or 3.

UPPER LIMIT

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• When an 8051 is first initialized, it resets the PC to 0000h.

• The 8051 then begins to execute instructions sequentially in memory unless a program instruction causes the PC to be otherwise altered.

• There are various instructions that can modify the value of the PC; specifically, conditional branching instructions, direct jumps and calls, and "returns" from subroutines.

• Additionally, interrupts, when enabled, can cause the program flow to deviate from its otherwise sequential scheme.

PROGRAM FLOW

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• Repeating a sequence of instructions a certain number of times is called a loop.

• The loop action is performed by the instruction

DJNZ reg,label• In this instruction, the register is

decremented; if it is not zero, it jumps to the target address referred to by the label.

• Prior to the start of the loop the register is loaded with the counter for the number of repetitions.

LOOP & JUMPINSTRUCTIONS

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• All conditional jumps are short jumps, meaning that the address of the target must be within -128 and +127 bytes of the contents of the program counter (PC).

• Unconditional jump instructions are:–LJMP (Long jump) – 3 byte

instruction–SJMP (Short jump) – 2 byte

instruction

UNCONDITIONAL JUMP INSTRUCTIONS

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• CALL instruction is used to call a subroutine

• LCALL (long call) – 3 byte instruction• ACALL (absolute call) – 2 byte instruction–When a subroutine is called, control is

transferred to that subroutine.– After finishing execution of the

subroutine, the instruction RET (return) transfers control back to the caller.

CALL INSTRUCTIONS

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• In the 8051 family, these clock cycles are referred to as machine cycles.

• The frequency of the crystal connected to the 8051 family can vary from 4MHz to 30MHz.

• In the 8051, one machine cycle lasts 12 oscillator periods.

• Therefore, to calculate the machine cycle, we take 1/12 of the crystal frequency and then take the inverse.

TIME DELAY GENERATION& CALCULATION

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• A delay subroutine consists of two parts:(a) setting a counter(b) a loop

• Most of the time delay is performed by the body of the loop.

• Very often we calculate the time delay based on the instructions inside the loop and ignore the clock cycles associated with the instructions outside the loop.

• Largest value of a register can hold is 255;• therefore, one way to increase the delay is to

use the NOP command.• NOP, which stands for “No Operation” simply

wastes time.

DELAY CALCULATION

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• This project is designed to demonstrate the technology used in the now a day’s driver less metro train.

• These trains are equipped with the CPU, which controls the train.

• The train is programmed for the specific path.

• Every station on the path is defined; stoppage timing of the train and distance between the two stations is predefined.

INTRODUCTION TOMETRO TRAIN PROTOTYPE

USING 8051

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• The motion of the train is controlled by the stepper motor, for displaying message in the train we are using intelligent LCD display of two lines.

• Before stopping at station the train blows the buzzer.

• It also includes an emergency brake system due to which the train stops as soon as the brakes are applied and resumes journey when the emergency situation is over.

• This project is implemented using the VPL-ET kit.

METRO TRAIN PROTOTYPEUSING 8051