Philips 8051

PHILIPS SEMICONDUCTORS - SIGNETICS. MICROCONTROLLER TRAINING FOILS 1

Agenda

1. Overview of 8051 Architecture, Timing, On-chip Resources, Instruction Set etc. Derivative products

2. Programming the 8051: Basic techniques, tips & tricks.

3. Development Support: Development Boards, Emulators, EPROM Programmers, Compilers, etc.

4. I2C, a simple Multi-master 2-wire serial bus.

5. ACCESS.Bus, an I2C-based protocol for connecting peripherals to workstations/PCs.


The 8051

An 8-bit Microcontroller optimized for control applications.

A Microcontroller derivative family based on the 8051 core.

A Microcontroller because you can make a one-chip system with the one chip containing:

Program & Data Memory

I/O Ports

Serial Communication

Counters/Timers

Interrupt Control logic

A-to-D and D-to-A convertors

& so on ...


Features of the 8051

- 8 Bit data path and ALU.

- Easy interfacing.

- 12 to 30 MHz versions available.

( 1 µsec to 400 ns for single cycle instructions).

- Full instruction set including:

Multiply and Divide.

Bit set, reset, and test (Boolean instructions).

- Variety of addressing modes.


Features of the 8051 (cont'd)

- 4K X 8 ROM - Program memory.

- 128 x 8 RAM - Data memory.

- Special function registers.

- Serial I/O port.

- 32 I/O lines.

- Two 16-bit counter/timers.


8051 Logic Symbol

VSS VCC RST

P0.7P0.6P0.5P0.4P0.3P0.2P0.1P0.0

PO RT0

ADDRESS ANDDATA BUS

XTAL1

XTAL2

ALE

EA

PSEN

P3.7P3.6P3.5P3.4P3.3P3.2P3.1P3.0

RxD TxD INT0INT1T0T1WRRD

SECONDARYFUNCTIONS

PORT3

P2.7P2.6P2.5P2.4P2.3P2.2P2.1P2.0

PORT2

ADDRESSBUS

P1.7P1.6P1.5P1.4P1.3P1.2P1.1P1.0

PORT1


80C51 Block Diagram

Interrupt Control

External Interrupts

CPU

OSC

Timer 1

Timer 0

SerialPort

I/O PortsBusControl

CounterInputs

P0 P3P1

4k byteROM

128 byteRAM

P2(Address/Data)

TXD RXD


Addressing Space

- 64K X 8 ROM - Program memory.

- 64K x 8 RAM - External data memory.

- 256 x 8 RAM - Internal data memory.

- 128 x 8 Special function registers (SFRs).

- Bit addressing of 16 RAM locations

and 16 SFRs.


Program Memory

- 16 bit Program Counter (PC).

- 16 bit Data Pointer (DPTR).

- 64K byte address space each for Program & Data.

- Table lookup using relative addressing:

PC + ACC (Move).

DPTR + ACC (Move and jump).

- EA pin disables internal ROM and

activates external program memory

and addressing.


Internal Data Memory

- 128 bytes of RAM.

- Directly addressable range:

00 to 7F hexadecimal.

- Indirectly addressable range:

00 to FF hexadecimal.

- Bit addressable space:

20 to 2F hexadecimal .

- Four register banks:

00 to 1F hexadecimal.


Internal Data Memory

7F

30

2F

20

R0

R1

R2

R3

R4

R5

R6

R7

REGISTER BANK 1

REGISTER BANK 2

END 8051 RAM

BIT ADDRESSABLE

REGISTER BANK 3

00

1F

0F

17

18

08

07

20

REGISTER BANK 0

07 . . . . . . . . . 00

FF . . . . . . . . . F8


External Data Memory

- 64K byte address space.

- Indirectly addressable via R0 and R1

in 256 byte segments.

- Entire space is indirectly addressable

via the data pointer DPTR.


External Bus Expansion

8051

PORT 2

PORT 0

ALE

P3.7

P3.6

PSEN

A15 - A8: High byte of address

AD7 - AD0: Data and low byte

address

ALE: Address latch enable

RD: Read strobe

WR: Write strobe

PSEN: Program store enable


8051 Timing

State 1 State 2 State 3 State 4 State 5 State 6 State 1 State 2

XTAL2

ALE

_____PSEN

P0

P2

Datasampled

PCL out PCL out

Datasampled

PCL out

Datasampled

PCH out PCH out

P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2


External Program Memory

8051

PORT2

ALE

PORT0

PSEN

ADDRESS

LATCH

ROM(S)

ADDRESS INPUTS

DATA

OUTPUTS

OE

A15 - A8

A7 - A0

D7 - D0

AD7 - AD0


External Data Memory

· 64K byte adress space.

· Indirectly addressable via R0 and R1

in 256 byte segments.

· Entire space in indirectly addressable

via the data pointer DPTR. 8051

PORT 2

ALE

PORT 0

WRRD

RAM(S) or I/O

CE

DATA OUTPUTS

ADDRESS INPUTS

R/WOE

ADDRESS LATCH

DECODE


Reset

· RST pin is Schmitt trigger input.

· External reset is asychronous to the internal clock.

· RST pin must be high for at least two machine cycles while the oscillator is running.

· Internal RAM not affected by reset, but indeterminate on power up.

· Port pins in random state until oscillator starts and algorithm write 1's to them.

· Reset sets PC to 0000.

· Typical circuits:

8051

RST

+5V

8.2K

10uF

80C51

RST

+5V

2.2uF


Special Function Register Space

- 128 byte address space, directly

addressable as 80 to FF hex.

- 16 addresses are bit addressable:

Set, Clear, AND, OR, MOV

(those ending in 0 or 8).

- This space contains:

Special purpose CPU registers.

I/O control registers.

I/O ports.


Special Function Register Map

F8

F0 B

E8

E0 ACC

D8

D0 PSW

C8

C0

B8 IP

B0 P3

A8 IE

A0 P2

98 SCON SBUF

90 P1

88 TCON TMOD TL0 TL1 TH0 TH1

80 P0 SP DPH DPL PCON

Bit Addressable


Special Function Registers

CPU registers:

- ACC : Accumulator.

- B : B register.

- PSW : Program Status Word.

- SP : Stack Pointer.

- DPTR : Data Pointer (DPH, DPL).

Interrupt control:

-IE : Interrupt Enable.

-IP : Interrupt Priority.

I/O Ports:

- P0 : Port 0.

- P1 : Port 1.

- P2 : Port 2.

- P3 : Port 3.


Special Function Registers (cont'd)

TImers:

- TMOD : Timer mode.

- TCON : Timer control.

- TH0 : Timer 0 high byte.

- TL0 : Timer 0 low byte.

- TH1 : Timer 1 high byte.

- TL1 : Timer 1 low byte.

Serial I/O:

- SCON : Serial port control.

- SBUF : Serial data registers.

Other:

- PCON : Power control & misc.


PSW : Program Status Word

CY AC F0 RS1 RS0 OV ---- P

- CY : Carry Flag.

- AC : Auxiliary Carry Flag.

- F0 : Flag 0 (available for user).

- RS1 : Register Select 1.

- RS0 : Register Select 0.

- OV : Arithmetic Overflow Flag.

- P : Accumulator Parity Flag.

RS1 RSO Register BankAddress

0 0 0 00h - 07h

0 1 1 08h - 0Fh

1 0 2 10h - 17h

1 1 3 18h - 1Fh


I/O Ports

- Four 8-bit I/O ports.

- Most have alternate functions.

- Quasi-bidirectional:

Soft pull-up when port latch

contains a 1. Can be used as

inputs (30Kohm average pullup).

Strong pull-up for 2 CPU cycles

during 0 to 1 transitions.


Port Configuration

NMOS2 OSC. PERIODS

Q

PORT PIN

FROM PORT LATCH

PORT PIN

Q FROM PORT LATCH

2 OSC. PERIODS

P1 P2 P3

V C C

V C C

V C C

N

INPUTDATA

READ PORT PIN

C MOS


Port 0

- As an I/O port:

No strong pull-up, outputs act as

open drain.

- As a multiplexed data bus:

Tristate bus with strong pull-ups.

8-bit instruction bus, strobed by PSEN.

Low byte of address bus, strobed by ALE.

8-bit data bus, strobed by WR and RD.

- 3.2 mA outputs (about 8 LSTTL loads).


Port 1

As an I/O port:

Standard quasi-bidirectional.

- Alternate functions:

Only on some derivatives.



Port 2

- As an I/O port:



High byte of address bus for external

program and data memory accesses.



Port 3

- As an I/O port:



Serial I/O - TXD, RXD

Timer clocks - T0, T1

Interrupts - INT0, INT1

Data memory - RD, WR



Counter / Timers

- Two 16-bit Counter/Timers:

Up counters, can interrupt on overflow.

- Counts:

CPU cycles (crystal/12).

External input (max. half CPU rate).

- Four Operation Modes.


Timer Modes

- Timer Mode 0 :

Emulates 8048 counter/timer (13-bits).

8-bit counter (TL0 or TL1).

5-bit prescaler (TH0 or TH1).

- Timer Mode 1 :

Simple 16-bit counter.

- Timer Mode 2 :

8-bit auto-reload.

Counter in TL0 or TL1.

Reload value in TH0 or TH1.

Provides a periodic flag or interrupt.


Timer Modes (cont'd)

- Timer Mode 3 :Splits timer 0 into two 8-bit counter/timers.First counter (TLO) acts like mode 0,without prescaler.Second counter (TH0):

Counts CPU cycles.Uses TR1 (timer 1 run bit) as enable.Uses TF1 (timer 1 overflow bit) as flag.Uses Timer 1 interrupt.

Timer 1 (when timer 0 is in mode 3 ):Counter stopped if in mode 3.Running in mode 0, 1, or 2.Has gate (INT1) and external input (T1), but no flag or interrupt.May be used as a baud rate generator.


Counter/Timer in 16-bit (Mode 1)

Osc. ÷12 Osc.

TL18-bits

TF1 TH18-bits

Interrupt

Control

T1 (Pin)

TR1

Gate

INT1 (Pin)

The Gate input controls whether the Counter runs while gated by the interrupt signal or not.


TMOD : Counter/Timer Mode Register

GATE C/T M1 M0 GATE C/T M1M0

Timer 1 Timer 0- GATE : Permits INTx pin to enable/disable counter.

- C/T : Set for counter operation, reset for timer operation.

- M1, M0 :

00 : Emulate 8048 counter/timer (13-bits).

01 :16-bit counter/timer.

10 : 8-bit auto-reload mode

11 :Timer 0 = two 8-bit timers.

Timer 1 Counting disabled. Timing function allowed. Can be used as Baud Rate generator.


TCON : Counter/Timer Control Register

- TF1, TF0 : Overflow flags for Timer 1 and Timer 0.

- TR1, TR0 : Run control bits for Timer 1 and Timer 0.Set to run, reset to hold.

- IE1, IE0 : Edge flag for external interrupts 1 and 0. *

Set by interrupt edge, cleared when interrupt is processed.

- IT1, IT0 : Type bit for external interrupts. *

Set for falling edge interrupts, reset for 0 level interrupts.

* = not related to counter/timer operation.

TF1 TR1 TF0 TR0 IE1 IT1 IE0IT0


Serial Interface

- Full duplex UART.- Four modes of operation:

Synchronous serial I/O expansion.Asynchronous serial I/O with variable baud rate.Nine bit mode with variable baud rate.Nine bit mode with fixed baud rate.

- 10 or 11 bit frames.- Interrupt driven or polled operation.- Registers:

SCON - Serial port control register.SBUF - Read received data.

- Write data to be transmitted. PCON - SMOD bit.


Serial Interface Modes of Operation

TXD and RXD are the serial output and input pins (Port 3, bits 1 and 0).

Mode 0: Shift Register Mode. Serial data is transmitted/received on RXD. TXD outputs shift clock. Baud

Rate is 1/12 of clock frequency.

Mode 1: 10-bits transmitted or received. Start (0), 8 data bits (LSB first), and a stop bit (1). Baud Rate Clock is variable using Timer 1 overflow or external count input. Can go up to

104.2KHz (20MHz osc.).

Mode 2: 11-bits transmitted or received. Start (0), 8 data bits (LSB first), programmable 9th bit, and stop bit (1). Baud Rate programmable to either 1/32 or 1/64 oscillator frequency (625KHz for 20MHz

osc.).

Mode 3: 11-bit mode. Baud Rate variable using Timer 1 overflow or external input. 104.2 KHz max. (20 MHz osc.).


Multi-Drop Communication

Serial Communication Modes 2 and 3 allow one "Master" 8051 to control several "Slaves":

The serial port can be programmed to generate an interrupt if the 9th data bit = 1.

The TXD outputs of the slaves are tied together and to the RXD input of the master. The RXD inputs of the slaves are tied together and to the TXD ouput of the master.

Each slave is assigned an address. Address bytes transmitted by the master have the 9th bit = 1.

When the master transmits an address byte, all the slaves are interrupted. The slaves then check to see if they are being addressed or not.

The Addressed slave can then carry out the master's commands.


SCON : Serial Control Register

- SM0, SM1 = Serial Mode:

00 = Mode 0 : Shift register I/O expansion.

01 = Mode 1 : 8-bit UART with variable baud rate.

10 = Mode 2 : 9-bit UART with fixed baud rate.

11 = Mode 3 : 9-bit UART with variable baud rate.

- SM2 :

Mode 0 : Not used.

Mode 1 : 1 = Ignore bytes with no stop bit.

Mode 2,3 : 0 = Set receive interrupt (RI) on all bytes.

: 1 = Set RI on bytes where bit 9 = 1.

- REN = Enables receiver.

- TB8 = Ninth bit transmitted (in modes 2 and 3).

- RB8 = Ninth bit received:

Mode 0 : Not used.

Mode 1 : Stop bit.

Mode 2,3 : Ninth data bit.

- TI = Transmit interrupt flag.

- RI = Receive interrupt flag.

SMO SM1 SM2 REN TB8 RB8 TI RI


Interrupt System

- 5 Interrupt Sources (in order of priority):External Interrupt 0.Timer 0.External Interrupt 1.Timer 1.Serial Port.

- Each interrupt type has a separatevector address.

- Each interrupt type can be programmedto one of two priority levels.

- External interrupts can be programmedfor edge or level sensitivity.


IE : Interrupt Enable Register

- EA : Global interrupt enable.

- ES : Serial interface.

- ET1 : Timer 1.

- EX1 : External interrupt 1.

- ET0 : Timer 0.

- EX0 : External interrupt 0.

- 0 = Disabled.

- 1 = Enabled.

EA ---- ---- ES ET1 EX1 ET0 EX0


Interrupt Vector Addresses

Source Address

IE0 03H

TF0 0BH

IE1 13H

TF1 1BH

RI&TI 23H

The 8051 starts execution at 0000H after Reset.


IP: Interrupt Priority Register

- PS : Serial interface.

- PT1 : Timer 1.

- PX1 : External interrupt 1.

- PT0 : Timer 0.

- PX0 : External interrupt 0.

- 0 = Low priority.

- 1 = High priority.

----- ----- ----- PS PT1 PX1 PT0PX0


80C51(CMOS) vs. 8051(NMOS)

·Controlled Power Reduction�·Idle State�·Power down state�

·Power savings in CMOS ports�· General purpose software flags

· Higher speed versions in 80C51 (up to 30MHz)

· Static versions in development


PCON : Power Control Register

- POWER DOWN OPERATION

Setting PD bit stops oscillator.

RAM contents are saved.

Exit via Reset.

Some (newer) 80C51 derivatives allow Power-Down wakeup via Interrupt.

SMOD ---- ---- ---- GF1 GF0 PDIDL


PCON : Power Control Register

- IDLE MODE OPERATION

Setting IDL gates clocks off, leaves oscillator running.

All register and RAM contents are saved.

Interrupt sources remain active:

Serial interface.

External interrupts.

Timers.

Exit with any enabled interrupt or Reset.

- GF0, GF1 are general purpose software flags.

- SMOD serial interface control bit.

Doubles baud rate in modes 1,2, and 3.

- Only SMOD available on NMOS parts.


Power Consumption

Example : for 80C51 at Vcc = 5V.

Mode / Freq. 0.5 MHz 16 MHz

Operating 2.2 mA 20.5 mA

Idle 0.9 mA 5.0 mA

Power Down 50 uA 50 uA


8051 Addressing Modes

There are basically 5 ways of specifying source/destination operand addresses:

1. Particular On-chip Resources:

This includes the Accumulator (A), the Stack Pointer (SP), the Data Pointer (DP), the Program Counter (PC), and the Carry (C). Other On-chip Registers are Memory-mapped while these have special Op-codes.

2. Immediate operands:

The # sign is the designator. These are 8-bits except for DPTR contents (16-bits).

3. Register operands:

Designated as Rn, where n is 0..7. One of the four Register Banks is used (PSW selected).

4. Direct Operands:

From 00 to FF Hex, specifies one of the internal data addresses.

5. Indirect Address:

Designated as @Ri, where i is 0 or 1, uses the contents of R0 or R1 in the selected Register Bank to specify the address. Other form is @A, using Accumulator contents.


Instruction Set : Arithmetic

Mnemonics Operands Bytes/Cycles

ADD A, Rn 1/1

ADDC A, direct 2/1

SUBB A, @Ri 1/1

A, #data 2/1

INC A 1/1

DEC Rn 1/1

direct 2/1

@Ri 1/1

INC DPTR 1/2

MUL AB 1/4

DIV AB 1/4

DA A 1/1


Instruction Set : Logic

Mnemonic Operands Bytes/Cycles

ANL A, Rn 1/1

ORL A, direct 2/1

XRL A, @Ri 1/1

A, #data 2/1

direct, A 2/1

direct, #data 3/2

C, bit 2/2

C, /bit 2/2

CLR A 1/1

CPL C 1/1

bit 2/1


Instruction Set : Logic (cont'd)


RL A 1/1

RLC A 1/1

RR A 1/1

RRC A 1/1

SWAP A 1/1

SETB C 1/1

CLR bit

CPL

2/1


Instruction Set : Data Transfer


MOV A, Rn 1/1

A, direct 2/1

A, @Ri 1/1

A, #data 2/1

Rn, A 1/1

Rn , direct 2/2

Rn, #data 2/1

direct, A 2/1

direct, Rn 2/2

direct, direct 3/2

direct, @Ri 2/2

direct, #data 3/2


Instruction Set : Data Transfer (cont'd)


MOV @Ri, A 1/1

@Ri, direct 2/2

@Ri, #data 2/1

DPTR, #data16 3/2

C, bit 2/1

bit, C 2/2

MOVX A,@DPTR 1/2

@DPTR,A 1/2

A,@Ri 1/2

@Ri,A 1/2


Instruction Set: Data Transfer (cont'd)


MOVC A, @A+DPTR 1/2

A, @A+PC 1/2

PUSH direct 2/2

POP direct 2/2

XCH A, Rn 1/1

A, direct 2/1

A, @Ri 1/1

XCHD A, @Ri 1/1


Instruction Set : Branching


LCALL addr16 3/2

ACALL addr11 2/2

RET - 1/2

RETI - 1/2

LJMP addr16 3/2

AJMP addr11 2/2

SJMP rel 2/2

JMP @A+DPTR 1/2

JZ rel 2/2

JNZ rel 2/2


Instruction Set : Branching (cont'd)


CJNE A, direct, rel 3/2

A, #data, rel 3/2

Rn, #data, rel 3/2

@Ri,#data,rel 3/2

DJNZ Rn, rel 2/2

direct, rel 3/2

NOP - 1/1

JC rel 2/2

JNC rel 2/2

JB bit, rel 3/2

JNB bit, rel 3/2

JBC bit, rel 3/2


The I C BUS

(Inter - Integrated Circuit)

· A 2 wire serial data and control bus

· Implemented with one serial data (SDA) and one clock (SCL) line.

· Unique start and stop conditions.

· Slave selection protocol uses a 7-Bit slave address.

· Bi-directional data transfer.

· Acknowledgement after each byte transferred.

· No limit on the number of bytes transferred.

· Real multimaster capability.

2


I2C Bus Features

· Clock synchronization.

· Arbitration procedure.

· Transmission speed up to 100Khz

· Maximum bus length of 4 meters.

· Maximum drive capacity of 400pF.

· Allows series resistor for IC protection.

· Compatible with most IC technologies (TTL, CMOS,Etc.).


I2C Definitions

MASTER:

· Initiates a transfer by generating start and stop conditions.

· Generates the clock.

· Transmits the slave address.

· Determines data transfer direction.

SLAVE:

· Responds only when addressed.

· Timing is controlled by the clock line.


I2C Hardware Details

· Devices connected to the bus must have an open drain or open collector output for serial clock and data.

· The device must also be able to sense the logic level on these pins.

· All devices must have a common reference ground.

· The serial clock and data lines are connected to VCC through pull up resistors.

· At any given moment the I2C bus is: Idle, in Master transmit mode, or in Master receive mode.


The Open Drain Configurationof I2C Circuits

SCLK1OUT

SCLKIN

DATA1OUT

DATAIN

SCLK2OUT

SCLKIN

DATA2OUT

DATAIN

SDASCL

DEVICE 2DEVICE 1

I2C devices are wire ANDed together.

+VDD

Rp RpPull-upResistors

Serial clock lineSerial data line


Start and Stop Conditions

· A transition of the data line, when the clock line is high, is defined as either a start or a stop condition.

· Both start and stop conditions are generated by bus master.

· The Bus is busy after a start condition.

SDA

SCL

StartCondition

StopCondition

S P

SDA

SCL


Bit Transfer on the I2C Bus

· In normal data transfer, the data line only changes state when the clock is low.

SDA

SCLData linestable:

Data valid

Changeof dataallowed


I2C Address

· Each node has a unique 7 bit address.

· Peripherals usually have fixed and programmable address portions.

· Addresses starting with 0000 or 1111 have special functions.

· 0000000 is a general call address.0 · 0000001 is a null address. · 1111xxxx is reserved for future bus expansion


First Byte Transmitted on the I2C Bus

LSB ACK

7-bit slave address

R/W :0 - Slave will be written by master.1 - Slave will be read by master.

R/W

MSB


Acknowledgement

· Master/slave receivers pull data line low for one clock pulse after reception of a byte.

· Master receiver leaves data line high after receipt of the last byte requested.

· Slave receiver leaves data line high on the byte following the last byte it can accept.


Data Transfer on the I2C Bus

1 2 7 8 9ACK

SCL

SDA

STARTCONDITION

STOPCONDITION

S P3 - 81 2 9ACK

MSB


Possible Data Formats

S SLAVE ADDRESS W A DATA A DATA A

P

· Master Write:

· Master Read:

Acknowledge from slave

Acknowledge from master

No acknowledge from master

S SLAVE ADDRESS R A DATA A DATA NA

P

Acknowledge from slave


I2C Clock Synchronization

· Clock synchronization is used to synchronize arbitrating masters.

· It can also be used as a handshake by a slave device to slow data transfer from a master.

The clock synchronization procedure consists of two algorithms:

1) If the clockline goes low when a master is asserting a high,

the master asserts a low and starts to time out its low clock period.

2) When a master stops asserting a low on the clock line, it waits

until the clockline actually goes high before starting to time the

high period.


I2C-Bus Clock Synchronization Procedure

SCL

CLK 2

CLK 1

Start countinglow period

Wait StateStart counting

high period


Multimaster I2C Systems

Multimaster situations require two additional features of the I2C protocol.

ARBITRATION:

· Arbitration is the procedure by which competing masters decide final control of the bus.

· I2C arbitration does not corrupt the data transmitted by the prevailing master.

Arbitration is performed bit by bit until it is uniquely resolved.

· Arbitration is lost by a master when it attempts to assert a high on the data line and fails..


Arbitration Procedure Between Two Masters

SCL

SDA

DATA1

1 2 3 4 5

DATA2

Transmitter 1 loses arbitration


I2C Family ICs

· Microcontrollers

· Microprocessors

· General Purpose Peripherals

I/O, Memory, Display, DAC, ADC, Clock/Calendar

· Peripherals for Specific Target Martkets

Audio, Telephony, Video


An OpenDesktop Bus Standard

based onI2C


ACCESS.bus .1

DEC has invented an interconnect method for connecting a PC or Workstation to

low speed I/O devices such as:

· Keyboards

· Mouses

· Trackballs

· Tablets

· Low speed printers

· Modems

This interconnect method, known as ACCESS.bus, is based on the I2C serial protocol invented by Philips.


ACCESS.bus .2

ACCESS.bus features:

· 80 KBps Peak Bandwidth

· Hot plugging and unplugging of devices (keyboard, mouse, etc.)

· Up to 14 devices

· Up to 8 Meters (26.4 feet) in length

· Serial, daisy-chained 4-pin cable (2 pins are power and ground). Only ONE device port needed on computer.


ACCESS Bus .3

ACCESS.Bus features:

· Layered 3-layer protocol defined by DEC:

· Physical layer is I2C.

· Base Protocol over I2C defines the structure of I2C messages and defines Control and Status Messages. Also supports auto-addressing and hot plugging.

· Applications Protocol defines message semantics for particular device types.

· Extremely low cost implementation based on off-the-shelf Microcontrollers with I2C such as the Signetics 83/87C751 (used in new DEC workstation ).


ACCESS.Bus .4

· Device address and type recognition is automatic. No drivers have to be loaded.

· Concise protocol. Only 7 standard message types. Fully implemented in the 87C751 with 2K of Program memory.

· ACCESS.Bus is part of DEC's ARC and ACE platforms.

· Fully open and free. No royalties.

· DEC and Signetics will provide Developer's Kit with all information required to to develop applications.

· DEC's TRI/ADD developer program will provide technical support, documentation and updates, technical seminars, and newsletters and assist with marketing support.


ACCESS.bus .5

The closest thing to the ACCESS.bus is Apple's ADB (Apple Desktop Bus). The following is a comparison between ADB and ACCESS.bus:

ADB ACCESS.bus

Hot-Plugging not recommended fully supported

Peak data rate 10 KBits/sec 80 KBits/sec

Daisy-chain limit 3 devices 14 devices

3rd party access Proprietary Open. No royalties

Max. cable length 5 meters 8 meters


Directions from the Core Product

Very SmallPackages

ExtendedI/O

ASIC CellLibrary

I2C SerialBus

EEPROMderivatives

Memory2 to 32 K

EPROM &OTP

Analog-to-Digital

Low PowerLow Voltage

80C51

SpeedUp to 30 MHz


Philips/Signetics 8051 Family

Product Name Process ROM RAM Pins 8-bit Ports Serial I/O Timers Special

8031/51 NMOS 4K 128 40 4 UART 2 Industry Standard

8032/52 NMOS 8K 256 40 4 UART 3 Industry Standard

8XC751 CEPROM 2K 64 24 2+3/8 I2C 1 24 Pin Skinny DIP

8XC752 CEPROM 2K 64 28 2+5/8 I2C 1 8-bit A/D,PWM

8XC31/51 CEPROM 4K 128 40 4 UART 2 20,24, 30MHz

8XCL410 SACMOS 4K 128 40 4 I2C 2 LowVolt/Power (1.8 volts)

80/3C851 EEPROM 4K 128 40 4 UART 2 256 EEPROM

8XC550 CEPROM 4K 128 40 4 UART 2 8-bit A/D, WD

8XC451 CEPROM 4K 128 68 7 UART 2 7 I/O Ports

8XC652 CEPROM 8K 256 40 4 UART,I2C 2 8K ROM, I2C Serial Bus

8XC52 CEPROM 8K 256 40 4 UART 3 Industry Standard

8XC053/054 CEPROM 8K/16k 192 42 4 -- 2 TV Display (OSD), D/A

8XC562 CEPROM 8K 256 68 6 UART 4 8-bit A/D, PWM, WD, T2

8XC552 CEPROM 8K 256 68 6 UART,I2C 4 10-bit A/D, PWM, WD, T2

8XC654 CEPROM 16K 256 40 4 UART,I2C 2 16K ROM, I2C Serial Bus

8XC524 CEPROM 16K 512 40 4 UART, I2C 3 16K, 512 bytes, WD

8XC528 CEPROM 32K 512 40 4 UART,I2C 3 32K ROM, 512 RAM, WD


80C51 Coding:

Ideas and Examples


Reading a Timer "on the Fly"

ReadTimer: MOV ValH,TH0 ;Read initial timer high and low values.

MOV ValL,TL0

MOV A,TH0 ;Read timer high byte again.

CJNE A,ValH,ChkHigh ;Has it changed?

SJMP RTEX ;If not, first sample is OK.

ChkHigh: JB ValL.7,RTEX ;Otherwise, check low byte to see if it

; changed after the original high byte

; sample.

MOV ValH,A ;If it did change, use second high byte

; sample.

RTEX: RET


Compare

The 80C51 has no basic compare instruction. However, the CJNE (compare and jump if not equal) instruction leaves the carry flag set after execution, allowing further magnitude comparisons to be made.

This method works for all variations of CJNE:

CJNE A,direct,rel

CJNE A,#data,rel

CJNE Rn,#data,rel

CJNE @Ri,#data,rel


Compare

Examples of four variations of magnitude comparison:

CJNE A,Value,Test ;Branch if A < Value.

Test: JC LT

CJNE A,Value,Test ;Branch if A >= Value.

Test: JNC GTE

CJNE A,Value,Test ;Branch if A > Value.

SJMP Else

Test: JNC GT

Else: -----

CJNE A,Value,Test ;Branch if A <= Value.

SJMP LTE

Test: JNC LTE


Read-Modify-Write

Most instructions that reference 80C51 port data read the value on the port pins rather than the value in the port latch. However, some instructions read the port latch instead.

1) Arithmetic or logical operations that may alter port values:

ANL port,src

ORL port,src

XRL port,src

INC port

DEC port

DJNZ port,label

3) Instructions that may alter port bits:

MOV bit,C

JBC bit,label

CPL bit

CLR bit

SETB bit


Single Step Under Program Control

The 80C51 does not have any specific built-in facility for allowing a hardware single step operation. However, when a Return from Interrupt instruction is executed, at least one instruction from the originally interrupted routine is always executed before another interrupt may be serviced.

Thus, if execution of RETIs are carefully controlled while an interrupt is pending, a software single step may be effected.


Single Step Under Program ControlThis example uses external interrupt 0 as the means to accomplish the single step. This interrupt is a

good choice because it is the highest priority interrupt . Note: the user program must not write to the IE or IP registers or make use of other interrupt related functions.

;Set up for single step of some user routine:

StartSS: SETB PX0 ;Set INT0 as high priority.SETB IT0 ;Set INT0 to edge triggered mode.JNB INT0,$ ;Wait for a "single step" interrupt to come, JB INT0,$ ; and go.MOV IE,#81h ;Enable INT0 and insure that we are not LJMP UserProg ; interrupted during the following jump.

ExInt0: . . ;Code to dump registers, user program . . ; address, etc.JNB INT0,$ ;Wait for a "single step" interrupt to come, JB INT0,$ ; and go.RETI ;This RETI will allow one user program instruction to

; execute, after which we will return to the INT0 service ; routine.


Pulse Width Measurement

start timer

Problem: measure the width of an input pulse.

?

stop timer

Assumption: use external interrupt 0 for the pulse input. Use timer 0 in gated mode.

Note: to measure pulse low time in this manner, the input must be inverted externally.


Pulse Width Measurement

Setup: MOV TMOD,#09h ;Timer 0 gate on, in mode 1.MOV TCON,#01h ;Set INT0 to edge triggered mode.MOV TH0,#0 ;Clear timer 0 for measurement.MOV TL0,#0SETB TR0 ;Start timer in gated mode.SETB EX0 ;Enable external interrupt 0.SETB EA ;Enable global interrupts.. .. .. .

;External interrupt 0 service routine.ExInt0: CLR TR0 ;Stop timer.

MOV ValH,TH0 ;Save timer value.MOV ValL,TL0MOV TH0,#0 ;Clear timer 0 for measurement.MOV TL0,#0SETB TR0 ;Restart timer.RETI


Pulse Period Measurement

start timer

Problem: measure the period of an input pulse.

?

stop timer

Assumption: use external interrupt 0 for the pulse input.

Note: this method may entail some loss of precision due to the possibility of variable interrupt latency.


Pulse Period Measurement

Setup: (same as previous example, but leave timer gate function turned off)

MOV TMOD,#01h ;Timer 0 in mode 1.

;External interrupt 0 service routine.

ExInt0: CPL TR0 ;Complement the timer run flag. This starts

; and stops the timer on alternate interrupts.

JB TR0,INT0EX ;Exit if timer is running.

MOV ValH,TH0 ;Otherwise sample the timer value.

MOV ValL,TL0

MOV TH0,#0 ;Clear timer so another sample can

MOV TL0,#0 ; be taken.

INT0EX: RETI


Creating an Output Pulse

Problem: create a pulse of known duration on a port pin.

stop pulsestart pulse, timer

timer

Note: the precision of pulses generated using this method will vary depending on the interrupt latency of the timer interrupt.

Assumption: use any spare port bit for the output.


Creating an Output Pulse

Setup: MOV TCON,#0h ;Make sure timer is stopped.

MOV TMOD,#01h ;Set timer to mode 1.

MOV TH0,#HiTime ;Load timer with pulse duration. The value is the MOV TL0,#LoTime ; two's complement of the

number of machine ; cycles to use for the pulse width.

SETB TR0 ;Start timer.

SETB P2.0 ;Start pulse (use CLR for a low going pulse).

;Tiimer 0 interrupt routine.

T0INT: CLR P2.0 ;End of pulse (use SETB for a low going pulse).

CLR TR0 ;Stop timer.

RETI


Programming a PWM Output

Problem: create a PWM output on a port pin.

set timerhigh time

set timerlow time

repeat

Note: the precision of pulses generated using this method will vary depending on the interrupt latency of the timer interrupt.


Programming a PWM Output

T0INT: CLR TR0 ;Stop timer.

CPL P2.0 ;Toggle output bit.

JB P2.0,SetPWMHigh ;Is current phase high or low?

MOV TH0,PWMLowH ;Set PWM low time.

MOV TL0,PWMLowL

SJMP T0EX

SetPWMHigh: MOV TH0,PWMHighH ;Set PWM high time.

MOV TL0,PWMHighL

T0EX: SETB TR0 ;Restart timer.

RETI

Note: for higher frequency pulses, it may be possible to use the timer reload feature (mode 2) to obtain more accurate pulse durations.


Block Memory Move with External Data Memory

0000

FFFF

{

{

Problem: move any random external data memory block of any length to another location.


Block Memory Move

BlockMove: MOV R0,#LOW(FromAddr) ;Initialize 'from' memory pointer.MOV P2,#HIGH(FromAddr)MOV DPTR,#ToAddr ;Initialize 'to' memory pointer.MOV R1,#LOW(ByteCount) ;Initialize byte count.MOV R2,#HIGH(ByteCount)

Loop: MOVX A,@R0 ;Read in a source block byte.MOVX @DPTR,A ;Write byte out to destination block.INC DPTR ;Increment 'to' memory pointer.INC R0 ;Increment 'from' memory pointer.MOV A,R0JNZ L1INC P2

L1: DJNZ R1,Loop ;Decrement byte count andDJNZ R2,Loop ; test for end of block.RET


Implementing a Second UART in Firmware

Often, an application may require a second UART communication function. A simplex (transmit or receive only at any one time) UART can be programmed with the use of one timer.

The transmit routine will simply start the timer, create a start bit, and then send one bit at every timer interrupt, until finally sending the stop bit. The transmit bit may be any unused port bit.

Since the receive routine must sample each bit somewhere in the middle of the bit cell, it starts the timer with a value of a half bit cell when a start is detected. Then, on the first timer interrupt, it verifies the presence of the start bit and changes the timer count to one full bit cell. On every subsequent timer interrupt, one data bit is read, until finally the stop bit is verified. The receive bit must be an external interrupt pin (usually INT0 or INT1).


UART Flow: Start Transmit

Start Transmit

Set up timer for one bit cell time.

Exit

Get byte to be transmitted and set bit count.

Send start bit.


UART Flow: Start Receive

Exit

Start Receive(START bit Interrupt)

Set bit count.

Set up timer for one half bit cell time.


UART Flow: Timer Interrupt

Timer Interrupt

Advance bit count.

Receive?Y

Transmit One Bit

Receive One Bit

N


UART Flow: Transmit One Bit

Transmit One Bit

Exit

Done?

N

YSend STOP bit.

Rotate transmit byte and send next data bit.


UART Flow: Receive One Bit

Exit

Done?

N

Y

Receive One Bit

Look for START(set error flag and abort

if not found).

Get next data bit androtate into received

byte.

Look for STOP(set error flag and abort

if not found).

First bit?N

Y

Change timer setting to one full bit cell time.


80C51 Development Support


Signetics/Ceibo 80C51 Family Development Board

· Supports 80C51 derivative microcontrollers that have external program memory access and serial port.

· Connects to an MS-DOS compatible PC via serial port (PC runs user interface software).

· Line assembler and disassembler.

· Register and memory contents may be viewed and altered.

· Source, memory, register windows.

· 32K user program memory on board.

· Software breakpoints.


80C51 Family Development Board (continued)

· Help screens.

· Symbolic debugger.

· Upload and download of object and hex files.

· Fully documented. User's manual includes experiments for learning the development board and the 80C51 architecture.

· Switches, LEDs, and a potentiometer are included to allow simple experiments to be performed without additional circuitry.


Supported Microcontrollers

· 8031/51

· 8032/52

· 8xC31/51

· 8xC32/52

· 8xC451

· 8xC550

· 8xC552

· 8xC528

· 8xC652/654

· 8xC851

Type 1 (full support via RS-232 to PC)


Supported Microcontrollers (continued)

· 8xC410

· 8xC751

· 8xC752

Type 2 (limited support via I2C bus to type 1 device and PC)

The 8xC751 and 8xC752 have no external program memory capability and do not support user program loading on the DB-51.

The 8xC410 does not have an on-chip UART and must be communicated with via its I2C port. The current version of the DB-51 does not support user program loading on the 8xC410.


Demo Board Block Diagram

Emulation Memory 32K x 8

MonitorEPROM

Type 1 Microcontroller

RS-232 Interface

Type 2 Microcontroller

I2Cbus

MS-DOS Compatible

PC

PC Software(user interface)


Uses for the Demo Board

· Training vehicle for 80C51 product seminars.

· Self training and experimentation system for customers, FAEs, sales, factory, etc.

· Basis for product demonstrations to customers.

· Low cost development support, allows limited hardware and software prototyping.


Emulators

Nohau Corp.

51 E. Campbell Ave.

Campbell, CA 95008

(408) 866-1820

MetaLink Corp.

325 E. Elliot Road, Suite 23

Chandler, AZ 85225

(602) 926-0797

Ceibo Ltd.

105 Gleason Rd.

Lexington, MA 02173

(617) 863-9927

BSO/Tasking

128 Technology Center

P.O.Box 9164

Waltham, MA 02254-9164

(617) 894-7800

Signum Systems

171 E. Thousand Oaks Blvd., #202

Thousand Oaks, CA 91360

(805) 371-4608

And others...


List of Programmer Manufacturer Contacts

Data I/O Corporation

10525 Willows Rd. N.E.

P.O. Box 97046

Redmond, WA 98073-9746

(206) 867-6899

Logical Devices, Inc.

1201 Northwest 65th Place

Ft. Lauderdale, FL 33309

(305) 974-0967

Signetics Co.

(contact nearest sales office)

And many others...

Ceibo Ltd.

105 Gleason Rd.

Lexington, MA 02173

(617) 863-9927

North Valley Designs

1610B Dell Avenue

Campbell, CA 95008

(408) 866-4300

Needham's Electronics

4535 Orange Grove Ave.

Sacramento, CA 95841

(916) 924-8037


8051 Cross Assemblers

Metalink

· macro cross assembler ASM51

· Public Domain! Free on the Signetics BBS

2500 AD software

· Macro assembler

· Cross assembler

· Simulator / debugger

And a host of others...


8051 C Compilers

Archimedes Software, Inc.

2159 Union Street

San Francisco, CA 94123-9923

(415) 567-4010

Avocet Systems, Inc.

120 Union Street

P.O. Box 490 BP

Rockport, Maine 04856

(800) 448-8500

BSO/Tasking

128 Technology Center

PO Box 9164

Waltham, MA 02254-9164

(617) 894-7800

2500 AD Software, Inc.

109 Brookdale Avenue

P.O. Box 480

Buena Vista, CO 81211

(800) 843-8144

Franklin Software, Inc.

888 Saratoga Ave., #2

San Jose, CA 95129

(408) 296-8051

And others...


Microcontroller Support BBS

· Support for Philips/Signetics PLDs and Microcontrollers

· Modem 300/1200/2400 baud, 8-N-1

· Download software:

- Public Domain 80C51 support tools

- Demonstration code

· Send messages to Signetics applications engineers

(800) 451-6644

or

(408) 991-2406

Documents

Philips 8051