73M1903C Demo Board User Manual

Simplifying System IntegrationTM

73M1903C Evaluation Board User Manual

June 12, 2009 Rev. 2.0

UM_1903C_030

73M1903C Evaluation Board User Manual UM_1903C_030

2 Rev. 2.0

© 2009 Teridian Semiconductor Corporation. All rights reserved. Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation. Simplifying System Integration is a trademark of Teridian Semiconductor Corporation. All other trademarks are the property of their respective owners. Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly contained in the Company’s warranty detailed in the Teridian Semiconductor Corporation standard Terms and Conditions. The company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice and does not make any commitment to update the information contained herein. Accordingly, the reader is cautioned to verify that this document is current by comparing it to the latest version on http://www.teridian.com or by checking with your sales representative.

Teridian Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618 TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com

UM_1903C_030 73M1903C Evaluation Board User Manual

Rev. 2.0 3

Table of Contents 1 Introduction ................................................................................................................................... 5

1.1 Safety and ESD Notes .......................................................................................................... 51.2 Evaluation Board Host Interfaces .......................................................................................... 5

2 System Description ....................................................................................................................... 62.1 MAFE Interface ..................................................................................................................... 72.2 73M1903C Register Map ...................................................................................................... 92.3 73M1903C System Initialization ............................................................................................ 92.4 Typical Sample Rate Settings ............................................................................................. 11

3 Hardware Description .................................................................................................................. 123.1 Board Settings: Jumpers and Connectors ........................................................................... 123.2 Board Physical and Operating Information .......................................................................... 16

4 73M1903C Evaluation Board Schematics, PCB Layouts and Bill of Materials .......................... 174.1 Schematic ........................................................................................................................... 174.2 PCB Layouts ....................................................................................................................... 184.3 Bill of Materials ................................................................................................................... 21

5 Ordering Information ................................................................................................................... 236 Related Documentation ............................................................................................................... 237 Contact Information ..................................................................................................................... 23Revision History .................................................................................................................................. 23


4 Rev. 2.0

Figures Figure 1: 73M1903C Evaluation Board ..................................................................................................... 5Figure 2: 73M1903C Evaluation Board Block Diagram ............................................................................. 6Figure 3: 73M1903C in Master or Slave Configuration ............................................................................. 7Figure 4: 73M1903C Daisy Chain Configurations ..................................................................................... 7Figure 5: MAFE Timing Diagram .............................................................................................................. 8Figure 6: Serial Data Timing .................................................................................................................... 8Figure 7: 73M1903C Evaluation Board Jumpers and Connectors ........................................................... 12Figure 8: 73M1903C Evaluation Board PCB Dimensions ....................................................................... 16Figure 9: 73M1903C Evaluation Board Electrical Schematic .................................................................. 17Figure 10: 73M1903C Evaluation Board Silk Screen Top ....................................................................... 18Figure 11: 73M1903C Evaluation Board Top Signal Layer ..................................................................... 19Figure 12: 73M1903C Evaluation Board Layer 2 – Ground Plane ........................................................... 19Figure 13: 73M1903C Evaluation Board Layer 3 – Supply Plane ............................................................ 20Figure 14: 73M1903C Evaluation Board Bottom Signal Layer ................................................................ 20

Tables Table 1: 73M1903C Register Memory Map .............................................................................................. 9Table 2: Control Register Settings for Example Sample Rates ............................................................... 11Table 3: 73M1903C Evaluation Board Connectors ................................................................................. 12Table 4: JP25 Pin Assignments ............................................................................................................. 13Table 5: 73M1903C Evaluation Board Jumper Description ..................................................................... 13Table 6: 73M1903C Evaluation Board Bill of Materials ........................................................................... 21


Rev. 2.0 5

1 Introduction The Teridian Semiconductor Corporation (TSC) 73M1903C Evaluation Board is a Modem Analog Front End Evaluation Board with an on-board DAA for evaluating the 73M1903C device. This device can support up to V.90 modulation and demodulation on typical DSP or CPU systems available in the market. The 73M1903C Evaluation Board incorporates a 73M1903C integrated circuit, a US, CTR21 or World Wide DAA circuit for interfacing with the telephone line and an audio amplifier and speaker for line monitoring during the call progress period. The Evaluation Board supports the evaluation of the 73M1903C Modem Analog Front End device for universal modem applications and interfaces to a general purpose DSP or CPU system.

Figure 1: 73M1903C Evaluation Board

1.1 Safety and ESD Notes THE 73M1903C EVALUATION BOARD IS ESD SENSITIVE! ESD PRECAUTIONS SHOULD BE TAKEN WHEN HANDLING THE EVALUATION BOARD!

1.2 Evaluation Board Host Interfaces The 73M1903C Evaluation Board includes a Modem Analog Front End (MAFE) Interface with a 20-pin right angle connector to connect to a target DSP or CPU system. The Evaluation Board also includes a 3.3 V power receptacle for powering the on board circuits from either the target system or an external power supply.


6 Rev. 2.0

2 System Description Figure 2 shows a block diagram of the 73M1903C Evaluation Board. This section includes descriptions of: • Modem Analog Front End (MAFE) Host System Interface • 73M1903C Register Map • System Initialization

73M1903C

SCLKFSBFSBDSDIN

TXAP1TXAN1TXAP2TXAN2RXAPRXAN DAA

GPIO5(OH)

GPIO4(RING)

SDOUTPHONE

Line

POWER SUPPLY

RESET

POWER AMP Speaker

Volume Control

GP

IO0

GP

IO1

GP

IO2

XTAL

73M1903C Evaluation Board

Figure 2: 73M1903C Evaluation Board Block Diagram


Rev. 2.0 7

2.1 MAFE Interface The Modem Analog Front End (MAFE) Interface is a serial port integrated into the 73M1903C device to interface to a host controller or a DSP. This serial data port is a bi-directional port that is supported by most DSPs available in the market. The MAFE interface requires one end to act as a master and the other as a slave. The 73M1903C device can be configured either as a master or as a slave (refer to Figure 3). Multiple 73M1903C devices can also be daisy chained in a single master and multiple slave configuration (refer to Figure 4).

SCLK

FSB

OSCIN

SDIN

SDOUT

73M1903C(Master)

SckMod "1/0"FSB

SCLK

SDIN

SDOUT

MCLKHOST

SCLK

FSB

OSCIN

SDIN

SDOUT

73M1903C(Slave)

SckMod "x"FSB

SCLK

SDIN

SDOUT

HOST

73M1903C Master Mode 73M1903C Slave Mode

(Master)(Slave)

Figure 3: 73M1903C in Master or Slave Configuration

SCLK

FSB

OSCIN

SDIN

SDOUT

73M1903C(Master)

SckMod "1/0"FSB

SCLK

SDIN

SDOUT

MCLKHOST

SCLK

FSB

OSCIN

SDIN

SDOUT

73M1903C(Slave)

SckMod "x"

FSBD

SCLK

FSB

OSCIN

SDIN

SDOUT

73M1903C(Slave)

SckMod "x"FSB

SCLK

SDIN

SDOUT

HOST

SCLK

FSB

OSCIN

SDIN

SDOUT

73M1903C(Slave)

SckMod "x"

FSBD

Daisy Chain for Master/Slave Mode Daisy Chain for Slave Mode

(Slave) (Master)

Figure 4: 73M1903C Daisy Chain Configurations

Figure 5 and Figure 6 show the MAFE and serial data timing diagrams.


8 Rev. 2.0

TX15 TX14 TX13 TX12 TX11 TX10 TX9 TX8 TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0

RX15 RX14 RX13 RX12 RX11 RX10 RX9 RX8 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0

SCLK

SDOUT

SDIN

FSB

Data Frame with Frame Sync

R/W A6 A5 A4 A3 A2 A1 A0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

0 0 0 0 0 0 0 0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

Control Frame Data format

SDOUT

SDIN

FSB

SCLK

Figure 5: MAFE Timing Diagram

SCLK

SDOUT

SDIN

FSB

TXD

RXD

CTRL-DI

CTRL-DO

TXD

RXD

CTRL-DI

CTRL-DO

Control FrameData Frame

One Sample Period

Control FrameData Frame

SCLK

SDOUT

SDIN

FSB

TXD

RXD

TXD

RXD

CTRL-DI

CTRL-DO

D0=0 D0=1

TXD

RXD

TXD

RXD

D0=0

Hardware Controlled Control Frame

Software Controlled Control Frame

One Sample Period

Figure 6: Serial Data Timing


Rev. 2.0 9

2.2 73M1903C Register Map Table 1 shows the memory map of the addressable registers in the 73M1903C. Each register can be read or written by a host controller or a DSP using the MAFE interface control frame format. All registers and their bits are described in detail in the 73M1903C Data Sheet.

Table 1: 73M1903C Register Memory Map

Address Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x00 0x08 ENFE SelTX2 TXBST1 TXBST0 TXDIS RXG1 RXG0 RXGAIN 0x01 0x00 TMEN DIGLB ANALB INTLB CkoutEn RXPULL SPOS HC 0x02 0xFF GPIO7 GPIO 6 GPIO 5 GPIO 4 GPIO 3 GPIO 2 GPIO 1 GPIO 0 0x03 0xFF DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 0x04 0x00 reserved reserved reserved reserved reserved reserved reserved reserved 0x05 0x00 reserved reserved reserved reserved reserved reserved reserved reserved 0x06 0x50 Rev3 Rev2 Rev1 Rev0 FSBDEn Trim(2) Trim(1) Trim(0) 0x07 0x00 Unused TestPll Tclksel1 Tclksel0 ATX DTX ARX DRX 0x08 0x00 Pseq7 Pseq6 Pseq5 Pseq4 Pseq3 Pseq2 Pseq1 Pseq0 0x09 0x0A Prst2 Prst1 Prst0 Pdvsr4 Pdvsr3 Pdvsr2 Pdvsr1 Pdvsr0 0x0A 0x22 Ichp3 Ichp2 Ichp1 Ichp0 FL Kvco2 Kvco1 Kvco0 0x0B 0x12 Unused Ndvsr6 Ndvsr5 Ndvsr4 Ndvsr3 Ndvsr2 Ndvsr1 Ndvsr0 0x0C 0x00 Nseq7 Nseq6 Nseq5 Nseq4 Nseq3 Nseq2 Nseq1 Nseq0 0x0D 0xC0 Xtal1 Xtal0 LokdetEn ThLk0 Unused Nrst2 Nrst1 Nrst0 0x0E 0x00 Frcvco PwdnPLL Lokdet Unused Unused Unused Unused Unused

2.3 73M1903C System Initialization The following example shows the sequence to follow to bring the 73M1903C device out of reset and to start up after power up.

The 73M1903C device does not have a power on reset circuit. For proper operation, a reset signal must be asserted from the host by pulling the 73M1903C reset pin low for approximately 100 ns or longer after the power is stabilized. The 73M1903C device will be ready to use within 100 µs after the removal of the reset pulse from the reset pin.

RESET the 73M1903 Device 1. Power up the system. 2. Wait for the 3.3 V power to become stable. 3. Hold the 73M1903C RESET pin low for 100 ns or longer then let it go high. 4. Wait for 100 µs for the PLL and OSC to be stabilized. INITIALIZE the 73M1903 Device There are control operating modes; Hardware Control and Software control. In the Hardware Control mode, the serial interface will alternate between data frames and control frames. If synchronization is lost and it is not known whether a data or control frame is being sent, it is necessary to reinitialize the HC mode. Since there isn’t way to initially tell the difference between whether a control frame or data frame is being sent, it is necessary to send a reset of this bit in two consecutive frames, and the procedure for this is as follows: A. Frame Synchronization

1. Reset the HC bit (Register 0x01 bit 0) in a frame sequence.


10 Rev. 2.0

2. Reset the HC bit (Register 0x01 bit 0) in next frame sequence.

At this point, the 73M1903C is guaranteed to be in the software controlled control frame mode. All the MAFE serial data will be data only unless the host requests a control frame by setting the LSB of the TX data to a one by setting bit 0 of data frame. The following frame will then be a control frame. B. Control Frame Generation

Software Controlled Control Frame 1. Mask TXD Bit 0 as 1 to request a subsequent control frame. 2. Write or read the 73M1903C register using the MAFE control data format. 3. Make sure to Mask TXD bit 0 as 0 if the control frame is not needed.

Hardware Controlled Control Frame

1. Mask TXD Bit 0 as 1 to request a subsequent control frame. 2. Set the HC bit (Register 0x01 bit 0) using the MAFE control data format in the next frame.

From this point on, there will be alternating data and control frames. Make sure not to miss this sequence. This is needed to initialize the HC mode.

Example 1: Using the Software Controlled Control Frame:

static const U16 init_afe_config[] = // MUST HAVE Data(LSB=1), Control, Data(LSB=1), Control,.. FRAMES CTRL2|0x00, CTRL2|0x00, // Force to Software controlled control frame CTRL_FRAME, CTRL13|0x00, // Force to Xtal clock CTRL_FRAME, CTRL1|ENFE, // Enable Analog CTRL_FRAME, CTRL2|0x00, // CTRL_FRAME, GPIO|0x00, // CTRL_FRAME, GDIR|0xD0, // GPIO 7,6,4=in 5,3,2,1,0=output CTRL_FRAME, GIE|0x00, CTRL_FRAME, GIP|0x00, CTRL_FRAME, BGTRIM|0x00, CTRL_FRAME, TEST|0x00, CTRL_FRAME, CTRL08|AFE_CTRL08, // Timing chain set up CTRL_FRAME, CTRL09|AFE_CTRL09, CTRL_FRAME, CTRL10|AFE_CTRL10, CTRL_FRAME, CTRL11|AFE_CTRL11, CTRL_FRAME, CTRL12H|AFE_CTRL12H, CTRL_FRAME, CTRL12L|AFE_CTRL12L, CTRL_FRAME, RWB|GPIO, // Delay for 2 sample cycle time to CTRL_FRAME, RWB|GPIO, // let PLL settle before Lockdet CTRL_FRAME, CTRL13|AFE_CTRL13 ; note: CTRL_FRAME = 0x0001

Example 2: Using the Automatic Control Frame (Hardware Controlled Control Frame)

static const U16 init_afe_config[] = // MUST HAVE Dummy Data, Control, Dummy Data, Control,.. FRAMES CTRL2|0x00, CTRL2|0x00, // Force to Software controlled control frame CTRL_FRAME, CTRL13|0x00, // Force to Xtal clock CTRL_FRAME, CTRL1|ENFE|HC, // Enable Analog 0x0000, GPIO|0x00, // Forces DATA to be 0x0000 0x0000, GDIR|0xD0, // GPIO 7,6,4=in 5,3,2,1,0=output


Rev. 2.0 11

0x0000, GIE|0x00, 0x0000, GIP|0x00, 0x0000, BGTRIM|0x00, 0x0000, TEST|0x00, 0x0000, CTRL08|AFE_CTRL08, // Timing chain set up 0x0000, CTRL09|AFE_CTRL09, 0x0000, CTRL10|AFE_CTRL10, 0x0000, CTRL11|AFE_CTRL11, 0x0000, CTRL12H|AFE_CTRL12H, 0x0000, CTRL12L|AFE_CTRL12L, 0x0000, RWB|GPIO, // Delay for 2 sample cycle time to 0x0000, RWB|GPIO, // let PLL settle before Lockdet 0x0000, CTRL13|AFE_CTRL13 ;

2.4 Typical Sample Rate Settings Table 2 shows the register values to set up for each example sample rate using a 24.576 MHz crystal.

Table 2: Control Register Settings for Example Sample Rates

Register (Addr) Sample Rate 7.2 kHz 8 kHz 9.6 kHz 14.4 kHz 16 kHz

CTRL08 (0x08) 0x00 0x00 0x00 0x00 0x00 CTRL09 (0x09) 0x0A 0x0A 0x0A 0x0A 0x08 CTRL10 (0x0A) 0x10 0x11 0x22 0x26 0x17 CTRL11 (0x0B) 0x0D 0x0F 0x12 0x1B 0x18 CTRL12H (0x0C) 0x02 0x00 0x00 0x00 0x00 CTRL12L (0x0D) 0xC1 0xC0 0xC0 0xC0 0xC0


12 Rev. 2.0

3 Hardware Description 3.1 Board Settings: Jumpers and Connectors Figure 7 shows all the connectors and jumpers available on 73M1903C Evaluation Board.

J7

JP12 -- JP23

JP1--JP11

JP25

JS1

J6

J4

J5JP24

J1J3

J2

Figure 7: 73M1903C Evaluation Board Jumpers and Connectors

Table 3 lists the Evaluation Board connectors. JS1 is the main connector for interfacing to a host processor or DSP board. The pins of this connector are configurable by jumper settings (JP1 to JP24). Table 5 describes the details of the jumper settings. J6 is a modular connector for connection to the telephone line and J7 is for power connection from the main board or from an external power supply. JP25 is an alternative MAFE interface connector whose pin assignments are show in Table 4.

Table 3: 73M1903C Evaluation Board Connectors

Schematic and PCB Reference Name Description

JS1 CONN SOCKET 10X2 20-pin connector to interface the 73M1903C Evaluation Board to a host controller main board.

J6 RJ-11 Telephone line connector. J7 3.3V external supply Plug for connecting external 3.3 V DC power supply.

JP25 HEADER 5X2 10 pin interface connector / MAFE test points.


Rev. 2.0 13

Table 4: JP25 Pin Assignments

Pin# Name Pin# Name 1 NC (SCLK in slave mode) 6 SCLK 2 RINGD 7 AFEIN 3 HOOK 8 AFEOUT 4 FSB 9 RESET 5 FSBD 10 GND

Table 5: 73M1903C Evaluation Board Jumper Description


JP1 Jumper Strap

Two-pin header that allows JS1 pin 1 to be assigned as FSBD. SHUNT: JS1 pin1 = FSBD OPEN: JS1 pin 1 is floating

JP2 Jumper Strap

Two-pin header that allows JS1 pin 4 to be assigned as AFEIN. SHUNT: JS1 pin4 = AFEIN OPEN: JS1 pin 4 is controlled by JP13

JP3 Jumper Strap

Two-pin header that allows JS1 pin 5 to be assigned as AFEOUT. SHUNT: JS1 pin 5 = AFEOUT OPEN: JS1 pin 5 is floating

JP4 Jumper Strap

Two-pin header that allows JS1 pin 7 to be assigned as FS. SHUNT: JS1 pin 7 = FS OPEN: JS1 pin 7 is controlled by JP15

JP5 Jumper Strap

Two-pin header that allows JS1 pin 9 to be assigned as FS. SHUNT: JS1 pin 9 = FS OPEN: JS1 pin 9 is controlled by JP16

JP6 Jumper Strap

Two-pin header that allows JS1 pin 11 to be assigned as AFEOUT. SHUNT: JS1 pin11 = AFEOUT OPEN: JS1 pin 11 is floating

JP7 Jumper Strap

Two-pin header that allows JS1 pin 15 to be assigned as AFEIN. SHUNT: JS1 pin 15 = AFEIN OPEN: JS1 pin 15 is controlled by JP19

JP8 Jumper Strap

Two-pin header that allows JS1 pin 16 to be assigned as AFEOUT. SHUNT: JS1 pin 16 = AFEOUT OPEN: JS1 pin 16 is floating

JP9 Jumper Strap

Two-pin header that allows JS1 pin 17 to be assigned as AFEIN. SHUNT: JS1 pin 17 = AFEIN OPEN: JS1 pin 17is controlled by JP20

JP10 Jumper Strap

Two-pin header that allows JS1 pin 18 to be assigned as FS. SHUNT: JS1 pin 18 = FS OPEN: JS1 pin 18 is floating

JP11 Jumper Strap

Two-pin header that allows JS1 pin 20 to be assigned as digital signal ground.

SHUNT: JS1 pin 20 =GND OPEN: JS1 pin 20 is floating

JP12 Jumper Strap

Two-pin header that allows JS1 pin 2 to be assigned as VCCD (3.3 V Digital supply).

SHUNT: JS1 pin 2 = VCCD OPEN: JS1 pin 2 is floating


14 Rev. 2.0


JP13 Jumper Strap

Two-pin header that allows JS1 pin 4 to be assigned as RESET. SHUNT: JS1 pin 4 = RESET OPEN: JS1 pin 4 is controlled by JP2

JP14 Jumper Strap

Two-pin header that allows JS1 pin 6 to be assigned as SCLK. SHUNT: JS1 pin 6 = SCLK OPEN: JS1 pin 6 is floating

JP15 Jumper Strap

Two-pin header that allows JS1 pin 7 to be assigned as RESET. SHUNT: JS1 pin 7 = SCLK OPEN: JS1 pin 7 is controlled by JP4

JP16 Jumper Strap

Two-pin header that allows JS1 pin 9 to be assigned as RINGD. SHUNT: JS1 pin 9 = RINGD OPEN: JS1 pin 9 is controlled by JP5

JP17 Jumper Strap

Two-pin header that allows JS1 pin 10 to be assigned as HOOK. SHUNT: JS1 pin 10 = HOOK OPEN: JS1 pin 10 is floating

JP18 Jumper Strap

Two-pin header that allows JS1 pin 13 to be assigned as HOOK. SHUNT: JS1 pin 13 = HOOK OPEN: JS1 pin 13 is floating

JP19 Jumper Strap

Two-pin header that allows JS1 pin15 to be assigned as RINGD. SHUNT: JS1 pin 15 = RINGD OPEN: JS1 pin 15 is controlled by JP7

JP20 Jumper Strap

Two-pin header that allows JS1 pin 17 to be assigned as SCLK. SHUNT: JS1 pin 17 = SCLK OPEN: JS1 pin 17 is controlled by JP9

JP21 TESTB Two-pin header that selects factory test. This pin must be left open for normal operation.

JP22 CLKMODE Two-pin header that selects the 73M1903C Clock Mode. SHUNT: 73M1903C 32 clock per frame OPEN: 73M1903C continuous clock mode

JP23 Jumper Strap

Two-pin header to select Slave mode. SHUNT: 73M1903C MASTER configuration. (R8 must be depopulated) OPEN: 73M1903C SLAVE configuration (R8 must be populated)

JP24 Jumper Strap

Two-pin header to enable Daisy Chaining. SHUNT: 72M1903C FSBD signal is connected to JP25 pin3 and

JS1 pin through JP1 (Daisy Chain enable) OPEN: 73M1903C FSBD pin is isolated (No Daisy Chain)

J1, J2, J3 Speaker Volume control

Three-pin header for selecting the line monitor speaker volume.

Manual volume control: J1 J2 J3 Volume Control 1-2 don’t care don’t care Shutdown (MUTE)

open 1-2 1-2 6 db Amp gain open 1-2 open 12 db Amp gain open open 1-2 18 db Amp gain open open open 23.4 db Amp gain


Rev. 2.0 15


Software volume control by the 73M1903C GPIO: The 73M1903C GPIO 0, 1 and 2 must be configured as output). J1(2-3), J2(2-3), J3(2-3)

GPIO2 GPIO1 GPIO0 Volume Control

Low don’t care don’t care Shutdown (MUTE) High Low Low 6 db Amp gain High Low High 12 db Amp gain High High Low 18 db Amp gain High High High 23.4 db Amp gain

J4 Ring Detector Output

Three-pin header that selects the Ring Detector output to connect to either GPIO4 of the 73M1903C or to a Host CPU GPIO through JS1 or JP25.

1-2: Ring Detector output is fed to 73M1903C GPIO4 (GPIO4 must be configured as an input).

2-3: Ring detector output is directed to a host controller through either JS1 or JP25.

J5 Off-hook Control

Three-pin header that selects the Off-hook control by either 73M1903C GPIO5 or by a Host CPU GPIO through JS1 or JP25.

1-2: Off-hook is controlled by 73M1903C GPIO5 (GPIO5 must be configured as an output).

2-3: Off-hook is controlled by a host output through either JS1 or JP25.


16 Rev. 2.0

3.2 Board Physical and Operating Information

PWR

RJ11

20 P CONN

TRANS

SPK

4.00

2.15

0.69

0.62

1.17 1.18

0.27

0.35

0.33

0.20 0.15

Figure 8: 73M1903C Evaluation Board PCB Dimensions

PCB Dimensions

• Size 4.00 x 2.15” (101.60 x 54.60 mm) • Height with components and solder 0.65” (16.5 mm)

Environmental

• Operating Temperature -40 °C to +85 °C ( crystal oscillator function is affected outside –10 °C to +60 °C range)

• Storage Temperature -65 °C to 150 °C Power Supply

• DC Input Voltage (powered from DC supply) 3.3 VDC ± 0.5 V • Supply Current 25 mA (off-hook at room temperature) typical

UM_1903C_030 73M1903C Evaluation Board User’s Manual

Rev. 2.0 17

4 73M1903C Evaluation Board Schematics, PCB Layouts and Bill of Materials 4.1 Schematic

HOOK

AFEOUTSCLK

+C19

3.3UFC22

0.1UF

C18

0.1UF

- +

U4

HD04

3

1

4

2

VCCD

R21 150K

JS1 CONN SOCKET 10X23M 5120-B7A2JL

22

44

66

88

1010

1212

1414

11

33

55

77

99

1111

1313

1515

1616

1717

1818

1919

2020

VCCA

VCCD

RINGD

RINGD

J7

POWER CONNECTOR

O1

I3

S2

R6 150K

TP15TIP

1

TP16

RING

1

RESET

TP2RXAN 1

TP4TXAN2

1

TP5TRAN1

1

TP14

TRAN2

1

TP13RXAP

1

TP10TXAP2

1

JP13

SCLK

FS

AFEOUTRESET

AFEIN

FSBD

C28

0.47UF 200V

C13.082UF

C27 0.47UF 200V

R1520K

R8 4.7K NCAFEIN

Slave mode: Populate R8 w ith a4.7K resistorMaster mode: Do not populate R8

Slave mode: Open JP23Master mode: Shunt JP23

VCCD

E1P3100SCTECCORSIDACTOR

JP18

R29

20K

F1TR600-150RAYCHEMPOLYSWITCH

CID

cou

plin

g

DEFAULT SETTING:Shunt JP7, JP8, JP10, JP11, JP20, JP22

R33 9.1K

R49

9.1K

Of f hook Control

RINGB

HOOK

RING Detection

JP19

This version supports:---Ring Detection---Caller ID

D4

1N400121

HOOK

J6

RJ-11123456

SCLKMODEopen

OPTIONS:JS 1 - Redw ood 5 Connector 20 pin Rt. angle socketShunt JP7,JP8, JP10, JP11, JP20, JP22 and install R48, R49.Use Sumida MIT 4033 TransformerEnergy ring detection: Remove U3, D4, D2, D3, R29, R33 andreplace C25 and C26 w ith 0.22uF

MODE0open

R11 374

R20 374

C7 150n

+C1

3.3UF

C3

0.1UF

JP7

+

C15 10UF

C20 0.1UF

D1

BZT52C15-7

Slave mode: Shunt JP14, JP1Master mode: Open JP14, JP1

JP16

R504.7k

T1

TRANSFORMER_0Sumida

3A 2A

4A 1A1B

2B3B

4B

R52 0

R51

0

VCCD

JP17

VCCA

Slave mode: Populate R31 w ith 0 OhmMaster mode: Do not populate R31

JP10

U2

73M1903C-32_0

VN

D1

VP

D2

GP

IO0

3

GP

IO1

4

GP

IO2

5

GP

IO3

6

FS

7

SC

LK8

VPA9

TXAN110

TXAN211

TXAP112

TXAP213

RXAN14

RXAP15

VNA16

VN

PLL

17X

OU

T18

XIN

19V

PP

LL20

FS

BD

21V

ND

22G

PIO

423

GP

IO5

24

VPD25 RST26 TEST27 SCKMODE28 SDIN29 GPIO630 GPIO731 SDOUT32

C6 150n

C23 150n

JP11

J2HEADER3

123

J3HEADER3

123

J1HEADER3

123

R5 4.7K

R9 4.7K

JP15

TP11GND

1

Q2MMBTA42L

OFFHOOKRING DETECTOR

C29

0.047u

SHUTDOWN

JP3

GAIN1 GAIN0

JP4

Manual volume control: J1 (1-2) , J2/J3(don't care):Shutdow n (MUTE) J1(open), J2((1-2),J3(1-2) : 6db Amp gain J1(open), J2((1-2),J3(open) : 12db Amp gain J1(open), J2((open),J3(1-2) : 18db Amp gain J1(open), J2((open),J3(open) : 23.4db Ampgain.

Softw are Volume control: J1(2-3), J2(2-3) andJ3(2-3).

JP24

R10 49.9

JP5

JP1

R30 56K

TP1GPIO0

1

C12

1uF

C40.1uF

JP6

C5 1uF

C9

10uF

R1 120KR2 120K

C11

220pF

R3 120KU1

TPA2001D1

INP1

INN2

SHDN3

GAIN04

GAIN15

PVDD6

OUTP7

PGND8

PGND9OUTN10PVDD11VDD12ROSC13COSC14AGND15BYP16

C21uF

C10

1uF

LS1

INTERVOXBST1811P-06

12

3

RING path

R12

120K

C8

0.1uF

CID coupling

D3

22V

2 1

VCCD

D2

22V21

VCCD

VCCA

SLV_CLK

JP9R48 100

JP20

R2418

Q1

FZT605CT

1

32 4+

C16

10UF 25V

TP3TXAN1

1

TP12TXAP1

1

R2262K

R1733K

+ C243.3UF 25V

SLV_CLK

JP14

C143.3UF

C173.3uF Dial Pulse Shaper

This block must beisolated from the main power/ground plane.

VCCD

FS

U3

TLP627

12

43

FS

JP8

SCLK

TP9 GPIO61TP6 GPIO71

VCCD

JP12

JP21GATED SCK

12

JP22MODE 0

12

VCCD

TP8RESET1

Y1 24.576M

C25

33PF

C26

22PF

FSBD

L4

NLC322522T-4R7M

JP2

TP7FSBD

1

L1NLC322522T-4R7ML2

NLC322522T-4R7M

L3

NLC322522T-4R7M

J5

HEADER3

123

U5TLP627

12

43

J4

HEADER3

1 2 3

Default setting: Shunt J23 and remove R8.

TP18

GND

1

R13 210

R16

210

Default setting:Do not populate R52

R4 48.7K

R14150K

R23

48.7K

R18 150K

C21 150n

JP23

R19 49.9

JP25

HEADER 5X2

1 23 45 67 89 10

Figure 9: 73M1903C Evaluation Board Electrical Schematic


18 Rev. 2.0

4.2 PCB Layouts

Figure 10: 73M1903C Evaluation Board Silk Screen Top


Rev. 2.0 19

Figure 11: 73M1903C Evaluation Board Top Signal Layer

Figure 12: 73M1903C Evaluation Board Layer 2 – Ground Plane


20 Rev. 2.0

Figure 13: 73M1903C Evaluation Board Layer 3 – Supply Plane

Figure 14: 73M1903C Evaluation Board Bottom Signal Layer


Rev. 2.0 21

4.3 Bill of Materials Table 6 provides the bill of materials for the 73M1903C Evaluation Board schematic provided in Figure 9.

Table 6: 73M1903C Evaluation Board Bill of Materials

Item Qty. Reference Part Manufacturer 1 4 C1, C14, C17, C19 3.3 µF Panasonic 2 4 C2, C5, C10, C12 1 µF Panasonic 3 6 C3, C4, C8, C18, C20, C22 0.1 µF Panasonic 4 4 C6, C7, C21, C23 150 nF (0.15 µF) Panasonic 5 2 C9,C15 10 µF Panasonic 6 1 C11 2 nF (0.002 µF) Panasonic 7 1 C13 0.082 µF Panasonic 8 1 C16 3.3 µF 16 V / 25 V Kemet 9 1 C24 10 µF 16 V / 25 V Panasonic

10 1 C25 33 pF Panasonic 11 1 C26 22 pF Panasonic 12 2 C27, C28 0.47 µF 250 V UTC 13 1 C29 0.047 µF 50 V Panasonic 14 2 D1 15 V / MMSZ15T1 On Semiconductor 15 2 D3, D2 22 V/ MMSZ5251BDICT Diodes 16 1 D4 S1G Diodes 17 1 E1 P3100SC Teccor 18 1 F1 TR600-150 Raychem 19 24 JP1 – JP24 2 pin HEADER Sullin 20 1 JP25 HEADER 5X2 Sullin 21 1 JS1 CONN SOCKET 10x2 3M 22 5 J1, J2, J3, J4, J5 3 pin HEADER Sullin 23 1 J6 RJ-11 AMP/Tyco 24 1 J7 power connector Switchcraft 25 1 LS1 Speaker/AT-2308 Intervox 26 4 L1, L2, L3, L4 NLC322522T-4R7M TDK 27 1 Q1 FZT605 Zetex Ind. 28 1 Q2 MMBTA42 On Semiconductor 29 4 R1, R2, R3, R12, 120 kΩ Panasonic 30 2 R23, R4 48.7 kΩ Panasonic 31 3 R5, R9, R50 4.7 kΩ Panasonic 32 4 R6, R14, R18, R21 150 kΩ Panasonic 33 2 R19, R10 49.9 Ω Panasonic 34 2 R11, R20 374 Ω Panasonic 35 2 R13, R16 210 Ω Panasonic 36 2 R15,R29 20 kΩ Panasonic 37 1 R17 33 kΩ Panasonic 38 1 R22 62 kΩ Panasonic 39 1 R24 18 Ω ½ W Panasonic 40 2 R33, R49 9.1 kΩ Panasonic 41 1 R30 56 kΩ Panasonic 42 1 R48 100 Ω Panasonic


22 Rev. 2.0

Item Qty. Reference Part Manufacturer 44 1 R51, R52 0 Ω Panasonic 45 17 TP1 – TP18 Test point Sullin 46 1 T1 EMIT4033L Sumita 47 1 U1 TPA2001D1 TI 48 1 U2 73M1903C-32 Teridian 49 2 U3, U5 TLP627 Toshiba 50 1 U4 H04 Diodes 51 1 Y1 24.576 MHz ECS inc


Rev. 2.0 23

5 Ordering Information Part Description Order Number 73M1903C Evaluation Board with worldwide and 600 Ω termination 73M1903C-EVM

6 Related Documentation The following 73M1903C documents are available from Teridian Semiconductor Corporation: 73M1903C Data Sheet 7 Contact Information For more information about Teridian Semiconductor products or to check the availability of the 73M1903C contact us at: 6440 Oak Canyon Road Suite 100 Irvine, CA 92618-5201 Telephone: (714) 508-8800 FAX: (714) 508-8878 Email: [email protected] For a complete list of worldwide sales offices, go to http://www.teridian.com. Revision History Revision Date Description 1.0 11/12/2004 First release. 2.0 6/12/2009 Revised in new format.

http://www.teridian.com/

Documents

73M1903C Demo Board User Manual