6.Verilog Shift Register

SNSCT ME-VLSI 2011-2013

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EX:NO:6

DATE:4.11.11

DESIGN AND SIMULATION OF SHIFT REGISTER

USING VERILOG CODE

AIM

To write the Verilog code for the design and simulation of shift register.

TOOLS REQUIRED

Xilinx ISE, modelsim 5.7

THEORY

SERIAL-IN PARALLEL-OUT (SIPO)

The operation is as follows. Lets assume that all the flip-flops (FFA to FFD) have just been RESET (CLEAR input) and that all the outputs QA to QD are at logic level "0" i.e,

no parallel data output. If a logic "1" is connected to the DATA input pin of FFA then on the

first clock pulse the output of FFA and therefore the resulting QA will be set HIGH to logic

"1" with all the other outputs still remaining LOW at logic "0". Assume now that the DATA

input pin of FFA has returned LOW again to logic "0" giving us one data pulse or 0-1-0.

The second clock pulse will change the output of FFA to logic "0" and the output of

FFB and QB HIGH to logic "1" as its input D has the logic "1" level on it from QA. The logic

"1" has now moved or been "shifted" one place along the register to the right as it is now at

QA. When the third clock pulse arrives this logic "1" value moves to the output of FFC (QC)

and so on until the arrival of the fifth clock pulse which sets all the outputs QA to QD back

again to logic level "0" because the input to FFA has remained constant at logic level "0".

SERIAL-IN SERIAL-OUT (SISO)

This shift register is very similar to the SIPO, except were the data was read directly

in a parallel form from the outputs QA to QD, this time the data is allowed to flow straight

through the register and out of the other end. Since there is only one output, the DATA leaves

the shift register one bit at a time in a serial pattern, hence the name Serial-in to Serial-Out

Shift Register or SISO.

The SISO shift register is one of the simplest of the four configurations as it has only

three connections, the serial input (SI) which determines what enters the left hand flip-flop,

the serial output (SO) which is taken from the output of the right hand flip-flop and the

sequencing clock signal (Clk). The logic circuit diagram below shows a generalized serial-in

serial-out shift register.


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FIG 6.1 4-BIT SERIAL-IN TO PARALLEL-OUT SHIFT REGISTER

FIG 6.2 4-BIT SERIAL-IN TO SERIAL-OUT SHIFT REGISTER


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PARALLEL-IN SERIAL-OUT (PISO)

The Parallel-in to Serial-out shift register acts in the opposite way to the serial-in to

parallel-out. The data is loaded into the register in a parallel format i.e. all the data bits enter

their inputs simultaneously, to the parallel input pins PA to PD of the register. The data is then

read out sequentially in the normal shift-right mode from the register at Q representing the

data present at PA to PD. This data is outputted one bit at a time on each clock cycle in a serial

format. It is important to note that with this system a clock pulse is not required to parallel

load the register as it is already present, but four clock pulses are required to unload the data.

This shift register converts parallel data, such as an 8-bit data word into serial format,

it can be used to multiplex many different input lines into a single serial DATA stream which

can be sent directly to a computer or transmitted over a communications line.

PARALLEL-IN PARALLEL-OUT (PIPO)

The final mode of operation is the Parallel-in to Parallel-out Shift Register. This type

of register also acts as a temporary storage device or as a time delay device similar to the

SISO configuration. The data is presented in a parallel format to the parallel input pins PA to

PD and then transferred together directly to their respective output pins QA to QA by the same

clock pulse. Then one clock pulse loads and unloads the register. This arrangement for

parallel loading and unloading is shown below.

PROCEDURE

SIMULATION PROCEDURE

1. To start the programs click the modelsim software.

2. The main page is opened; click the file option to create a new source in Verilog.

3. After the program is typed, it is saved in a name with extension.verilog.

4. Then the program is compiled and errors are checked.

5. After that it is simulated.

6. Then the program is viewed and the signal option is clicked from the view

menu and the input signals are given.

7. Then in the edit option, force is selected and the values are given.

8. Finally add-wave is clicked view the result waveform.


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FIG 6.3 4-BIT PARALLEL-IN TO SERIAL-OUT SHIFT REGISTER

FIG 6.4 4-BIT PARALLEL-IN TO PARALLEL-OUT SHIFT REGISTER


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SYNTHESIS PROCEDURE

1. In the Xilinx, open a new project and give the file name.

2. Select Verilog module from XC3S400-4pq208.

3. Type the program and create new source.

4. Select implementation constraint file and give the file name.

5. Then click assign package pin (run) from user constrains.

6. Give the pin location and save the file.

7. Run the synthesis XST, implement design and generate program file

sequentially.

8. Select program and wait until it gets succeed.

9. Give the input and observe the output in the Xilinx kit.

D FLIP FLOP

PROGRAM

module dff (d,clk,q);

input d;

input clk;

output q;

reg q;

always@(posedge clk)

q


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Fig 6.5 RTL Schematic of SIPO


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Fig 6.6 wave form of SIPO

Fig 6.7 RTL Schematic of SISO


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Fig 6.8 wave from of SISO


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SERIAL-IN PARALLEL-OUT (SIPO)

PROGRAM

module sipo(s4,s3,s2,s1,s0,clk);

input s0,clk;

inout s1,s2,s3;

output s4;

dff dff1(s0,clk,s1);




end module

SERIAL-IN SERIAL-OUT (SISO)

PROGRAM

module siso(q,si,clk);

input si,clk;

output q;

wire s0,s1,s2;

dff dff1 (s1,clk,s0);

dff dff2 (so,clk,s1);

dff dff3 (s1,clk,s2);

dff dff4 (s2,clk,q);

end module


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Fig 6.9 RTL schematic of PISO

Fig 6.10 wave form of PISO


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PARALLEL-IN SERIAL-OUT (PISO)

PROGRAM

module piso(q0,q1,q2,q3,a,c,d,e,s,l,clk);

input s,l,clk;

input a,c,d,e;

inout q0,q1,q2,q3;

wire b0,b1,b2;

wire w0,w1,w2,w3,w4,w5;

assign w0 = q0 & s;

assign w1 = l & e;

assign b0 = w0 | w1;

assign w2 = q1 & s;

assign w3 = c & l;


assign w4 = q2 & s;

assign w5 = d & l;


dff d1 (a,clk,q0);

dff d2 (b0,clk,q1);

dff d3 (b1,clk,q2);

dff d4 (b2,clk,q3);

end module


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Fig 6.11 RTL schematic of PIPO

Fig 6.12 wave form of PIPO


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PARALLEL-IN PARALLEL-OUT (PIPO)

PROGRAM

module pipo(q1,q2,q3,q4,s1,s2,s3,s4,clk);

input s1,s2,s3,s4,clk;

output q1,q2,q3,q4;

dff dff1 (s1,clk,q1);

dff dff2(s2,clk,q2);



end module

RESULT

Thus the Verilog code for shift register s designed and simulated.

Documents

6.Verilog Shift Register