600 MHz Dual Integrated DCL with PPMU, VHH Drive ... · and active load (DCL), four quadrant, per pin, parametric measurement unit (PPMU). It has VHH drive capability per chip to

600 MHz Dual Integrated DCL with PPMU, VHH Drive Capability, Level Setting DACs,

and On-Chip Calibration Engine

Data Sheet ADATE318

Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

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FEATURES 600 MHz/1200 Mbps data rate 3-level driver with high-Z and reflection clamps Window and differential comparators ±25 mA active load Per pin PPMU with −2.0 V to +6.5 V range Low leakage mode (typically 4 nA) Integrated 16-bit DACs with offset and gain correction High speed operating voltage range: −1.5 V to +6.5 V Dedicated VHH output pin range: 0.0 V to 13.5 V 1.1 W power dissipation per channel Driver

3-level voltage range: −1.5 V to +6.5 V Precision trimmed output resistance Unterminated swing: 200 mV minimum to 8 V maximum 725 ps minimum pulse width, VIH − VIL = 2.0 V

Comparator Differential and single-ended window modes >1.2 GHz input equivalent bandwidth

Load ±25 mA current range

Per pin PPMU (PPMU) Force voltage/compliance range: −2.0 V to +6.5 V 5 current ranges: 40 mA, 1 mA, 100 μA, 10 µA, 2 µA External sense input for system PMU Go/no-go comparators

Levels Fully integrated 16-bit DACs On-chip gain and offset calibration registers and

add/multiply engine Package

84-lead 10 mm × 10 mm LFCSP (0.4 mm pitch)

APPLICATIONS Automatic test equipment Semiconductor test systems Board test systems Instrumentation and characterization equipment

GENERAL DESCRIPTION The ADATE318 is a complete, single-chip ATE solution that performs the pin electronics functions of driver, comparator, and active load (DCL), four quadrant, per pin, parametric measurement unit (PPMU). It has VHH drive capability per chip to support flash memory testing applications and integ-rated 16-bit DACs with an on-chip calibration engine to provide all necessary dc levels for operation of the part.

The driver features three active states: data high, data low, and terminate mode, as well as a high impedance inhibit state. The inhibit state, in conjunction with the integrated dynamic clamps, facilitates the implementation of a high speed active termination. The output voltage capability is −1.5 V to +6.5 V to accommodate a wide range of ATE and instrumentation applications.

The ADATE318 can be used as a dual, single-ended drive/ receive channel or as a single differential drive/receive channel. Each channel of the ADATE318 features a high speed window comparator as well as a programmable threshold differential comparator for differential ATE applications. A four quadrant PPMU is also provided per channel.

All dc levels for DCL and PPMU functions are generated by 24 on-chip 16-bit DACs. To facilitate accurate levels programming, the ADATE318 contains an integrated calibration function to correct gain and offset errors for each functional block. Correction coefficients can be stored on chip, and any values written to the DACs are automatically adjusted using the appropriate correction factors.

The ADATE318 uses a serial programmable interface (SPI) bus to program all functional blocks, DACs, and on-chip calibration constants. It also has an on-chip temperature sensor and over/undervoltage fault clamps for monitoring and reporting the device temperature and any output pin or PPMU voltage faults that may occur during operation.

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ADATE318 Data Sheet

Rev. B | Page 2 of 80

TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Functional Block Diagram .............................................................. 3 Specifications ..................................................................................... 4

SPI Timing Details ..................................................................... 22 Absolute Maximum Ratings .......................................................... 27

Thermal Resistance .................................................................... 27 ESD Caution ................................................................................ 27

Pin Configuration and Function Descriptions ........................... 28 Typical Performance Characteristics ........................................... 31 SPI Interconnect Details ................................................................ 49 Use of the SPI BUSY Pin ................................................................ 50 Reset Sequence and the RST Pin .................................................. 51 SPI Register Definitions and Memory Map ................................ 52

Control Register Details ................................................................ 55 Level Setting DACs ......................................................................... 63

DAC Update Modes ................................................................... 63 DAC Transfer Functions ........................................................... 67 Gain and Offset Correction ...................................................... 68 X2 Registers .................................................................................. 68 Sample Calculations of m and c ............................................... 68

Power Supply, Grounding, and Decoupling Strategy ................ 70 User Information and Truth Tables ............................................. 71

Alarm Functions ......................................................................... 72 PPMU External Capacitors ....................................................... 72 Temperature Sensor ................................................................... 72 Default Test Conditions ............................................................. 73

Detailed Functional Block Diagrams ........................................... 74 Outline Dimensions ....................................................................... 80

Ordering Guide .......................................................................... 80

REVISION HISTORY 7/2017—Rev. A to Rev. B Changes to Table 13 ........................................................................ 26 Changes to Figure 119 .................................................................... 57 Updated Outline Dimensions ....................................................... 80 Changes to Ordering Guide .......................................................... 80

7/2011—Rev. 0 to Rev. A Updated Outline Dimensions ....................................................... 80

4/2011—Revision 0: Initial Version

Data Sheet ADATE318


FUNCTIONAL BLOCK DIAGRAM

OVDH

OVDL

TO ALARM(HIGH/LOW

VOLTAGE FAULT)

OVER-VOLTAGE

VOH0

VOL0

PPMUGO/NO-GO

THERM

TO ALARM(PPMU HIGH/LOW

CLAMP FAULT)

OUT

PPMU

ADATE318

S F

PPMU_VIN0

VCH0VCL0

VCH0VCL0

VCOM0

100Ω

100Ω

50Ω 50Ω

IOH0

VIH0VIT/VCOM0

VIL0

MUX

MUX

DRIVER 50Ω

ACTIVELOAD

+

–

VOH0

VOL0

NWC

NWC

DIFF CH0 ONLYCOMPARATOR

DAT0

RCV0

COMMON

CHANNEL 0

CHANNEL 1(SAME AS CHANNEL 0 EXCEPT WHERE NOTED)

VHHDRIVER

VHHVIH0VIL0

MUX2 × 12

16-BIT DACs

GAIN/OFFSETCORRECTION

ALARM

TEMPSENSOR

SPI

PMU_S0

DUT0

HVOUT

VPLUS

VDD

VCC

PGND

DGND

VSSRST

BUSY

SDOCS

SCLK

SDI

ALARM

THERM

CMPL0

CMPL0

CMPH0

CMPH0

VTTC0

RCV0

RCV0

DAT0

DAT0

PPMU_S0

PPMU_MEAS0

PPMU_CMPL0

PPMU_CMPH0

0953

0-00

1

IOL0

Figure 1.

ADATE318 Data Sheet


SPECIFICATIONS VDD = +10.0 V, VCC = +2.5 V, VSS = −6.0 V, VPLUS = +16.75 V, VTTCx = +1.2 V, VREF = 5.000 V, VREFGND = 0.000 V. All test conditions are as defined in Table 32. All specified values are at TJ = 50°C, where TJ corresponds to the internal temperature sensor reading (THERM pin), unless otherwise noted. Temperature coefficients are measured around TJ = 50° ± 20°C, unless otherwise noted. Typical values are based on statistical mean of design, simulation analyses, and/or limited bench evaluation data. Typical values are neither tested nor guaranteed. See Table 16 for an explanation of test levels.

Table 1. Detailed Electrical Specifications

Parameter Min Typ Max Unit Test Level Conditions

TOTAL FUNCTION

Output Leakage Current, DCL Disable

PPMU Range E −10.0 ±4.0 +10.0 nA P −2.0 V < VDUTx < +6.5 V, PPMU and DCL disabled, PPMU Range E, VCL = −2.5 V, VCH = +7.5 V

PPMU Range A, Range B, Range C, and Range D

±4.0 nA CT −2.0 V < VDUTx < +6.5 V, PPMU and DCL disabled, PPMU Range A, Range B, Range C, Range D, VCL = −2.5 V, VCH = +7.5 V

Output Leakage Current, Driver High-Z Mode

−2 +2 μA P −2.0 V < VDUTx < +7.0 V, PPMU disabled and DCL enabled, RCVx active, VCL = −2.5 V, VCH = +7.5 V

DUTx Pin Capacitance 1.2 pF S Drive VIT = 0.0 V

DUTx Pin Voltage Range −2.0 +7.0 V D

POWER SUPPLIES

Total Supply Range, VPLUS to VSS

22.75 23.55 V D

VPLUS Supply, VPLUS 15.90 16.75 17.60 V D Defines dc PSR conditions

Positive Supply, VDD 9.5 10.0 10.5 V D Defines dc PSR conditions

Negative Supply, VSS −6.3 −6.0 −5.7 V D Defines dc PSR conditions

Logic Supply, VCC 2.3 2.5 3.5 V D Defines dc PSR conditions

Comparator Output Termination, VTTCx 0.5 1.2 3.3 V D

VPLUS Supply Current, VPLUS 1.1 2.5 mA P VHH pin disabled

4.75 13.28 16.25 mA P VHH pin enabled, RCVx active, no load, VHH programmed level = 13.0 V

Logic Supply Current, VCC −125 1 +125 μA P Quiescent (SPI is static); VCC = 2.5 V

7.5 mA S Current drawn during clocked portion of device reset sequence

Termination Supply Current, VTTCx 30 45 50 mA P

Positive Supply Current, VDD 90 99 115 mA P Load power-down (IOH = IOL = 0 mA)

Negative Supply Current, VSS 155 172 185 mA P Load power-down (IOH = IOL = 0 mA)

Total Power Dissipation 1.9 2.1 2.3 W P Load power-down (IOH = IOL = 0 mA)

Positive Supply Current, VDD 145 174 210 mA P Load active off (IOH = IOL = 25 mA)

Negative Supply Current, VSS 210 246 280 mA P Load active off (IOH = IOL = 25 mA)

Total Power Dissipation 3.0 3.3 3.6 W P Load active off (IOH = IOL = 25 mA)

Positive Supply Current, VDD 167 mA CT Load active off (IOH = IOL = 25 mA), calibrated

Negative Supply Current, VSS 238 mA CT Load active off (IOH = IOL = 25 mA), calibrated

Total Power Dissipation 3.2 W CT Load active off (IOH = IOL = 25 mA), calibrated

Positive Supply Current, VDD 109 mA CT Load power-down, PPMU standby

Negative Supply Current, VSS 183 mA CT Load power-down, PPMU standby

Total Power Dissipation 2.3 W CT Load power-down, PPMU standby

Data Sheet ADATE318



TEMPERATURE MONITOR

Temperature Sensor Gain 10 mV/K D

Temperature Sensor Accuracy over Temperature Range

±6 K CT

VREF INPUT REFERENCE

DAC Reference Input Voltage Range (VREF Pin)

4.950 5.000 5.050 V D Provided externally: VREF pin = +5.000 V VREFGND pin = 0.000 V (not referenced to VDUTGND)

Input Bias Current 100 μA P Tested with 5.000 V applied

DUTGND INPUT

Input Voltage Range, Referenced to AGND

−0.1 +0.1 V D

Input Bias Current −100 +100 μA P Tested at −100 mV and +100 mV

Table 2. Driver (VIH − VIL ≥ 100 mV to Meet DC and AC Performance Specifications)


DC SPECIFICATIONS

High-Speed Differential Input Characteristics

High Speed Input Termination Resistance: DATx, RCVx

92 100 108 Ω P Impedance between each pair of DATx and RCVx pins; push 4 mA into positive pin, force 0.8 V on negative pin, measure voltage between pins; calculate resistance (∆V/∆I)

Input Voltage Differential: DATx, RCVx 0.2 0.4 1.0 V D 0.2 V < VDM < 1.0 V

Input Voltage Range: DATx, RCVx 0.0 3.3 V D 0.0 V < (VCM ± VDM/2) < 3.3 V

Output Characteristics

Output High Range, VIH −1.4 +6.5 V D

Output Low Range, VIL −1.5 +6.4 V D

Output Term Range, VIT −1.5 +6.5 V D

Functional Amplitude (VIH – VIL)

0.0 8.0 V D

DC Output Current Limit Source 75 130 mA P Drive high, VIH = +6.5 V, short DUTx pin to −1.5 V, measure current

DC Output Current Limit Sink −130 −75 mA P Drive low, VIL = −1.5 V, short DUTx pin to +6.5 V, measure current

Output Resistance, ±40 mA 46 48.6 51 Ω P ∆VDUT/∆IDUT; source: VIH = 3.0 V, IDUT = +1 mA, +40 mA; sink: VIL = 0.0 V, IDUT = −1 mA, −40 mA

DC ACCURACY VIH tests with VIL = −2.5 V, VIT = −2.5 V VIL tests with VIH = +7.5 V, VIT = +7.5 V VIT tests with VIL = −2.5 V, VIH = +7.5 V, unless otherwise specified

VIH, VIL, VIT Offset Error −500 +500 mV P Measured at DAC Code 0x4000 (0 V), uncalibrated

VIH, VIL, VIT Offset Tempco ±625 μV/°C CT

VIH, VIL, VIT Gain 1.0 1.1 V/V P Gain derived from measurements at DAC Code 0x4000 (0 V) and DAC Code 0xC000 (5 V); based on ideal DAC transfer functions (see Table 21)

VIH, VIL, VIT Gain Tempco ±40 ppm/°C CT

VIH, VIL, VIT DNL ±1 mV CT After two point gain/offset calibration; calibration points at 0x4000 (0 V) output; 0xC000 (+5 V) output; measured over full specified output range

VIH, VIL, VIT INL −7 +7 mV P After two point gain/offset calibration; applies to nominal VDD = +10.0 V supply case only

ADATE318 Data Sheet



VIH, VIL, VIT Resolution 153 µV D

DUTGND Voltage Accuracy −7 ±2 +7 mV P Over ±0.1 V range; measured at end points of VIH, VIL, and VIT functional range

DC Levels Interaction DC interaction on VIL, VIH, and VIT output level while other driver DAC levels are varied

VIH vs. VIL ±0.2 mV CT Monitor interaction on VIH = +6.5 V; sweep VIL = −1.5 V to +6.4 V, VIT = +1.0 V

VIH vs. VIT ±1 mV CT Monitor interaction on VIH = +6.5 V; sweep VIT = −1.5 V to +6.5 V, VIL = 0.0 V

VIL vs. VIH ±0.2 mV CT Monitor interaction on VIL = −1.5 V; sweep VIH = −1.4 V to +6.5 V, VIT = +1.0 V

VIL vs. VIT ±1 mV CT Monitor interaction on VIL = −1.5 V; sweep VIT = −1.5 V to +6.5 V, VIH = +2.0 V

VIT vs. VIH ±1 mV CT Monitor interaction on VIT = +1.0 V; sweep VIH = −1.4 V to +6.5 V, VIL = −1.5 V

VIT vs. VIL ±1 mV CT Monitor interaction on VIT = +1.0 V; sweep VIL = −1.5 V to +6.4 V, VIH = +6.5 V

Overall Voltage Accuracy ±8 mV CT VIH − VIL ≥ 100 mV; sum of INL, dc interaction, DUTGND, and tempco errors over ±5ºC, after calibration

VIH, VIL, VIT DC PSRR ±10 mV/V CT Measured at calibration points

AC SPECIFICATIONS All ac specifications performed after calibration

Rise/Fall Times Toggle DATx

0.2 V Programmed Swing, TRISE 215 ps CB 20% to 80%, VIH = 0.2 V, VIL = 0.0 V, terminated

0.2 V Programmed Swing, TFALL 277 ps CB 20% to 80%, VIH = 0.2 V, VIL = 0.0 V, terminated



1.0 V Programmed Swing, TRISE 150 222 320 ps P 20% to 80%, VIH = 1.0 V, VIL = 0.0 V, terminated

1.0 V Programmed Swing, TFALL 150 283 320 ps P 20% to 80%, VIH = 1.0 V, VIL = 0.0 V, terminated





5.0 V Programmed Swing, TRISE 1117 ps CB 10% to 90%, VIH = 5.0 V, VIL = 0.0 V, unterminated

5.0 V Programmed Swing, TFALL 798 ps CB 10% to 90%, VIH = 5.0 V, VIL = 0.0 V, unterminated

Rise to Fall Matching −25 ps CB Rise to fall within one channel, VIH = 2.0 V, VIL = 0.0 V, terminated

−61 ps CB Rise to fall within one channel; VIH = 1.0 V, VIL = 0.0 V, terminated

Minimum Pulse Width Toggle DATx

0.5 V Programmed Swing 725 ps CB VIH = 0.5 V, VIL = 0.0 V, terminated, timing error less than +69/−33 ps

725 ps CB VIH = 0.5 V, VIL = 0.0 V, terminated, less than 10% amplitude loss

Maximum Toggle Rate 2040 Mbps CB VIH = 0.5 V, VIL = 0.0 V, terminated, less than 10% loss at 50% duty



Data Sheet ADATE318









Maximum Toggle Rate 1100 Mbps CB VIH = 3.0 V, VIL = 0.0 V, terminated, less than 10% amplitude loss at 50% duty cycle

Dynamic Performance, Drive (VIH to VIL)

Toggle DATx

Propagation Delay Time 1.26 ns CB VIH = 2.0 V, VIL = 0.0 V, terminated

Propagation Delay Tempco 1.4 ps/ºC CB VIH = 2.0 V, VIL = 0.0 V, terminated

Delay Matching, Edge to Edge 43 ps CB VIH = 2.0 V, VIL = 0.0 V, terminated, rising vs. falling

Delay Matching, Channel to Channel 32 ps CB VIH = 2.0 V, VIL = 0.0 V, terminated, rising vs. rising, falling vs. falling

Delay Change vs. Duty Cycle −28 ps CB VIH = 2.0 V, VIL = 0.0 V, terminated, 5% to 95% duty cycle

Overshoot and Undershoot −116 mV CB VIH = 2.0 V, VIL = 0.0 V, terminated, driver CLC set to 0

Settling Time (VIH to VIL) Toggle DATx

To Within 3% of Final Value 1.7 ns CB VIH = 2.0 V, VIL= 0.0 V, terminated

To Within 1% of Final Value 45 ns CB VIH = 2.0 V, VIL= 0.0 V, terminated

Dynamic Performance, VTerm (VIH or VIL to/from VIT)

Toggle RCVx

Propagation Delay Time 1.39 ns CB VIH = 2.0 V, VIT = 1.0 V, VIL = 0.0 V, terminated

Propagation Delay Tempco 2.3 ps/ºC CB VIH = 2.0 V, VIT = 1.0 V, VIL = 0.0 V, terminated

Transition Time, Active to VIT 310 ps CB 20% to 80%, VIH = 2.0 V, VIT = 1.0 V, VIL = 0.0 V, terminated

Transition Time, VIT to Active 329 ps CB 20% to 80%, VIH = 2.0 V, VIT = 1.0 V, VIL = 0.0 V, terminated

Dynamic Performance, Inhibit (VIH or VIL to/from Inhibit)

Toggle RCVx

Transition Time, Inhibit to Active 357 ps CB 20% to 80%, VIH = +1.0 V, VIL = −1.0 V, terminated

Transition Time, Active to Inhibit 1.34 ns CB 20% to 80%, VIH = +1.0 V, VIL = −1.0 V, terminated

Prop Delay, Inhibit to VIH 2.6 ns CB VIH = +1.0 V, VIL = −1.0 V, terminated; measured from RCVx input crossing to DUTx pin output 50%

Prop Delay, Inhibit to VIL 2.8 ns CB VIH = +1.0 V, VIL = −1.0 V, terminated

Prop Delay Matching, Inhibit to VIL vs. Inhibit to VIH

52 ps CB VIH = +1.0 V, VIL = −1.0 V, terminated

Prop Delay, VIH to Inhibit 2.29 ns CB VIH = +1.0 V, VIL = −1.0 V, terminated, measured from RCVx input crossing to DUTx pin output 50%

Prop Delay, VIL to Inhibit 2.02 ns CB VIH = +1.0 V, VIL = −1.0 V, terminated

I/O Spike 24 mV pk-pk

CB VIH = 0.0 V, VIL = 0.0 V, terminated

Driver Pre-Emphasis (CLC)

Pre-Emphasis Amplitude Rising 35 % CB VIH = 2.0 V, VIL = 0.0 V, terminated, DRV_CLC_x[15:13] = 7

14 % CB VIH = 2.0 V, VIL = 0.0 V, terminated, DRV_CLC_x[15:13] = 0

Pre-Emphasis Amplitude Falling 24 % CB VIH = 2.0 V, VIL = 0.0 V, terminated, DRV_CLC_x[15:13] = 7

16 % CB VIH = 2.0 V, VIL = 0.0 V, terminated, DRV_CLC_x[15:13] = 0

ADATE318 Data Sheet



Pre-Emphasis Resolution 2 % D

Pre-Emphasis Time Constant 0.8 ns CB VIH = 2.0 V, VIL = 0.0 V, terminated

Table 3. Reflection Clamp (Clamp Accuracy Specifications Apply Only When VCH − VCL > 0.8 V)


VCH/VCL PROGRAMMABLE RANGE −2.5 +7.5 V D DC specifications apply over full functional range unless noted.

VCH

VCH Functional Range −1.2 +7.0 V D

VCH Offset Error −300 +300 mV P Driver high-Z, sinking 1 mA, measured at DAC Code 0x4000, uncalibrated.

VCH Offset Tempco ±0.5 mV/ºC CT

VCH Gain 1.0 1.1 V/V P Driver high-Z, sinking 1 mA, gain derived from measurements at DAC Code 0x4000 (0 V) and DAC Code 0xC000 (5 V), based on ideal DAC transfer function (see Table 21).

VCH Gain Tempco ±30 ppm/°C CT

VCH Resolution 153 µV D

VCH DNL ±1 mV CT Driver high-Z, sinking 1 mA, after two point gain/offset calibration; calibration points at DAC Code 0x4000 (0 V) and DAC Code 0xC000 (5 V), measured over functional clamp range.

VCH INL −20 +20 mV P Driver high-Z, sinking 1 mA, after two point gain/offset calibration; calibration points at 0x4000 (0 V) and 0xC000 (5 V), measured over functional clamp range.

VCL

VCL Functional Range −2 +6.2 V D

VCL Offset Error −300 +300 mV P Driver high-Z, sourcing 1 mA, measured at DAC Code 0x4000, uncalibrated.

VCL Offset Tempco ±0.5 mV/°C CT

VCL Gain 1.0 1.1 V/V P Drive high-Z, sourcing 1 mA, gain derived from measurements at DAC Code 0x4000 (0 V) and DAC Code 0xC000 (5 V), based on ideal DAC transfer function (see Table 21).

VCL Gain Tempco ±30 ppm/°C CT

VCL Resolution 153 µV D

VCL DNL ±1 mV CT Driver high-Z, sourcing 1 mA, after two point gain/offset calibration; calibration points at 0x4000 (0 V) and 0xC000 (+5 V), measured over functional clamp range.

VCL INL −20 +20 mV P Driver high-Z, sourcing 1 mA, after two point gain/offset calibration; calibration points at 0x4000 (0 V) and 0xC000 (+5 V), measured over functional clamp range.

DC Clamp Current Limit, VCH −120 −75 mA P Driver high-Z, VCH = 0 V, VCL = −2.0 V, VDUTx = +5.0 V.

DC Clamp Current Limit, VCL +75 +120 mA P Driver high-Z, VCH = +6.0 V, VCL = +5.0 V, VDUTx = 0.0 V.

DUTGND Voltage Accuracy −7 ±2 +7 mV P Over ±0.1 V range, measured at end points of VCH and VCL functional range.

Data Sheet ADATE318


Table 4. Normal Window Comparator (NWC) (Unless Otherwise Specified: VOH Tests at VOL = −1.5 V, VOL Tests at VOH = +6.5 V, Specifications Apply to Both Comparators)


DC SPECIFICATIONS

Input Voltage Range −1.5 +6.5 V D

Differential Voltage Range ±0.1 ±8.0 V D

Comparator Input Offset Voltage −250 +250 mV P Measured at DAC Code 0x4000 (0V), uncalibrated

Input Offset Voltage Tempco ±100 µV/ºC CT

Gain 1.0 1.1 V/V P Gain derived from measurements at DAC Code 0x4000 (0 V) and DAC Code 0xC000 (5 V); based on ideal DAC transfer function (see Table 21)

Gain Tempco ±25 ppm/°C CT

Threshold Resolution 153 µV D

Threshold DNL ±1 mV CT Measured over −1.5 V to +6.5 V functional range after two point gain/offset calibration; calibration points at 0x4000 (0 V) and 0xC000 (5 V)

Threshold INL −7 +7 mV P Measured over −1.5 V to +6.5 V functional range after two point gain/offset calibration; calibration points at 0x4000 (0 V) and 0xC000 (5 V)

DUTGND Voltage Accuracy −7 ±2 +7 mV P Over ±0.1 V range; measured at end points of VOH and VOL functional range

Uncertainty Band 5 mV CB VDUTx = 0 V, sweep comparator threshold to determine the uncertainty band

Maximum Programmable Hysteresis 96 mV CB

Hysteresis Resolution 5 mV D Calculated over hystersis control Code 10 to Code 31

DC PSRR ±5 mV/V CT Measured at calibration points

Digital Output Characteristics

Internal Pull-Up Resistance to Comparator, VTTC

46 50 54 Ω P Pull 1 mA and 10 mA from Logic 1 leg and measure ∆V to calculate resistance; measured ∆V/9 mA; done for both comparator logic states

Comparator Termination Voltage, VTTC

0.5 1.2 3.3 V D

Common Mode Voltage VTTC − 0.3 V CT Measured with 100 Ω differential termination

VTTC − 0.5

VTTC V P Measured with no external termination

Differential Voltage 250 mV CT Measured with 100 Ω differential termination

450 500 550 mV P Measured with no external termination

Rise/Fall Times, 20% to 80% 166 ps CB Measured with 50 Ω to external termination voltage (VTTC)

AC SPECIFICATIONS All ac specifications performed after dc level calibration, input transition time of ~200 ps, 20% to 80%, measured with 50 Ω to external termination voltage (VTTC); peaking set to CLC = 2, unless otherwise specified

Propagation Delay, Input to Output 0.93 ns CB VDUTx: 0 V to 1.0 V swing, driver term mode, VIT = 0.0 V, comparator threshold = 0.5 V

Propagation Delay Tempco 1.6 ps/ºC CB VDUTx: 0 V to 1.0 V swing, driver term mode, VIT = 0.0 V, comparator threshold = 0.5 V

Propagation Delay Matching High Transition to Low Transition

7 ps CB VDUTx: 0 V to 1.0 V swing, driver term mode, VIT = 0.0 V, comparator threshold = 0.5 V

Propagation Delay Matching High to Low Comparator


ADATE318 Data Sheet



Propagation Delay Dispersion

Slew Rate 400 ps vs. 1 ns (20% to 80%)


Overdrive 250 mV vs. 1.0 V

40 ps CB For 250 mV, VDUTx: 0 V to 0.5 V swing; for 1.0 V, VDUTx: 0 V to 1.25 V swing, driver term mode, VIT = 0.0 V, comparator threshold = 0.25 V

1 V Pulse Width 0.7 ns, 1 ns, 5 ns, 10 ns

+2/− 17 ps CB VDUTx: 0 V to 1.0 V swing at~32.0 MHz; driver term mode, VIT = 0.0 V, comparator threshold = 0.5 V

0.5 V Pulse Width 0.6 ns, 1 ns, 5 ns, 10 ns

+3/− 24 ps CB VDUTx: 0 V to 0.5 V swing at~32.0 MHz, driver term mode, VIT = 0.0 V; comparator threshold = 0.25 V

Duty Cycle 5% to 95%

21 ps CB VDUTx: 0 V to 1.0 V swing at~32.0 MHz; driver term mode, VIT =0.0 V, comparator threshold = 0.5 V

Minimum Detectable Pulse Width 0.5 ns CB VDUTx: 0 V to 1.0 V swing at 32.0 MHz, driver term mode, VIT = 0.0 V; greater than 50% output differential amplitude

Input Equivalent Bandwidth, Terminated

1520 MHz CB VDUTx: 0 V to 1.0 V swing; driver term mode, VIT = 0.0 V, CLC = 2; as measured by shmoo plot; fEQUIV = 0.22/√(tMEAS

2 − tDUT2)

ERT High-Z Mode, 3 V, 20% to 80% 721 ps CB VDUTx: 0 V to 3.0 V swing, driver high-Z as measured by shmoo plot; fEQUIV = 0.22/√(tMEAS

2 – tDUT2)

Comparator Pre-Emphasis (CLC)

CLC Amplitude Range 16 % CB VDUTx: 0 V to 1.0 V swing, driver term mode, VIT = 0.0 V, comparator pre-emphasis set to maximum

CLC Resolution 2.3 % per bit

CB 3-bit amplitude control

Pre-Emphasis Time Constant 4.3 ns CB VDUTx: 0 V to 1.0 V swing, driver term mode, VIT = 0.0 V, comparator pre-emphasis set to maximum

Table 5. Differential Mode Comparator (DMC) (Unless Otherwise Specified: VOH Tests at VOL = −1.1 V, VOL Tests at VOH = +1.1 V)


DC SPECIFICATIONS

Input Voltage Range −1.5 +6.5 V D

Functional Differential Range ±0.05 ±1.1 V D

Maximum Differential Input ±8 V D

Input Offset Voltage −250 +250 mV P Offset extrapolated from measurements at DAC Code 0x2666 (−1 V) and DAC Code 0x599A (+1 V), with VCM = 0 V

Offset Voltage Tempco ±150 µV/ºC CT

Gain 1.0 1.1 V/V P Gain derived from measurements at DAC Code 0x2666 (−1 V) and DAC Code 0x599A (+1 V), based on ideal DAC transfer function (see Table 21)


VOH, VOL Resolution 153 µV D

VOH, VOL DNL ±1 mV CT After two point gain/offset calibration, VCM = 0.0 V, calibration points at 0x2666 (−1 V) and 0x599A (+1 V)

VOH, VOL INL −7 +7 mV P After two point gain/offset calibration, measured over VOH/VOL range of −1.1 V to +1.1 V, VCM = 0.0 V; calibration points at 0x2666 (−1 V) and 0x599A (+1 V)

Uncertainty Band 7 mV CB VDUTx = 0 V; sweep comparator threshold to determine the uncertainty band

Data Sheet ADATE318



Maximum Programmable Hysteresis

117 mV CB

Hysteresis Resolution 5.6 mV D Calculated over hystersis control Code 10 to Code 31

CMRR −1 +1 mV/V P Offset measured at VCM = −1.5 V and +6.5 V with VDM = 0.0 V, offset error change

DC PSRR ±5 mV/V CT Measured at calibration points

AC SPECIFICATIONS All ac specifications performed after dc level calibration, unless noted; input transition time ~200 ps, 20% to 80%, measured with 50 Ω to external termination voltage (VTTC), peaking set to CLC = 2, unless otherwise specified

Propagation Delay, Input to Output

0.83 ns CB VDUT0 = 0 V, VDUT1: −0.5 V to +0.5 V swing, driver term mode, VIT = 0.0 V, comparator threshold = 0.0 V, repeat for other channel

Propagation Delay Tempco 2.6 ps/ºC CB VDUT0 = 0 V, VDUT1: −0.5 V to +0.5 V swing, driver term mode, VIT = 0.0 V, comparator threshold = 0.0 V, repeat for other channel

Propagation Delay Matching, High Transition to Low Transition

15 ps CB VDUT0 = 0 V, VDUT1: −0.5 V to +0.5 V swing, driver term mode, VIT = 0.0 V, comparator threshold = 0.0 V, repeat for other channel

Propagation Delay Matching, High to Low Comparator

17 ps CB VDUT0 = 0 V, VDUT1: −0.5 V to +0.5 V swing, driver term mode, VIT = 0.0 V, comparator threshold = 0.0 V, repeat for other channel

Propagation Delay Change (Dispersion) With Respect To

Slew Rate: 400 ps and 1 ns (20% to 80%)

31 ps CB VDUT0 = 0.0 V; VDUT1: −0.5 V to +0.5 V swing; driver term mode, VIT = 0.0 V; comparator threshold = 0.0 V, repeat for other channel

Overdrive: 250 mV and 750 mV

32 ps CB VDUT0 = 0.0 V; for 250 mV: VDUT1: 0 V to 0.5 V swing; for 750 mV: VDUT1: 0 V to 1.0 V swing; driver term mode, VIT = 0.0 V; comparator threshold = −0.25 V; repeat for other channel with comparator threshold = +0.25 V

1 V Pulse Width: 0.7 ns, 1 ns, 5 ns, 10 ns

+1/− 21

ps CB VDUT0 = 0.0 V; VDUT1: −0.5 V to +0.5 V swing at 32 MHz; driver term mode, VIT = 0.0 V; comparator threshold = 0.0 V; repeat for other channel

0.5 V Pulse Width: 0.6 ns, 1 ns, 5 ns, 10 ns

+1/− 31

ps CB VDUT0 = 0.0 V; VDUT1: −0.25 V to +0.25 V swing at 32 MHz; driver term mode, VIT = 0.0 V; comparator threshold = 0.0 V; repeat for other channel

Duty Cycle: 5% to 95%

18 ps CB VDUT0 = 0.0 V; VDUT1: −0.5 V to +0.5 V swing at 32 MHz; driver term mode, VIT = 0.0 V; comparator threshold = 0.0 V; repeat for other channel

Minimum Detectable Pulse Width

0.5 ns CB VDUT0 = 0.0 V; VDUT1: −0.5 V to +0.5 V swing at 32 MHz; driver term mode, VIT = 0.0 V; comparator threshold = 0.0 V; greater than 50% output differential amplitude; repeat for other channel

Input Equivalent Bandwidth, Terminated

1038 MHz CB VDUT0 = 0.0 V; VDUT1: −0.5 V to +0.5 V swing; driver term mode, VIT = 0.0 V; comparator threshold = 0.0 V, CLC = 2 as measured by shmoo; repeat for other channel

Comparator Pre-Emphasis (CLC)

CLC Amplitude Range 11 % CB VDUT0 = 0.0 V; VDUT1: −0.8 V to +0.8 V swing, driver term mode, VIT = 0.0 V; comparator threshold = 0.0 V; comparator CLC set to maximum; repeat for other channel

CLC Resolution 1.6 % per bit CB 3-bit amplitude control

Pre-Emphasis Time Constant 4.8 ns CB VDUT0 = 0.0 V; VDUT1: −0.8 V to +0.8 V swing, driver term mode, VIT = 0.0 V; comparator threshold = 0.0 V; comparator CLC set to maximum; repeat for other channel

ADATE318 Data Sheet


Table 6. Active Load


DC SPECIFICATIONS Load active on, RCVx active, unless otherwise noted

Input Characteristics

VCOM Voltage Range −1.5 +6.5 V D | IOL and IOH | ≤ 1 mA

−1.0 +5.5 V D | IOL and IOH | ≤ 25 mA

VCOM Offset −200 +200 mV P Measured at DAC Code 0x4000, uncalibrated

VCOM Offset Tempco ±25 µV/°C CT

VCOM Gain 1.0 1.1 V/V P Gain derived from measurements at DAC Code 0x4000 (0 V) and DAC Code 0xC000 (+5 V), based on ideal DAC transfer function (see Table 21)

VCOM Gain Tempco ±25 ppm/°C CT

VCOM Resolution 153 µV D

VCOM DNL ±1 mV CT IOH = IOL = 12.5 mA; after two point gain/offset calibration; measured over VCOM range of −1.5 V to +6.5 V; calibration points at 0x4000 (0 V) and 0xC000 (+5 V)

VCOM INL −7 +7 mV P IOH = IOL = 12.5 mA; after two point gain/offset calibration; measured at end points of VCOM functional range

DUTGND Voltage Accuracy

−7 ±2 +7 mV P Over ±0.1 V range

Output Characteristics

Maximum Source Current

25 mA D −1.5 V to +5.5 V DUT range

IOL Offset −600 +600 µA P IOH = −2.5 mA, VCOM = 1.5 V, VDUTx = 0.0 V; offset extrapolated from measurements at DAC Code 0x451F (1 mA) and DAC Code 0xA666 (20 mA)

IOL Offset Tempco ±1 µA/°C CT

IOL Gain Error 0 25 % P IOH = −2.5 mA, VCOM = 1.5 V, VDUTx = 0.0 V; gain derived from measurements at DAC Code 0x451F (1 mA) and DAC Code 0xA666 (20 mA); based on ideal DAC transfer function (see Table 21 and Table 22)

IOL Gain Tempco ±25 ppm/°C CT

IOL Resolution 763 nA D

IOL DNL ±4 µA CT IOH = −2.5 mA, VCOM = 1.5 V, VDUTx = 0.0 V; after two point gain/offset calibration; measured over IOL range, 0 mA to 25 mA; calibrated at Code 0x451F (1 mA) and Code 0xA666 (20 mA)

IOL INL −100 ±20 +100 µA P IOH = −2.5 mA, VCOM = 1.5 V, VDUTx = 0.0 V; after two point gain/offset calibration

IOL 90% Commutation Voltage

0.25 0.4 V P IOH = IOL = 25 mA, VCOM = 2.0 V; measure IOL reference at VDUTx = −1.0 V; measure IOL current at VDUTx = 1.6 V; check >90% of reference current

IOL 90% Commutation Voltage

0.1 V CT IOH = IOL = 1 mA, VCOM = 2.0 V; measure IOL reference at VDUTx = −1.0 V; measure IOL current at VDUTx = 1.9 V; check >90% of reference current

Maximum Sink Current 25 mA D −1.0 V to +6.5 V output range

IOH Offset −600 +600 µA P IOL = −2.5 mA, VCOM = 1.5 V, VDUTx = 3.0 V; offset extrapolated from measurements at DAC Code 0x451F (1 mA) and DAC Code 0xA666 (20 mA)

IOH Offset Tempco ±1 µA/°C CT

IOH Gain Error 0 25 % P IOL = −2.5 mA, VCOM = 1.5 V, VDUTx = 3.0 V; gain derived from measurements at DAC Code 0x451F (1 mA) and DAC Code 0xA666 (20 mA); based on ideal DAC transfer function (see Table 21 and Table 22)

Data Sheet ADATE318



IOH Gain Tempco ±25 ppm/°C CT

IOH Resolution 763 nA D

IOH DNL ±4 µA CT IOL = −2.5 mA, VCOM = 1.5 V, VDUTx = 3.0 V; after two point gain/offset calibration; measured over IOH range, 0 mA to 25 mA; calibrated at Code 0x451F (1 mA) and Code 0xA666 (20 mA)

IOH INL −100 ±25 +100 µA P IOL = −2.5 mA, VCOM = 1.5 V, VDUTx = 3.0 V; after two point gain/offset calibration

IOH 90% Commutation Voltage

0.25 0.4 V P IOH = IOL = 25 mA, VCOM = 2.0 V; measure IOH reference at VDUTx = 5.0 V; measure IOH current at VDUTx = 2.4 V; ensure >90% of reference current

0.1 V CT IOH = IOL = 1 mA, VCOM = 2.0 V; measure IOH reference at VDUTx = 5.0 V; measure IOH current at VDUTx = 2.1 V; ensure >90% of reference current

AC SPECIFICATIONS All ac specifications performed after dc level calibration unless noted; load active on

Dynamic Performance

Propagation Delay, Load Active On to Load Active Off; 50%, 90%

3.1 ns CB Toggle RCVx; DUTx terminated 50 Ω to GND; IOL = IOH = 20 mA, VIH = VIL = 0 V; VCOM = +1.5 V for IOL and −1.5 V for IOH; measured from 50% point of RCVx − RCVx to 90% point of final output; repeat for drive low and drive high

Propagation Delay, Load Active Off to Load Active On; 50%, 90%

4.1 ns CB Toggle RCVx; DUTx terminated 50 Ω to GND; IOL = IOH = 20 mA, VIH = VIL = 0 V; VCOM = +1.5 V for IOL and −1.5 V for IOH; measured from 50% point of RCVx − RCVx to 90% point of final output; repeat for drive low and drive high

Propagation Delay Matching

1.0 ns CB Toggle RCVx; DUTx terminated 50 Ω to GND; IOL = IOH = 20 mA, VIH = VIL = 0 V; VCOM = +1.5 V for IOL and −1.5 V for IOH; active on vs. active off; repeat for drive low and drive high

Load Spike 106 mV pk-pk

CB Toggle RCVx; DUTx terminated 50 Ω to GND; IOL = IOH = 0 mA, VIH = VIL = 0 V; VCOM = +1.5 V for IOL and −1.5 V for IOH; repeat for drive low and drive high

Settling Time to 90% 1.6 ns CB Toggle RCVx; DUTx terminated 50 Ω to GND; IOL = IOH = 20 mA, VIH = VIL = 0 V; VCOM = +1.5 V for IOL and −1.5 V for IOH; measured at 90% of final value

Table 7. PPMU (PPMU Enabled in FV, DCL Disabled)


FORCE VOLTAGE

Current Range A −40 +40 mA D

Current Range B −1 +1 mA D

Current Range C −100 +100 µA D

Current Range D −10 +10 µA D

Current Range E −2 +2 µA D

Voltage Range at Output

Range A −2.0 +5.75 V D Output range for full-scale source and sink.

−2.0 +6 V D Output range for ±25 mA.

Range B, Range C, Range D, and Range E

−2.0 +6.5 V D Output range for full-scale source and sink.

Offset

Range C −100 +100 mV P Measured at DAC Code 0x4000 (0 V).

All Ranges ±10 mV CT Measured at DAC Code 0x4000 (0 V).

Offset Tempco, All Ranges ±25 µV/°C CT

ADATE318 Data Sheet



Gain

Range C 1.0 1.1 V/V P Gain derived from measurements at DAC Code 0x4000 (0 V) and DAC Code 0xC000 (5 V); based on ideal DAC transfer function (see Table 21 and Table 23).

All Ranges 1.05 V/V CT Gain derived from measurements at DAC Code 0x4000 (0 V) and DAC Code 0xC000 (5 V); based on ideal DAC transfer function (see Table 21 and Table 23).

Gain Tempco, All Ranges ±25 ppm/°C CT Gain derived from measurements at DAC Code 0x4000 (0V) and DAC Code 0xC000 (5 V); calibration point 0x4000 (0 V) and 0xC000 (+5 V) output.

INL

Range A ±1 mV CT After two point gain/offset calibration, output range of 2.0 V to 5.75 V, PPMU Current Range A only.

Range C −1.7 1.7 mV P After two point gain/offset calibration; output range of 2.0 V to 6.5 V.

Range B, Range D, and Range E ±1 mV CT After two point gain/offset calibration, output range of 2.0 V to 6.5 V.

Compliance vs. Current Load

Range A ±40 mV CT Force 2.0 V; measure voltage while sinking zero and full-scale current; measure V; force 5.75 V; measure voltage while sourcing zero and full-scale current; measure V.

±25 mV CT Force 2.0 V; measure voltage while sinking zero and 25 mA current; measure V; force 6 V; measure voltage while sourcing zero and 25 mA current; measure V.


±1 mV CT Force 2.0 V; measure voltage while sinking zero and full-scale current; measure V; force 6.5 V; measure voltage while sourcing zero and full-scale current; measure V.

Current Limit, Source and Sink All Ranges

120 140 180 %FS P Sink: force 2.0 V, short DUTx to 6.5 V; source: force 6.5 V, short DUTx to 2.0 V; repeat for each current range; example: Range A

FS = 40 mA, 120% FS = 48 mA 180% FS = 72 mA

DUTGND Voltage Accuracy −7 ±2 7 mV P Over ±0.1 V range; measured at endpoints of PPMU_VINFV functional range (see Figure 136).

MEASURE CURRENT PPMU enabled in FIMI, DCL disabled.

DUTx Pin Voltage Range at Full Current

Range A −2.0 +5.75 V D


−2.0 +6.5 V D

Zero-Current Offset, Range B −2 +2 %FSR P Interpolated from measurements sourcing and sinking 80% FSR current each range; FSR = 80 mA for Range A, 2 mA for Range B, 200 μA for Range C, 20 μA for Range D, 4 μA for Range E (see Table 21 and Table 23).

All Ranges ±0.5 %FSR CT See Table 21 and Table 23.

Zero-Current Offset Tempco, Range A ±0.001 %FSR/°C CT See Table 21 and Table 23.

Data Sheet ADATE318



Range B, Range C, and Range D ±0.001 %FSR/°C CT

Range E ±0.002 %FSR/°C CT

Gain Error

Range B −30 +5 % P Based on measurements sourcing and sinking, 80% FSR current.

All Ranges −10 % CT Based on measurements sourcing and sinking, 80% FSR current.

Gain Tempco

Range A ±50 ppm/°C CT


±25 ppm/°C CT

INL

Range A ±0.0125 %FSR CT Range A, after two point gain/offset calibration at ±80% FSR current; measured over FSR output of −40 mA to +40 mA.

Range B −0.03 +0.03 %FSR P After two point gain/offset calibration at ±80% FSR current; measured over FSR output of −1 mA to +1 mA.

Range C, Range D, and Range E ±0.01 %FSR CT After two point gain/offset calibration at ±80% FSR current; measured over each FSR output for Range C, Range D, and Range E.

DUTx Pin Voltage Rejection −1.2 +1.2 µA P Range B, FVMI, force −1 V and 5 V into load of 0.5 mA, measure ∆I reported at PPMU_MEASx pin.

DUTGND Voltage Accuracy −7 ±2 +7 mV P Over ±0.1 V range (see Figure 136).

FORCE CURRENT PPMU enabled in FIMI, DCL disabled.

DUTx Pin Voltage Range in Range A −2.0 +5.75 V D At full-scale source and sink current.

−2.0 +6 V D At 25 mA source and sink current.

DUTx Pin Voltage Range at Full Current, Range B, Range C, Range D, and Range E

−2.0 +6.5 V D

Zero-Current Offset, All Ranges −14.5 +14.5 %FSR P Extrapolated from measurements at Code 0x4CCC and Code 0xB333 for each range (see Table 21 and Table 23).

Zero-Current Offset Tempco ±0.002 %FSR/°C CT

Gain Error, All Ranges −5 +25 % P Derived from measurements at Code 0x4CCC and Code 0xB333 for each range (see Table 21 and Table 23).

Gain Tempco

Range A ±50 ppm/°C CT Significant PPMU self-heating effects in Range A can influence gain drift/tempco measurements.


±25 ppm/°C CT

INL

Range A −0.12 ±0.02 +0.12 %FSR P After two point gain/offset calibration; measured over FSR output of −40 mA to +40 mA.

Range B, Range C, and Range D −0.03 +0.03 %FSR P After two point gain/offset calibration; measured over FSR output; repeat for Range B, Range C, and Range D.

ADATE318 Data Sheet



Range E −0.045 +0.045 %FSR P After two point gain/offset calibration; measured over FSR output.

Force Current Compliance vs. Voltage Load

Range A −0.3 +0.3 %FSR P Force positive full-scale current driving −2.0 V and +5.75 V; measure ∆I at DUTx pin; force negative full-scale current driving −2.0 V and +5.75 V; measure ∆I at DUTx pin.

−0.3 +0.3 %FSR P Force +25 mA driving −2.0 V and +6.0 V; measure ∆I at DUTx pin; force −25 mA driving −2.0 V and +6.0 V; measure ∆I at DUTx pin.

−0.06 +0.06 %FSR P Force positive full-scale current driving 0.0 V and +4.0 V; measure ∆I at DUTx pin; force negative full-scale current driving 0.0 V and +4.0 V; measure ∆I at DUTx pin.

Range B and Range C −0.3 +0.3 %FSR P Force positive full-scale current driving −2.0 V and +6.5 V; measure ∆I at DUTx pin; force negative full-scale current driving −2.0 V and +6.5 V; measure ∆I at DUTx pin.

−0.06 +0.06 %FSR P Force positive full-scale current driving 0.0 V and +4.0 V; measure ∆I at DUTx pin; force negative full-scale current driving 0.0 V and +4.0 V; measure ∆I at DUTx pin.

Range D −0.3 +0.3 %FSR P Force positive full-scale current driving −2.0 V and +6.5 V; measure ∆I at DUTx pin; force negative full-scale current driving −2.0 V and +6.5 V; measure ∆I at DUTx pin; allows for 10 nA of DUTx pin leakage.

Range E −0.85 +0.85 %FSR P Force positive full-scale current driving −2.0 V and +6.5 V; measure ∆I at DUTx pin; force negative full-scale current driving −2.0 V and +6.5 V; measure ∆I at DUTx pin; allows for 10 nA of DUTx pin leakage.

MEASURE VOLTAGE PPMU enabled, FVMV, DCL disabled.

Voltage Range −2.0 +6.5 V D

Offset −25 +25 mV P Range B, VDUTx = 0 V; offset = (PPMU_MEAS − VDUTx).

Offset Tempco ±10 µV/°C CT

Gain 0.98 1.02 V/V P Range B, gain derived from measurements at VDUTx = 0.0 V and +5.0 V.


INL −1.7 +1.7 mV P Range B, measured over −2.0 V to +6.5 V.

Measure Pin DC Characteristics

Output Range −2.0 +6.5 V D

DC Output Current 4 mA D

Output Impedance 200 Ω P PPMU enabled in FVMV, DCL disabled; Source resistance:

PPMU force +6.5 V with 0 mA, +4 mA load Sink resistance:

PPMU force −2.0 V with 0 mA, −4 mA load Resistance = ∆V/∆I at PPMU_MEAS pin.

Output Leakage Current When Tristated

−1 +1 µA P Tested at −2.0 V and +6.5 V.

Data Sheet ADATE318



Output Short-Circuit Current −25 +25 mA P PPMU enabled in FVMV, DCL disabled; Source:

PPMU force +6.5 V, PPMU_MEAS to −2.0 V Sink: PPMU force −2.0 V, PPMU_MEAS to +6.5 V

PPMU_MEASx Pin, Output Capacitance

2 pF S

PPMU_MEASx Pin, Load Capacitance 100 pF S Maximum load capacitance.

VOLTAGE CLAMPS PPMU enabled in FIMI, DCL disabled, PPMU clamps enabled; clamp accuracy specifica-tions apply only when VCH > VCL.

Low Clamp Range (VCL) −2.0 +4.0 V D

High Clamp Range (VCH) 0.0 +6.5 V D

Positive Clamp Voltage Droop −300 ±1 +300 mV P ∆V seen at DUTx pin, Range A, VCH = +5.0 V, VCL = −1 V; PPMU force 5 mA and 40 mA into open.

Negative Clamp Voltage Droop −300 ±1 +300 mV P ∆V seen at DUTx pin, Range A, VCH = +5.0 V, VCL = −1 V, PPMU force −5 mA and 40 mA into open.

Offset, PPMU Clamp VCH/VCL −300 +300 mV P Range B, PPMU force ±0.5 mA into open; VCH measured at DAC Code 0x4000 (0 V) with VCL at Code 0x0000 (−2.5 V); VCL measured at DAC Code 0x4000 (0 V) with VCH at 0xFFFF (+7.5 V).

Offset Tempco, PPMU Clamp VCH/VCL ±0.5 mV/°C CT

Gain, PPMU Clamp VCH/VCL 1.0 1.2 V/V P Range B, PPMU force ±0.5 mA into open; VCH gain derived from measurements at DAC Code 0x4000 (0 V) and DAC Code 0xC000 (+5.0 V) with VCL at Code 0x0000 (−2.5 V); VCL gain derived from measurements at DAC Code 0x4000 (0 V) and DAC Code 0xA666 (+4.0 V) with VCH at 0xFFFF (+7.5 V).

Gain Tempco, PPMU Clamp VCH/VCL ±25 ppm/°C CT

INL, PPMU Clamp VCH/VCL −20 +20 mV P Range B, PPMU force ±0.5 mA into open, after two point gain/offset calibration; measured over PPMU clamp functional range.

DUTGND Voltage Accuracy −7 ±2 +7 mV P Over ±0.1 V range; measured at end points of clamp functional range.

SETTLING/SWITCHING TIMES

Force Voltage Settling Time to 0.1% of Final Value

Range A, 200 pF and 2000 pF Load

10 µs S PPMU enabled in FV, Range A, DCL disabled; program VIN steps from 0 V to 0.5 V and 5.0 V.

Range B, 200 pF and 2000 pF Load

12 µs S PPMU enabled in FV, Range B, DCL disabled; program VIN steps from 0 V to 0.5 V and 5.0 V.

Range C, 200 pF and 2000 pF Load

32 µs S PPMU enabled in FV, Range C, DCL disabled; program VIN steps from 0 V to 0.5 V and 5.0 V.

Force Voltage Settling Time to 1.0% of Final Value

Range A, 200 pF & 2000 pf Load

8.1 µs CB PPMU enabled in FV, Range A, DCL disabled; program VIN steps from 0 V to 5.0 V.

Range B, 200 pF and 2000 pf Load

8.1 µs CB PPMU enabled in FV, Range B, DCL disabled; program VIN steps from 0 V to 5.0 V.

Range C, 200 pF and 2000 pf Load

8.1 µs CB PPMU enabled in FV, Range C, DCL disabled; program VIN steps from 0 V to 5.0 V.

ADATE318 Data Sheet



Range A, 200 pF and 2000 pf Load

2.5 µs CB PPMU enabled in FV, Range A, DCL disabled; program VIN steps from 0 V to 0.5 V.

Range B, 200 pF and 2000 pf Load

6.3 µs CB PPMU enabled in FV, Range B, DCL disabled; program VIN steps from 0 V to 0.5 V.

Range C, 200 pF and 2000 pf Load

8.1 µs CB PPMU enabled in FV, Range C, DCL disabled; program VIN steps from 0 V to 0.5 V.

Force Current Settling Time to 0.1% of Final Value

Range A, 200 pF in Parallel with 120 Ω

16 µs S PPMU enabled in FI, Range A, DCL disabled; program VIN step of 0 mA to 40 mA.

Range B, 200 pF in Parallel with 1.5 KΩ

10 µs S PPMU enabled in FI, Range B, DCL disabled; program VIN step of 0 mA to 1 mA.

Range C, 200 pF in Parallel with 15.0 KΩ

40 µs S PPMU enabled in FI, Range C, DCL disabled; program VIN step of 0 mA to 100 μA.

Force Current Settling Time to 1.0% of Final Value

Range A, 200 pF in Parallel with 120 Ω

8.1 µs CB PPMU enabled in FI, Range A, DCL disabled; program VIN step of 0 mA to 40 mA.

Range B, 200 pF in Parallel with 1.5 KΩ

7.5 µs CB PPMU enabled in FI, Range B, DCL disabled; program VIN step of 0 mA to 1 mA.

Range C, 200 pF in Parallel with 15.0 KΩ

8.1 µs CB PPMU enabled in FI, Range C, DCL disabled; program VIN step of 0 mA to 100 μA.

INTERACTION and CROSSTALK

Measure Voltage Channel-to-Channel Crosstalk

±0.01 %FSR CT 0.01% × 8.5 V = 0.85 mV, PPMU enabled in FIMV, DCL disabled; CHx under test: Range B, forcing 0 mA into 0 V load; other channel: Range A, sweep 0 mA to 40 mA into 0 V load; report ∆V of PPMU_MEASx pin under test.

Measure Current Channel-to-Channel Crosstalk

±0.01 %FSR CT 0.01% × 5.0 V = 0.5 mV, PPMU enabled in FVMI, DCL disabled; CHx under test: Range E, forcing 0 V into 0 mA current load; other channel: Range E, sweep −2.0 V to +6.5 V into 0 mA current load; report ∆V of PPMU_MEASx pin under test.

Table 8. PPMU_Go/No-Go Comparators


Compare Voltage Range −2.0 +6.5 V D

Input Offset Voltage −250 +250 mV P Measured at DAC Code 0x4000 (0 V)

Input Offset Voltage Tempco ±50 μV/ºC CT

Gain 1.0 1.1 V/V P Gain derived from measurements at DAC Code 0x4000 (0 V) and DAC Code 0xC000 (+5.0 V)

Gain Tempco ±25 ppm/ºC CT Applies at m = 1.0 and c = 0.0

Comparator Threshold Resolution 153 µV D

Comparator Threshold DNL ±1 mV CT After two point gain/offset calibration; measured over VOH/VOL range − 2.0 V to +6.5 V; calibration points at 0x4000 (0 V) and 0xC000 (+5 V)

Comparator Threshold INL −7 +7 mV P After two point gain/offset calibration; measured at end points of VOH and VOL functional range

DUTGND Voltage Accuracy −7 ±2 +7 mV P Over ±0.1 V range

Data Sheet ADATE318



Comparator Uncertainty Band 1.6 mV CB Sweep comparator threshold to determine uncertainty (oscillation) band

DC Hysteresis <1 mV CB Sweep comparator threshold

COMPARATOR OUTPUTS PPMU_CMPHx, PPMU_CMPLx

Output Logic High VDD/4 − 0.5

VDD/4 + 0.5

V PF Sourcing 100 μA

Output Logic Low 0 0.5 V PF Sinking 100 μA

Table 9. PPMU_Sense Pin

Parameter Min Typ Max Unit Test Level Condition

PMU_Sx (SYSTEM PMU) SENSE PIN CHARACTERISTICS

Voltage Range −2.0 +7.0 V D DCL high-Z compliance range is −2.0 V to +7.0 V

Ext Sense Switch RON 2.5 kΩ P Push 0.5 mA into PMU_Sx with switch closed and DUTx pin at 0 V; calculate R = V/0.0005

Leakage −2 +2 nA P Tested at −2.0 V and +7.0 V, switch open

Pin Capacitance (PMU_Sx) 0.5 pF S Switch open

PPMU_Sx (INTERNAL PPMU) SENSE PIN CHARACTERISTICS

Voltage Range −2.0 +6.5 V D PPMU input select in all states

Leakage −2 +2 nA P Tested at −2.0 V and +6.5 V

Max Load Capacitance 2 nF S

Table 10. Serial Programmable Interface (SPI) (SDI, RST, CS, SCLK, SDO, BUSY)


Input Logic High 1.8 VCC V PF SDI, RST, CS, SCLK.

Input Logic Low 0 0.7 V PF

Input Bias Current −10 ±1 +10 µA P Tested at 0.0 V and VCC volts.

SCLK Clock Rate 0.5 50 MHz D

SCLK Pulse Width, Minimum 9 ns CT

SCLK Crosstalk on DUTx Pin 30 mV CB DCL disabled; PPMU FV enabled and forcing 0.0 V.

Serial Output Logic High VCC − 0.5 VCC V PF SDO; sourcing 2 mA.

Serial Output Logic Low 0 0.5 V PF Sinking 2 mA.

BUSY Pull-Up Voltage 2.3 2.5 3.5 V D BUSY is an open drain output that pulls low when the SPI requires additional SCLK cycles.

BUSY Active Voltage 0.2 0.8 V PF BUSY active, sinking 2 mA.

ADATE318 Data Sheet


Table 11. VHH Driver (VHH Mode Enabled, RCV Active)


VHH BUFFER VHH mode enabled, RCVx active

Voltage Range 0.0 13.5 V D

Output High 13.5 V P VHH level = full scale, sourcing 15 mA

Output Low 5.9 V P VHH level = zero-scale, sinking 15 mA

Extrapolated Offset −500 +500 mV P Extrapolated from measurements at DAC Code 0x8000 (+7 V) and DAC Code 0xC000 (+12 V)

Extrapolated Offset Tempco ±0.5 mV/ºC CT

Gain 2 2.2 V/V P Gain derived from measurements at DAC Code 0x8000 (+7 V) and DAC Code 0xC000 (+12 V); based on ideal DAC transfer function (see Table 21)

Gain Tempco ±25 ppm/ºC CT

Resolution 305 µV D

INL −25 +25 mV P VHH mode enabled, RCVx active; after two point gain/offset calibration; measured over +5.9 V to +13.5 V; calibrate at Code 0x8000 (+7 V) and Code 0xC000 (+12 V)

DUTGND Voltage Accuracy ±4 mV CT Over ±0.1 V range; measured at end points of VHH functional range

Output Resistance 10 Ω P ∆V/∆I; VHH mode enabled, RCVx active; Source: VHH = +10.0 V, I = 0 mA, +15 mA Sink: VHH = +6.5 V, I = 0 mA, −15 mA

DC Output Current Limit Source +60 +100 mA P VHH mode enabled, RCVx active; VHH = +13.5 V, short HVOUT pin to +5.9 V, measure current

DC Output Current Limit Sink −100 −60 mA P VHH mode enabled, RCVx active, VHH = 5.9 V, short HVOUT pin to 13.5 V, measure current

VHH Rise Time (from VIL or VIH to VHH)

163 ns CB 20% to 80%, VHH mode enabled, toggle RCVx: VHH = 13.5 V, VIL = 0.0 V, VIH = 3.0 V, DATx = high; VHH = 13.5 V, VIL = 3.0 V, VIH = 4.0 V, DATx = low

VHH Fall Time (from VHH to VIL or VIH)

30 ns CB 20% to 80%, VHH mode enabled, toggle RCVx; VHH = 13.5 V, VIL = 0.0 V, VIH = 3.0 V, DATx = high; VHH = 13.5 V, VIL = 3.0 V, VIH = 4.0 V, DATx = low

Preshoot, Overshoot, and Undershoot ±40.0 mV CB VHH mode enabled, toggle RCVx; VHH = 13.5 V, VIL = 0.0 V, VIH = 3.0 V, DATx = high; VHH = 13.5 V, VIL = 3.0 V, VIH = 4.0 V, DATx = low

VIL/VIH DRIVE FUNCTION VHH mode enabled, RCVx inactive

Voltage Range −0.1 +6.5 V D

Offset Voltage −500 +500 mV P Measured at DAC Code 0x4000 (0 V), for DATx = high and DATx = low

Offset Voltage Tempco 1 mV/ºC CT

Gain 1.0 1.1 V/V P Gain derived from measurements at DAC Code 0x4000 (0 V) and DAC Code 0xC000 (5 V); based on ideal DAC transfer function (see Table 21)

Gain Tempco ±75 ppm/ºC CT

Resolution 153 µV D

INL −20 +20 mV P VHH mode enabled, RCVx inactive; after two point gain/offset calibration; measured over −0.1 V to +6.0 V; calibrate at Code 0x4000 (0 V) and Code 0xC000 (+5.0 V)

Data Sheet ADATE318



DUTGND Voltage Accuracy ±2 mV CT Over ±0.1 V range; measured at end points of VIH and VIL functional range

Output Resistance 46 48 50 Ω P ∆V/∆I; VHH mode enabled, RCVx inactive; Source: VIH = +3.0 V, I = +1 mA, +50 mA; Sink: VIL = +2.0 V; I = −1 mA, −50 mA

DC Output Current Limit Source 60 100 mA P VHH mode enabled, RCVx inactive, VIH = +6.0 V, short HVOUT pin to −0.1 V, DATx high, measure current

DC Output Current Limit Sink −100 −60 mA P VHH mode enabled, RCVx inactive, VIL = −0.1 V, short HVOUT pin to +6.0 V, DATx low, measure current

Rise Time, VIL to VIH 6.4 ns CB 20% to 80%, VHH mode enabled, RCVx inactive, VIL = 0.0 V, VIH = 3.0 V, RLOAD > 500 Ω, toggle DATx

Fall Time, VIH to VIL 7.3 ns CB 20% to 80%, VHH mode enabled, RCVx inactive, VIL = 0.0 V, VIH = 3.0 V, RLOAD > 500 Ω, toggle DATx

Preshoot, Overshoot, and Undershoot ±30 mV CB VHH mode enabled, RCVx inactive, VIL = 0.0 V, VIH = 3.0 V, RLOAD > 500 Ω, toggle DATx

Table 12. Alarm Functions


DC CHARACTERISTICS Overvoltage Detect (OVD) See Figure 137

Programmable Voltage Range −2.5 +7.5 V D

Uncalibrated Error at −2.0 V −200 +200 mV P Measured at DAC Code 0x0CCC (−2.0 V); OVD comparators not guaranteed to function as specified if VDUTx is outside absolute maximum voltage range

Uncalibrated Error at +7.0 V −450 +450 mV P Measured at DAC Code 0xF333 (+7.0 V) Offset Voltage Tempco ±0.5 mV/°C CT Gain derived from measurements at DAC Code 0x4000 and

DAC Code 0xC000 Gain 1.045 V/V CT Hysteresis 125 mV CT

Thermal Alarm See Figure 137

Setpoint Error ±10 °C CT Relative to default value, 100°C Thermal Hysteresis −15 °C CT

PPMU Clamp Alarm See Figure 137 and Table 29 for electrical characteristics

ALARM Output Characteristics

Off State Leakage 10 500 nA P Disable alarm, apply 2.5 V to ALARM pin, measure leakage current

Max On Voltage at100 µA 0.1 0.7 V P Activate alarm, force 100 µA into ALARM pin, measure active alarm voltage

Propagation Delay 1.5 µs CB For OVD_HI: VDUTx: 0 V to 6 V swing, OVDH = +3.0 V, OVDL = −1.0 V

For OVD_LO: VDUTx: 0 V to 6 V swing, OVDH = +7.0 V, OVDL= +3.0 V

ADATE318 Data Sheet


SPI TIMING DETAILS

0953

0-00

4

SCLK

CS

SDI A0 D15 D14

0 1 2 3 4 5 6 7 8 9 10 11 24 25 0 1 2 3 4 5 6 7

D1C1 C0 A6 A5 A4 A3 A2 A1

C1 C0 A6 A5 A4 A3 A2 A1 A0

C1 C0 A6 A5 A4 A3 A2 A1

C1 C0 A6 A4 A3 A2 A1 A0D15 D14 D1 D0

D0

SDO

BUSY

tCH

tCLtCSAS

tCSAH

tCSO

tDS

tDH tDO

tCSAM

tCSRS

tCSRH

tCSZ

tBUSA tBUSR

tBUSW

SEE TABLE 18

NOTE 1 NOTE 1

NOTES1. IF THE SPI_SDO_HIZ CONTROL BIT (ADDR 0x12 [1]) IS HIGH, THE SDO PIN BECOMES ACTIVE FOLLOWING THE ASSERTION OF CS. IT BECOMES HIGH-Z FOLLOWING RELEASE OF CS. IF THE SPI_SDO_HIZ CONTROL BIT IS LOW, THE SDO PIN REMAINS ACTIVE INDEPENDENT OF CS.

R/W

R/W

Figure 2. SPI Detailed Read/Write Timing Diagram

0953

0-00

5

SCLK

CS

SDI

SDO

BUSY FROM PREVIOUS SPI INSTRUCTIONS (SEE TABLE 18) SEE TABLE 18

CH[1:0] WADDR[6:0] DATA[15:0]

NOTE 1 NOTE 1ACTIVE – OUTPUT IS THE PREVIOUS SPI WORD SHIFTED INTO SDI

NOTES1. IF THE SPI_SDO_HIZ CONTROL BIT (ADDR 0x12 [1]) IS HIGH, THE SDO PIN BECOMES ACTIVE FOLLOWING THE ASSERTION OF CS. IT BECOMES HIGH-Z FOLLOWING RELEASE OF CS. IF THE SPI_SDO_HIZ CONTROL BIT IS LOW, THE SDO PIN REMAINS ACTIVE INDEPENDENT OF CS.

Figure 3. SPI Write Instruction

Data Sheet ADATE318


0953

0-00

6

. . . . . . . .

. . . . . . . .

. . . . . . . .

. . . . . . . .

SCLK

RST

BUSY

DAC0 PREVIOUS CODE DEFAULT DAC0 CODEVDUTGND

PREVIOUS CODE DEFAULT DAC1 CODEVDUTGND

PREVIOUS CODE DEFAULT DAC23 CODE

INITIALIZEDCONDITION

RESETCONDITION

VDUTGND

DAC1

DAC23

tCH

ASYNCHRONOUSASSERT

tCL

tRStRMIN

tBUSA tBUSR

tBUSWSEE TABLE 18

3µs(DAC DEGLITCH)

Figure 4. SPI Detailed Hardware Reset Timing Diagram

ADATE318 Data Sheet


0953

0-00

7

. . . . . . . .

. . . . . . . .

. . . . . . . .

. . . . . . . .

SCLK

CS

SDI SPI RESET

BUSY

DAC0

DAC1

DAC23



PREVIOUS CODE DEFAULT DAC23 CODE

INITIALIZEDCONDITION

RESETCONDITION

VDUTGND

tCH

tCL

tBUSA tBUSR

tBUSWSEE TABLE 18

3µs(DAC DEGLITCH)

Figure 5. SPI Detailed Software Reset Timing Diagram

0953

0-00

8

SCLK

CS

SDI

SDO

BUSY FROM PREVIOUS SPI INSTRUCTIONS (SEE TABLE 18)

CH[1:0] RADDR[6:0] DATA[15:0] = DON’T CARE

NOTE 1 NOTE 1ACTIVE – OUTPUT IS THE PREVIOUS SPI WORD SHIFTED INTO SDI

NOTES1. IF THE SPI_SDO_HIZ CONTROL BIT (ADDR 0x12 [1]) IS HIGH, THE SDO PIN BECOMES ACTIVE FOLLOWING THEASSERTION

OF CS. IT BECOMES HIGH-Z FOLLOWING RELEASE OF CS. IF THE SPI_SDO_HIZ CONTROL BIT IS LOW, THE SDO PIN ALWAYS REMAINS ACTIVE INDEPENDENT OF CS.

Figure 6. SPI Read Request Instruction (Prior to Readout)

Data Sheet ADATE318


0953

0-00

9

SCLK

CS

SDI

SDO

BUSY SEE TABLE 18

CH[1:0] R/WADDR[6:0] (COULD BE NOP)

CH[1:0] ADDR[6:0] 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DATA[15:0] = (IF NOP, THEN DON’T CARE)

NOTE 1

NOTE 2

NOTE 1

READ OUT DATA[15:0]

NOTES1. IF THE SPI_SDO_HIZ CONTROL BIT (ADDR 0x12 [1]) IS HIGH, THE SDO PIN BECOMES ACTIVE FOLLOWING THE ASSERTION OF CS. IT BECOMES HIGH-Z FOLLOWING RELEASE OF CS. IF THE SPI_SDO_HIZ CONTROL BIT IS LOW, THE SDO PIN REMAINS ACTIVE INDEPENDENT OF CS.2. THE FIRST 10 BITS OF SDO FOLLOWING A READ REQUEST ECHO ADDRESS AND CHANNEL BITS OF THE PRECEDING REQUEST. THE R/W BIT POSITION IS SET LOW. THE FOLLOWING 16 BITS CONTAIN DATA FROM THE REQUESTED ADDRESS AND CHANNEL.

Figure 7. SPI Readout Instruction (Subsequent to Read Request)

ADATE318 Data Sheet


Table 13. SPI Detailed Timing Requirements

Parameter Min Max Unit Test Level Description

fCLK 0.5 50 MHz CT SCLK operating frequency. tCH 9 ns CT SCLK high time. tCL 9 ns CT SCLK low time. tCSAS 3 ns CT Setup of CS to rising SCLK at assert.

tCSAH 3 ns CT Hold of CS to rising SCLK at assert.

tCSRS 3 ns CT Setup of CS to rising SCLK at release.

tCSRH 3 ns CT Hold of CS to rising SCLK at release.

4 ns CT Hold of CS release prior to rising SCLK. This parameter is critical only if the number of SCLK cycles from the previous release of CS is the minimum specified by the tCSAM parameter.

tCSO 6 ns CT Delay from CS assert to SDO active.

tCSZ 10 ns CT Delay from CS release to SDO high-Z, depends greatly on external pin loading.

tCSAM 3 Cycles CT Width of CS release between consecutive assertions of CS. This parameter is specified in units of SCLK cycles, more specifically in terms of rising edges of the SCLK input.

tDS 3 ns CT Setup of SDI data prior to rising SCLK. tDH 4 ns CT Hold of SDI data following rising SCLK. tDO 12 ns CT Delay of SDO data from rising SCLK. tBUSA 12 ns CT Delay of BUSY assert from first rising SCLK following a valid CS release or an

asynchronous RSTb release. tBUSW 3 26 Cycles CT Width of BUSY assert. To ensure proper SPI operation, the SCLK must be provided

for as long as BUSY remains asserted. Note that the number of SCLK cycles within any BUSY period is variable but deterministic and is based on the previous SPI write instruction type. See the Use of the SPI BUSY Pin section and Figure 2, Figure 4, Figure 5, and Table 18 for more information.

tBUSR 12 ns CT Delay of BUSY release from first rising SCLK, satisfying the requirements detailed in the Use of the SPI BUSY Pin section.

tRMIN 10 ns CT Width of asynchronous RST assert.

tRS 3 ns CT Setup of RST to rising SCLK at release.

tSPI 29 Cycles CT Number of SCLK rising edge cycles per SPI word write plus the additional tCSAM requirement.

tDAC 5 10 μs S Settling time of analog DAC levels to ±0.5 LSB relative to the beginning of the DAC deglitch period, which begins x SCLK cycles following the release of CS and four SCLK cycles prior to the release of the BUSY pin. The number of SCLK cycles, x, is defined by Table 18. Also see Figure 126 for more information.

Data Sheet ADATE318


ABSOLUTE MAXIMUM RATINGS Table 14. Absolute Maximum Ratings Parameter Rating Supply Voltages Positive Supply Voltage (VDD to PGND) −0.5 V to +11.0 V

Positive VCC Supply Voltage (VCC to DGND)

−0.5 V to +4.0 V

Negative Supply Voltage (VSS to PGND) −6.5 V to +0.5 V

Supply Voltage Difference (VDD to VSS) −1.0 V to +17.0 V Reference Ground (DUTGND to AGND) −0.5 V to +0.5 V VPLUS Supply Voltage (VPLUS to PGND) −0.5 V to +19.0 V Supply Sequence or Dropout

Condition1 Input/Output Voltages

Analog Input Common-Mode Voltage

VSS to VDD

DUTx Output Short Circuit Voltage2 −3.0 V to +8.0 V High Speed Input Voltage Absolute

Range3 −0.5 V to VTTC + 0.5 V

High Speed Differential Input Voltage3

−1.0 V to +1.0 V

DUTx I/O Pin Current DCL Maximum Short-Circuit Current4 ±140 mA

Temperature Operating Temperature, Junction 125°C Storage Temperature Range −65°C to +150°C

1 No supply should exceed the given ratings. 2 RLOAD = 0 Ω, VDUTx continuous short-circuit condition (VIH, VIL, VIT),

high-Z, VCOM, and clamp modes). 3 DAT, DAT, RCV, RCV, RSOURCE = 0 Ω. 4 RLOAD = 0 Ω, VDUTx = −3 V to +8 V; DCL current limit. Continuous short-circuit

condition. ADATE318 current limits and survives a continuous short-circuit fault.

Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 15. Thermal Resistance Package Type θJA θJC Unit Airflow 0 1 2 m/s LFCSP 45 40 37 1 °C/W

Table 16. Explanation of Test Levels Test Level Description D Definition S Design verification simulation P 100% production tested PF Functionally checked during production test CT Characterized on tester CB Characterized on bench

ESD CAUTION

ADATE318 Data Sheet


PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NOTES1. EXPOSED PADDLE IS INTERNALLY CONNECTED VIA HIGH IMPEDANCE TO VSS (SUBSTRATE).2. NC = THIS PIN IS OPEN. NO INTERNAL CONNECTION. 09

530-

002

1VDD_THERM2PPMU_S13THERM4DAT15DAT16NC7RCV18RCV19SCAP1

10FFCAPB111FFCAPA112CMPL113CMPL114VTTC115CMPH116CMPH117PGND18VDD19VSS20PPMU_CMPH1

22A

GN

D23

PPM

U_C

MPL

124

PPM

U_M

EAS1

25D

GN

D26

DU

TGN

D27

ALA

RM

28VS

S29

DG

ND

30C

S31

BU

SY32

SDO

33SC

LK34

SDI

35VC

C36

VDD

37R

ST38

VREF

39VR

EFG

ND

40PP

MU

_MEA

S0

55 SCAP056 RCV057 RCV058 NC59 DAT060 DAT061 HVOUT62 PPMU_S063 VPLUS

54 FFCAPB053 FFCAPA052 CMPL051 CMPL050 VTTC049 CMPH048 CMPH047 PGND46 VDD45 VSS44 PPMU_CMPH043 AGND

75VS

S76

VDD

77PG

ND

78VS

S79

VSSO

180

DU

T181

VDD

O1

82VD

D83

PMU

_S1

84VS

S

74A

GN

D73

VSS

72VD

D71

PGN

D70

VSS

69VS

SO0

68D

UT0

67VD

DO

066

VDD

65PM

U_S

064

VSS

ADATE318TOP VIEW

(Not to Scale)84-LEAD 10mm × 10mm LFCSP

(HEATSINK FACE UP,DIE FACE DOWN)

21AGND

41PP

MU

_CM

PL0

42A

GN

D

PIN 1IDENTIFIER

Figure 8. LFCSP Pin Configuration

Table 17. Pin Function Descriptions Pin Mnemonic Description

EP Exposed Paddle Exposed paddle is internally connected via high impedance to VSS (substrate). 1 VDD_THERM Temperature Sensor VDD Supply. 2 PPMU_S1 PPMU External Sense Connect, Channel 1. 3 THERM Temperature Sensor Analog Output. 4 DAT1 High Speed Data Input, Channel 1. 5 DAT1 High Speed Data Input Complement, Channel 1.

6 NC This pin is open. No internal connection. 7 RCV1 High Speed Receive Input, Channel 1. 8 RCV High Speed Receive Input Complement, Channel 1.

9 SCAP1 PPMU External Compensation Capacitor, Channel 1. 10 FFCAPB1 PPMU External Feed Forward Capacitor Pin B, Channel 1. 11 FFCAPA1 PPMU External Feed Forward Capacitor Pin A, Channel 1. 12 CMPL1 High Speed Comparator Low Output, Channel 1. 13 CMPL1 High Speed Comparator Low Output Complement, Channel 1.

14 VTTC1 Comparator Supply Termination, Channel 1. 15 CMPH1 High Speed Comparator High Output Complement, Channel 1.

16 CMPH1 High Speed Comparator High Output, Channel 1. 17 PGND Power Ground. 18 VDD VDD Supply. 19 VSS VSS Supply. 20 PPMU_CMPH1 PPMU Go/No-Go Comparator High Output, Channel 1. 21 AGND Analog Ground. 22 AGND Analog Ground. 23 PPMU_CMPL1 PPMU Go/No-Go Comparator Low Output, Channel 1.

Data Sheet ADATE318


Pin Mnemonic Description

24 PPMU_MEAS1 PPMU Analog Measure Output, Channel 1. 25 DGND Digital Logic Ground. 26 DUTGND DUT Ground Sense Input. 27 ALARM Fault Alarm Open Drain Output.

28 VSS VSS Supply. 29 DGND Digital Logic Ground. 30 CS Serial Programmable Interface (SPI) Chip Select Input (Active Low).

31 BUSY Serial Programmable Interface (SPI) Busy Output (Active Low).

32 SDO Serial Programmable Interface (SPI) Serial Data Output. 33 SCLK Serial Programmable Interface (SPI) Clock Input. 34 SDI Serial Programmable Interface (SPI) Serial Data Input. 35 VCC VCC Supply. 36 VDD VDD Supply. 37 RST Reset Input (Active Low).

38 VREF DAC Precision +5.0 V Reference Input. 39 VREFGND DAC Precision +0.0 V Reference Input. 40 PPMU_MEAS0 PPMU Analog Measure Output, Channel 0. 41 PPMU_CMPL0 PPMU Go/No-Go Comparator Low Output, Channel 0. 42 AGND Analog Ground. 43 AGND Analog Ground. 44 PPMU_CMPH0 PPMU Go/No-go Comparator High Output, Channel 0. 45 VSS VSS Supply. 46 VDD VDD Supply. 47 PGND Power Ground. 48 CMPH0 High Speed Comparator High Output, Channel 0. 49 CMPH0 High Speed Comparator High Output Complement, Channel 0.

50 VTTC0 Comparator Supply Termination, Channel 0. 51 CMPL0 High Speed Comparator Low Output Complement, Channel 0.

52 CMPL0 High Speed Comparator Low Output, Channel 0. 53 FFCAPA0 PPMU External Feed Forward Capacitor Pin A, Channel 0. 54 FFCAPB0 PPMU External Feed Forward Capacitor Pin B, Channel 0. 55 SCAP0 PPMU External Compensation Capacitor, Channel 0. 56 RCV0 High Speed Receive Input Complement, Channel 0.

57 RCV0 High Speed Receive Input, Channel 0. 58 NC This pin is open. No internal connection. 59 DAT0 High Speed Data Input Complement, Channel 0.

60 DAT0 High Speed Data Input, Channel 0. 61 HVOUT VHH Output Pin. 62 PPMU_S0 PPMU External Sense Connect, Channel 0. 63 VPLUS VPLUS Supply. 64 VSS VSS Supply. 65 PMU_S0 System PMU Sense Input, Channel 0. 66 VDD VDD Supply. 67 VDDO0 VDD Supply, Driver Output Stage, Channel 0. 68 DUT0 DUT Pin, Channel 0. 69 VSSO0 VSS Supply, Driver Output Stage, Channel 0. 70 VSS VSS Supply. 71 PGND Power Ground. 72 VDD VDD Supply. 73 VSS VSS Supply. 74 AGND Analog Ground.

ADATE318 Data Sheet


Pin Mnemonic Description

75 VSS VSS Supply. 76 VDD VDD Supply. 77 PGND Power Ground. 78 VSS VSS Supply. 79 VSSO1 VSS Supply, Driver Output Stage, Channel 1. 80 DUT1 DUT Pin, Channel 1. 81 VDDO1 VDD Supply, Driver Output Stage, Channel 1. 82 VDD VDD Supply. 83 PMU_S1 System PMU Sense Input, Channel 1. 84 VSS VSS Supply.

Data Sheet ADATE318


TYPICAL PERFORMANCE CHARACTERISTICS

0953

0-10

1

0.05

–0.05

0

0.10

–0.10

0.15

0.20

0.25

0.30

0.35

0 2 4 6TIME (ns)

8 10 12 14 16 18 20

VOLT

AG

E (V

)

500mV

200mV

Figure 9. Driver Small Signal Response, VIH = 0.2 V, 0.5 V, VIL = 0.0 V, 50 Ω Termination

0953

0-10

2

–0.2

–0.4

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

0 2 4 6 8 10 12 14 16 18 20

VOLT

AGE

(V)

TIME (ns)

2V

1V

3V

Figure 10. Driver Large Signal Response, VIH = 1.0 V, 2.0 V, 3.0 V; VIL = 0.0 V, 50 Ω Termination

1V

5V

3V

0953

0-10

3–1

0

1

2

3

4

5

6

0 2 4 6 8 10 12 14 16 18 20

VOLT

AG

E (V

)

TIME (ns)

Figure 11. Driver Large Signal Response, VIH = 1.0 V, 3.0 V, 5.0 V; VIL = 0.0 V, 50 Ω Unterminated

0953

0-10

4

–0.2

–0.4

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

1.8

0 2 4 6 8 10 12 14 16 18

VOLT

AG

E (V

)

20TIME (ns)

1V2V3V

Figure 12. 100 MHz Driver Response, VIH = 1. 0 V, 2.0 V, 3.0 V; VIL = 0.0 V, 50 Ω Termination

0953

0-10

5–0.2

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

1.8

0 2 4 6

VOLT

AGE

(V)

108

TIME (ns)

1V2V3V

Figure 13. 300 MHz Driver Response, VIH = 1.0 V, 2.0 V, 3.0 V; VIL = 0.0 V, 50 Ω Termination

0953

0-10

6–0.2

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

1.8

0 2 4 6

VOLT

AG

E (V

)

108

0.5V1V2V3V

TIME (ns)

Figure 14. 400 MHz Driver Response, VIH = 0.5 V, 1.0 V, 2.0 V, 3.0 V; VIL = 0.0 V, 50 Ω Termination

ADATE318 Data Sheet


0953

0-10

8–0.2

1.2

1.0

0.8

0.6

0.4

0.2

0

0 1 2 3

VO

LT

AG

E (

V)

54

TIME (ns)

0.5V1V2V

Figure 15. 600 MHz Driver Response, VIH = 0.5 V, 1.0 V, 2.0 V; VIL = 0.0 V, 50 Ω Termination

0953

0-10

9–0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

0 5 10 15 20

VO

LT

AG

E (

V)

TIME (ns)

VIH TO/FROM VIT

VIL TO/FROM VIT

Figure 16. Driver Active (VIH/VIL) to/from VTERM Transition; VIH = 1.0 V, VIT = 0.5 V; VIL = 0.0 V, 50 Ω Termination

0953

0-11

0–0.2

0

0.2

0.4

0.6

0.8

1.0

1.2

0 5 10 15 20

VO

LT

AG

E (

V)

TIME (ns)

VIL TO/FROM VIT

VIH TO/FROM VIT

Figure 17. Driver Active (VIH/VIL) to/from VTERM Transition; VIH = 2.0 V, VIT = 1.0 V; VIL = 0.0 V, 50 Ω Termination

0953

0-11

1–0.2

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

0 5 10

VO

LT

AG

E (

V)

2015

TIME (ns)

VIH TO/FROM VIT

VIL TO/FROM VIT

Figure 18. Driver Active (VIH/VIL) to/from VTERM Transition; VIH =3.0 V, VIT = 1.5 V; VIL = 0.0 V, 50 Ω Termination

0953

0-11

2

–10

–30

–50

70

90

50

30

10

0 2

PULSE WIDTH (ns)

4 6

TR

AIL

ING

ED

GE

ER

RO

R (

ps)

108

POSITIVE PULSENEGATIVE PULSE

Figure 19. Driver Trailing Edge Timing Error Pulse Width, VIH = 0.2 V; VIL = 0.0 V, 50 Ω Termination

0953

0-11

3

–10

–30

–50

70

90

50

30

10

0 2

PULSE WIDTH (ns)

4 6

TR

AIL

ING

ED

GE

ER

RO

R (

ps)

108


Figure 20. Driver Trailing Edge Timing Error vs. Pulse Width, VIH = 0.5 V; VIL = 0.0 V, 50 Ω Termination

Data Sheet ADATE318


0953

0-11

4

–10

–30

–50

70

50

30

10

0

0 2

PULSE WIDTH (ns)

4 6

TRAI

LING

EDG

E ER

ROR

(ps)

108



0953

0-11

5

–10

–30

–50

70

90

50

30

10

0 2

PULSE WIDTH (ns)

4 6

TRA

ILIN

G E

DG

E ER

RO

R (p

s)

108



0953

0-11

6

–20

–80

–60

–40

–100

80

100

60

40

20

0

0 2

PULSE WIDTH (ns)

4 6

TRAI

LING

EDG

E ER

ROR

(ps)

108



0953

0-11

7

0

–0.5

–1.0

1.5

1.0

0.5

–2 0–1DRIVER OUTPUT VOLTAGE (V)

31 42

LINE

ARIT

Y ER

ROR

(mV)

75 6

Figure 24. Driver VIH Linearity Error

0953

0-11

8

0

–0.5

–1.0

1.5

1.0

0.5


31 42

LINE

ARIT

Y ER

ROR

(mV)

75 6

Figure 25. Driver VIL Linearity Error

0953

0-11

9

0

–0.5

–1.0

1.5

1.0

0.5


31 42

LINE

ARIT

Y ER

ROR

(mV)

75 6

Figure 26. Driver VIT Linearity Error

ADATE318 Data Sheet


0953

0-12

0

0.10

0.20

0.15

–0.05

0

0.05

–0.10

0.25

0–1–2 21

VIL PROGRAMMED DAC VOLTAGE (V)

43 5

INTE

RA

CTI

ON

ER

RO

R (m

V)

76

Figure 27. Driver Interaction Error VIH vs. VIL, VIH = +6.5 V, VIL Swept from −1.5 V to +6.5 V

0953

0-12

1

0.02

0.06

0.04

–0.04

–0.02

0

–0.06

0.08

0–1–2 21

VIH PROGRAMMED DAC VOLTAGE (V)

43 5

INTE

RA

CTI

ON

ER

RO

R (m

V)

76

Figure 28. Driver Interaction Error VIL vs. VIH; VIL = −1.5 V, VIH Swept from −1.5 V to +6.5 V

0953

0-12

2

0.4

0.6

0.7

0.5

0.1

0

0.2

0.3

–0.1

0.8

0–1–2 21

VIH PROGRAMMED DAC VOLTAGE (V)

43 5

INTE

RACT

ION

ERRO

R (m

V)

76

Figure 29. Driver Interaction Error VIT vs. VIH, VIT = +1.0 V, VIH Swept from −1.5 V to +6.5 V

0953

0-12

3

49.0

49.5

48.0

48.5

47.5

50.0

–40 –20–60 0

DRIVER OUTPUT CURRENT (mA)

20

DRIV

ER O

UTPU

T RE

SIST

ANCE

(Ω)

6040

Figure 30. Driver Output Resistance vs. Output Current

0953

0-12

4

40

100

80

60

0

20

120

0–1–2 21

VDUT (V)

43 5

DR

IVER

OU

TPU

T C

UR

REN

T (m

A)

76

Figure 31. Driver Output Current Limit; Driver Programmed to −1.5 V, VDUT Swept −1.5 V to +6.5 V

0953

0-12

5

–80

–20

–40

–60

–120

–100

0

0–1–2 21

VDUT (V)

43 5

DR

IVER

OU

TPU

T C

UR

REN

T (m

A)

76

Figure 32. Driver Output Current Limit. Driver Programmed to 6.5 V, VDUT Swept −1.5 V to +6.5 V

Data Sheet ADATE318


0953

0-12

6

6

2

4

0

14

16

VHH OUTPUT

12

10

8

0 0.5

TIME (µs)

1.0

VOLT

AG

E (V

)

2.01.5

Figure 33. HVOUT Transient Response, VHH = 13.5 V

0953

0-12

7

–2

–4

–5

–6

–3

–7

2

3

1

0

–1

–1 1HVOUT OUTPUT VOLTAGE (V)

3

LIN

EAR

ITY

ERR

OR

(mV)

750 2 4 6

Figure 34. HVOUT VIH Linearity Error

0953

0-12

8

–2

–4

–5

–6

–3

–7

2

3

1

0

–1

–1 1HVOUT OUTPUT VOLTAGE (V)

3

LIN

EAR

ITY

ERR

OR

(mV)

750 2 4 6

Figure 35. HVOUT VIL Linearity Error

0953

0-12

9

–10

–5

–15

10

5

0

1HVOUT OUTPUT VOLTAGE (V)

3

LIN

EAR

ITY

ERR

OR

(mV)

7 8 9 10 11 12 13 14 1550 2 4 6

Figure 36. HVOUT VHH Linearity Error

0953

0-13

0

60

70

50

100

90

30

20

10

0

80

40

VHVOUT (V)

HVO

UT

DR

IVER

CU

RR

ENT

(mA

)

7 8 9 10 11 12 13 14 155 6

Figure 37. HVOUT VHH Output Current Limit; VHH = 5.9 V, HVOUT Swept 5.9 V to 13.5 V

0953

0-13

1

–20

–10

–30

20

10

–50

–60

–70

–80

–90

0

–40

VHVOUT (V)

HVO

UT D

RIVE

R CU

RREN

T (m

A)

7 8 9 10 11 12 13 14 155 6

Figure 38. HVOUT VHH Output Current Limit; VHH = 13.5 V, HVOUT Swept 5.9 V to 13.5 V

ADATE318 Data Sheet


0953

0-13

2–10

70

80

60

50

40

30

20

10

0

–1 1VHVOUT (V)

3

HVO

UT

DR

IVER

CU

RR

ENT

(mA

)

750 2 4 6

Figure 39. HVOUT VIL Output Current Limit; VIL = −0.1 V, HVOUT Swept −0.1 V to 6.0 V

0953

0-13

3

–20

–10

–30

10

0

–50

–60

–70

–80

–90

–40

VHVOUT (V)

HVO

UT

DR

IVER

CU

RR

ENT

(mA

)

1 2 3 4 5 6 7–1 0

Figure 40. HVOUT VIH Output Current Limit; VIH = 6.0 V, HVOUT Swept −0.1 V to 6.0 V

0953

0-13

4

0.4

0

0.2

–0.2

1.0

1.2

0.8

INPUTEDGE

0.6

0 2TIME (ns)

4

VOLT

AG

E (V

)

8 106

SHMOO

Figure 41. Normal Window Comparator Shmoo 1.0 V Swing; 50 Ω Termination, 200 ps (20% to 80%)

0953

0-19

0

0.4

0

0.2

–0.2

1.0

1.2

0.8

INPUTEDGE

0.6

0 2TIME (ns)

4

VOLT

AG

E (V

)

8 106

SHMOO

Figure 42. Normal Window Comparator Shmoo; 1.0 V Swing, 50 Ω Termination, 200 ps (20% to 80%)

0953

0-19

1

–15

–25

–20

–30

0

5

–5

–10

0 2PULSE WIDTH (ns)

4

TRA

ILIN

G E

DG

E (p

s)

8 106


Figure 43. Normal Window Comparator Trailing Edge Timing Error vs. Input Pulse Width; 50 Ω Termination, 1.0 V Swing, 200 ps (20% to 80%)

0953

0-19

2

–4

–8

–10

–12

–14

–16

–6

–18

0

–2

0.4 0.5INPUT TRANSITION TIME (20%/80%) (ns)

0.6

PRO

PAG

ATI

ON

DEL

AY

VAR

IATI

ON

(ps)

0.8 0.9 1.00.7

INPUT VOLTAGE SWING = 1VCOMPARATOR THRESHOLD = 0.5V

INPUT RISING EDGEINPUT FALLING EDGE

Figure 44. Normal Window Comparator Input Transition Time (20%/80%), 50 Ω Termination

Data Sheet ADATE318


0953

0-13

80

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0 5 10 15 20

VOLT

AG

E (V

)

TIME (ns)

Figure 45. Comparator Output Waveform

0953

0-13

9

–0.8

–0.2

–0.4

–0.6

–2.0

–1.0

–1.2

–1.4

–1.6

–1.8

0

0–1–2 21THRESHOLD VOLTAGE (V)

43 5

LINE

ARIT

Y ER

ROR

(mV)

76

Figure 46. Normal Window Comparator Threshold Linearity Error

0953

0-14

0

0.5

0

1.0

1.5

–1.0

–1.5

–0.5

–2.0

2.0

–1.0 –0.5–1.5 0THRESHOLD VOLTAGE (V)

0.5

LIN

EAR

ITY

ERR

OR

(mV)

1.51.0

Figure 47. Differential Comparator Threshold Linearity Error

0953

0-14

1

0

0.05

–0.05

0.20

0.15

–0.15

–0.20

–0.25

0.10

–0.10

–2THRESHOLD VOLTAGE (V)

–1

LIN

EAR

ITY

ERR

OR

(mV)

2 3 4 5 6 7–3 0 1

Figure 48. PPMU Go/No-Go Comparator Linearity Error

0953

0-14

2

1.5

2.0

0

1.0

0.5

2.5

0–1–2 21INPUT COMMON-MODE VOLTAGE (V)

43 5

DIF

FER

ENTI

AL

CO

MPA

RA

TOR

OFF

SET

(mV)

76

Figure 49. Differential Comparator CMR Error

0953

0-14

3–5

0

5

10

15

20

25

30

0 5 10 15 15 20

LOA

D C

UR

REN

T (m

A)

TIME (ns)

CURRENT VIL TO LOADCURRENT LOAD TO VIL

Figure 50. Active Load Response to/from Drive VIL = 0 V, 50 Ω Termination, IOL = 25 mA, VCOM = 2 V

ADATE318 Data Sheet


0953

0-14

4

10

0

30

20

–20

–30

–10

–2VDUT (V)

–1

LOA

D C

UR

REN

T (m

A)

2 3 4 5 6 7–3 0 1

Figure 51. Active Load Commutation Response, VCOM = 2.0 V, IOH = IOL = 25 mA

0953

0-14

5

5

15

10

–10

–5

0

–15

20

50 10

ACTIVE LOAD CURRENT (mA)

15 20

LINE

ARIT

Y ER

ROR

(µA)

25

Figure 52. Active Load IOH Linearity Error

0953

0-14

6

–0.8

–0.2

–0.4

–0.6

–1.0

–1.2

0

0–1–2 21VCOM VOLTAGE (V)

43 5

LINE

ARIT

Y ER

ROR

(mV)

76

Figure 53. Active Load VCOM Linearity Error

0953

0-14

7

4

2

8

6

–4

–2

0

–6

10

50 10ACTIVE LOAD CURRENT (mA)

15 20

LIN

EAR

ITY

ERR

OR

(µA

)

25

Figure 54. Active Load IOL Linearity Error

0953

0-14

8

–2.0

–1.5

–2.5

0

–0.5

–3.5

–4.0

–4.5

–1.0

–3.0

–2VDUT (V)

–1

LEAK

AGE

(nA)

2 3 4 5 6 7–3 0 1

Figure 55. DUTx Pin Leakage in Low Leakage Mode

0953

0-14

9

150

100

250

200

0

–50

50

–2VDUT (V)

–1

LEA

KA

GE

(nA

)

2 3 4 5 6 7 8–3 0 1

Figure 56. DUTx Pin Leakage in High-Z Mode

Data Sheet ADATE318


0953

0-15

0

2.0

1.5

3.0

2.5

0.5

0

1.0

DUTGND VOLTAGE (V)–0.10

ERR

OR

(mV)

0 0.05 0.10 0.15–0.15 –0.05

Figure 57. Typical DUTGND Transfer Function Voltage Error, Drive Low VIL = 0 V

0953

0-15

1

–0.2

–0.3

0.1

0

–0.1

–0.4

–0.5

0.2

0–1–2 21PMU OUTPUT VOLTAGE (V)

43 5

LINE

ARIT

Y ER

ROR

(mV)

76

Figure 58. PPMU Force Voltage Linearity Error, All Ranges

0953

0-15

2

0

–5

10

5

–10

15

–30 –20 –10–40 0PMU OUTPUT CURRENT (mA)

10 20

LIN

EAR

ITY

ERR

OR

(µA

)

4030

Figure 59. PPMU Range A Force Current Linearity Error

0953

0-15

3

–0.05

0.10

0.05

0

–0.15

–0.10

0.15

–0.5–1.0 0PMU OUTPUT CURRENT (mA)

0.5

LIN

EAR

ITY

ERR

OR

(µA

)

1.0

Figure 60. PPMU Range B Force Current Linearity Error

0953

0-15

4

0.016

0.012

0.010

0.004

0.002

0

0.006

0.014

0.008

0.018


0.05

LIN

EAR

ITY

ERR

OR

(µA

)

0.10

Figure 61. PPMU Range C Force Current Linearity Error

0953

0-15

5

0.0005

–0.0005

–0.0010

0

0.0010

0.0015


0.005

LIN

EAR

ITY

ERR

OR

(µA

)

0.010

Figure 62. PPMU Range D Force Current Linearity Error

ADATE318 Data Sheet


0953

0-15

6

–0.0001

–0.0003

–0.0004

–0.0005

–0.0002

–0.0006

0.0003

0.0004

0.0002

0.0001

0

–0.0020 –0.0010PMU OUTPUT CURRENT (mA)

0

LIN

EAR

ITY

ERR

OR

(µA

)

0.00200.0010–0.0015 –0.0005 0.0005 0.0015

Figure 63. PPMU Range E Force Current Linearity Error 09

530-

157

0

–10

–15

–20

–5

–25

20

25

15

10

5

–40 –20IDUT (mA)

0

ERRO

R (m

V)

4020–30 –10 10 30

Figure 64. PPMU Force Voltage Range A Compliance Error at −2.0 V vs. Output Current, Internal Sense

0953

0-15

8

0

–10

–15

–20

–5

–25

20

25

15

10

5

–40 –20IDUT (mA)

0

ERRO

R (m

V)

4020–30 –10 10 30

Figure 65. PPMU Force Voltage Range A Compliance Error at +5.75 V vs. Output Current, Internal Sense

0953

0-15

9

–0.1

0.4

0.3

0.1

0.2

0

–0.5

–0.2

–0.3

–0.4

0.5

–0.5–1.0 0IDUT (mA)

0.5

ERR

OR

(mV)

1.0

Figure 66. PPMU Force Voltage Range B Compliance Error at −2.0 V vs. Output Current, Internal Sense

0953

0-16

0

–0.1

0.3

0.1

0.2

0

–0.2

–0.3

–0.4–0.5–1.0 0

IDUT (mA)0.5

ERR

OR

(mV)

1.0

Figure 67. PPMU Force Voltage Range B Compliance Error at +6.5 V vs. Output Current, Internal Sense

0953

0-16

1

0

–5

10

5

20

15

–1 0 1–2 2VDUT (V)

3 4

ERR

OR

(µA

)

65

Figure 68. PPMU Force Current Range A Compliance Error at −40 mA vs. Output Voltage

Data Sheet ADATE318


0953

0-16

2

0

–5

10

5

20

25

30

35

15

–1 0 1–2 2VDUT (V)

3 4

ERR

OR

(µA

)

65

Figure 69. PPMU Force Current Range A Compliance Error at +40 mA vs. Output Voltage

0953

0-16

3

0

–0.05

0.10

0.05

0.20

0.25

0.30

0.15

–1 0 1–2 2VDUT (V)

3 4

ERR

OR

(µA

)

6 75

Figure 70. PPMU Force Current Range B Compliance Error at −1 mA vs. Output Voltage

0953

0-16

4

0

–0.1

0.2

0.1

0.3

0.4

0.5

–1 0 1–2 2VDUT (V)

3 4

ERRO

R (µ

A)

6 75

Figure 71. PPMU Force Current Range B Compliance Error at +1 mA vs. Output Voltage

0953

0-16

5

–0.0005

–0.0010

0.0005

0

0.0010

0.0015

0.0020

–1 0 1–2 2VDUT (V)

3 4

ERR

OR

(µA

)

6 75

Figure 72. PPMU Force Current Range E Compliance Error at −2 μA vs. Output Voltage

0953

0-16

6–0.0005

0.0005

0

0.0010

0.0015

0.0020

–1 0 1–2 2VDUT (V)

3 4

ERR

OR

(µA

)

6 75

Figure 73. PPMU Force Current Range E Compliance Error at +2 μA vs. Output Voltage

0953

0-16

7

20

10

30

0

40

50

60

–1 0 1–2–3 2VDUT (V)

3 4

PPM

U O

UTP

UT

CU

RR

ENT

(mA

)

6 75

Figure 74. PPMU Force Voltage Output Current Limit Range A, FV = −2.0 V, VDUT Swept −2.0 V to +6.5 V

ADATE318 Data Sheet


0953

0-16

8

–50

–60

–30

–40

–20

–10

0

10

–1 0 1–2–3 2VDUT (V)

3 4

PPM

U O

UTP

UT

CU

RR

ENT

(mA

)

6 75

Figure 75. PPMU Force Voltage Output Current Limit Range A, FV = +6.5 V, VDUT Swept −2.0 V to +6.5 V

0953

0-16

9

2.65

2.60

2.75

2.70

2.80

2.85

2.90

–1 0 1–2–3 2VDUT (V)

3 4

PPM

U O

UTPU

T CU

RREN

T (µ

A)

6 75

Figure 76. PPMU Force Voltage Output Current Limit Range E, FV = −2.0 V, VDUT Swept −2.0 V to +6.5 V

0953

0-17

0

–3

–4

–1

–2

0

1

2

3

–1 0 1–2–3 2VDUT (V)

3 4

PPM

U O

UTP

UT

CU

RR

ENT

(µA

)

6 75

Figure 77. PPMU Force Voltage Output Current Limit Range E, FV = 6.5 V, VDUT Swept −2.0 V to +6.5 V

0953

0-17

1

0

0.02

–0.02

0.03

–0.03

0.04

–0.04

–0.05

–0.06

0.01

–0.01

–1 0 1–2 2VDUT (V)

3 4

LIN

EAR

ITY

ERR

OR

(mV)

6 75

Figure 78. PPMU Range B Measure Voltage Linearity Error

0953

0-17

2

0.10

0.06

0.04

–0.02

–0.04

–0.06

0

0.08

0.02

0.12

–0.5–1.0 0IDUT (mA)

0.5

LIN

EAR

ITY

ERR

OR

(µA

)

1.0

Figure 79. PPMU Range B Measure Current Linearity Error

0953

0-17

3

0.10

–0.10

–0.15

–0.20

–0.25

–0.30

–0.35

–0.40

–0.45

0.05

–0.05

0

–1 0 1–2 2VDUT (V)

3 4

PPM

U_M

EAS0

PIN

ER

RO

R (m

V)1m

V =

~400

nA

65

Figure 80. PPMU Measure Current CMR Error, (FVMI), Sourcing 0.5 mA

Data Sheet ADATE318


0953

0-17

4

0.4

0.6

0.2

1.2

1.0

–0.2

–0.4

–0.6

0.8

0

–2OUTPUT VOLTAGE (V)

–1

LIN

EAR

ITY

ERR

OR

(mV)

2 3 4 5 6 7–3 0 1

Figure 81. Reflection Clamp VCL Linearity Error

0953

0-17

5

0.1

0.2

0.5

0.4

–0.1

–0.2

–0.3

–0.4

–0.5

0.3

0

–2OUTPUT VOLTAGE (V)

–1

LIN

EAR

ITY

ERR

OR

(mV)

2 3 4 5 6 7 80 1

Figure 82. Reflection Clamp VCH Linearity Error

0953

0-17

6

1

2

–2

–1

–3

–4

–5

0

–2–3OUTPUT VOLTAGE (V)

–1

LIN

EAR

ITY

ERR

OR

(mV)

2 3 4 50 1

Figure 83. PPMU Voltage Clamp VCL Linearity Error

0953

0-17

7

1.5

1.0

0.5

2.0

–0.5

–1.0

–1.5

–2.0

0

OUTPUT VOLTAGE (V)

LIN

EAR

ITY

ERR

OR

(mV)

2 3 4 5 6 70 1

Figure 84. PPMU Voltage Clamp VCH Linearity Error

0953

0-17

8

0

–70

–60

–50

–40

–30

–20

–10

–80

–90

–100–2–3

VDUT (V)–1

OU

TPU

T C

UR

REN

T (m

A)

2 3 4 5 60 1

Figure 85. VCL Reflection Clamp Current Limit; VCH = 6 V, VCL = 5 V, VDUT Swept −2.0 V to +5.0 V

0953

0-17

9

90

30

40

50

60

70

80

20

10

010

VDUT (V)2

OU

TPU

T C

UR

REN

T (m

A)

4 5 6 7 83

Figure 86. VCH Reflection Clamp Current Limit; VCH = 0 V, VCL = −2 V, VDUT Swept −2.0 V to +5.0 V

ADATE318 Data Sheet


0953

0-18

0

0

–120

–100

–80

–60

–40

–20

–140

–160

–18010

DRIVER CLC SETTING 3-BIT VALUE2

OFF

SET

(mV)

4 5 6 73

Figure 87. Driver Offset Error vs. Driver CLC Setting 09

530-

181

20

–5

0

5

10

15

–10

–15

–2010

COMPARATOR CLC SETTING 3-BIT VALUE2

OFF

SET

(mV)

4 5 6 73

Figure 88. Normal Window Comparator Offset Error vs. CLC Setting

0953

0-18

2

20

–5

0

5

10

15

–10

–15

–2010

DIFFERENTIAL COMPARATOR CLC SETTING 3-BIT VALUE2

OFF

SET

(mV)

4 5 6 73

Figure 89. Differential Comparator Offset error vs. CLC Setting

0953

0-20

8

60

40

0

50

30

20

10

90

100

80

70

0 5HYSTERESIS CODE

MEA

SUR

ED H

YSTE

RES

IS (m

V)

25 30 3510 15 20

RESOLUTION (0 TO 31) = ~ 3.0mV/BITRESOLUTION (10 TO 31) = ~ 4.6mV/BIT

VOL_HYSTERESISVOH_HYSTERESIS

Figure 90. Normal Window Comparator Hysteresis Transfer Function

0953

0-20

9

80

60

0

40

20

140

120

100

0 5HYSTERESIS CODE

MEA

SUR

ED H

YSTE

RES

IS (m

V)

25 30 3510 15 20

RESOLUTION (0 TO 31) = ~ 3.6mV/BITRESOLUTION (10 TO 31) = ~ 5.6mV/BIT

VOL_HYSTERESISVOH_HYSTERESIS

Figure 91. Differential Comparator Hysteresis Transfer Function

0953

0-18

3

1ns/DIV

C1

100m

V/D

IV

Figure 92. Driver Eye Diagram, 400 Mbps, PRBS31; VIH = 1 V, VIL = 0 V

Data Sheet ADATE318


0953

0-18

4

500ps/DIV

C1

100m

V/D

IV


0953

0-18

5

500ps/DIV

200m

V/D

IV

C1


0953

0-18

6

200ps/DIV

C1100m

V/D

IV


0953

0-18

7

200ps/DIV

C1

200m

V/D

IV


0953

0-18

8

200ps/DIV

C1

100m

V/D

IV


0953

0-18

9

200ps/DIV

C1

200m

V/D

IV


ADATE318 Data Sheet


0953

0-19

5

–0.2

–0.6

–0.4

–0.8

0.4

0.6

0.8

0.2

0

0 5TIME (µs)

10

VOLT

AG

E (V

)

2015

VIH TO HIGH-ZVIL TO HIGH-Z

Figure 99. Drive to/from High-Z Transition, VIH = 1 V, VIL = −1 V, 50 Ω Termination

0953

0-21

0

20

–20

–100

0

–40

–60

–80

80

100

60

40

0 5TIME (ns)

VOLT

AG

E (m

V)

15 2010

VIL TO IOLVIL TO IOHVIH TO IOLVIH TO IOHIOL TO VILIOL TO VIHIOH TO VILIOH TO VIH

Figure 100. Drive to/from Active Load Transient, VIL = VIH = 0 V, IOH = IOL = 0 V

0953

0-21

1

10

–10

–50

0

–20

–30

–40

40

50

30

20

0 5TIME (ns)

VOLT

AG

E (m

V)

15 20 25 30 35 40 45 5010

VIL TO HIZVIH TO HIZHIZ TO VILHIZ TO VIH

Figure 101. Drive to/from High-Z Transient, VIL = VIH = 0 V, 50 Ω Termination

0953

0-19

7

–0.02

0.08

0.06

0.04

0.02

–0.04

0.12

0.14

0.16

0

0.10

0 2TIME (ns)

4

VOLT

AG

E (V

)

206 8 10 12 14 16 18

CLC0CLC3CLC7

Figure 102. Driver 0.2 V Response vs. CLC Settings

0953

0-19

8

–0.1

0.4

0.3

0.2

0.1

–0.2

0.6

0.7

0.8

0

0.5

0 2TIME (µs)

4

VOLT

AG

E (V

)

206 8 10 12 14 16 18

CLC0CLC3CLC7

Figure 103. Driver 1 V Response vs. CLC Settings

0953

0-19

91.0

0.5

–0.5

1.5

2.0

0

0 2TIME (ns)

4

VOLT

AG

E (V

)

206 8 10 12 14 16 18

CLC0CLC3CLC7

Figure 104. Driver 3 V Response vs. CLC Settings

Data Sheet ADATE318


0953

0-20

0

4

3

2

1

–1

5

6

0

0 10TIME (µs)

VOLT

AG

E (V

)

6020 30 40 50

RISEFALL

Figure 105. PPMU Transient Response, FI Range A, Full -Scale Transition, Uncalibrated, CLOAD = 200 pF, RLOAD = 120 Ω

0953

0-20

1

1.0

0.5

–0.5

1.5

2.0

0

0 5TIME (µs)

VOLT

AG

E (V

)

3010 15 20 25

RISEFALL

Figure 106. PPMU Transient Response, FI Range B, Full-Scale Transition, Uncalibrated, CLOAD = 200 pF, RLOAD = 1.5 kΩ

0953

0-20

2

1.0

0.5

–0.5

1.5

2.0

0

0 10TIME (µs)

VOLT

AG

E (V

)

6020 30 40 50

RISEFALL

Figure 107. PPMU Transient Response, FI Range C, Full-Scale Transition, Uncalibrated, CLOAD = 200 pF, RLOAD = 15 kΩ

0953

0-20

3

4

3

0

5

6

2

1

0 10TIME (µs)

VOLT

AG

E (V

)

6020 30 40 50

RISEFALL

Figure 108. PPMU Transient Response, FV Range A, 0 V to 5 V, Uncalibrated, CLOAD = 200 pF

0953

0-20

4

0.3

0.1

0.2

0

0.6

0.5

0.4

0 2TIME (µs)

4

VOLT

AG

E (V

)

8 106

RISEFALL

Figure 109. PPMU Transient Response, FV Range A, 0 V to 0.5 V, Uncalibrated, CLOAD = 200 pF

0953

0-20

50.3

0.1

–0.1

0.2

0

0.6

0.7

0.5

0.4

0 5TIME (µs)

VOLT

AG

E (V

)

15 2010

RISEFALL

Figure 110. PPMU Transient Response, FV Range C, 0 V to 0.5 V, Uncalibrated, CLOAD = 200 pF

ADATE318 Data Sheet


0953

0-20

6

0.3

0.1

0.2

0

0.6

0.5

0.4

0 2 4TIME (µs)

VOLT

AGE

(V)

8 106

RISEFALL

Figure 111. PPMU Transient Response, FV Range A, 0 V to 0.5 V, Uncalibrated, CLOAD = 2000 pF

0953

0-20

7

0.3

0.1

–0.1

0.2

0

0.6

0.7

0.5

0.4

0 10TIME (µs)

VOLT

AG

E (V

)

30 4020

RISEFALL

Figure 112. PPMU Transient Response, FV Range C, 0 V to 0.5 V, Uncalibrated, CLOAD = 2000 pF

Data Sheet ADATE318


SPI INTERCONNECT DETAILS

0953

0-00

3

ADATE318(CHIP x)

SCLK

SDI

SDO

BUSY

CS

CS

n

ADATE318(CHIP 1)

SCLK

SDI

SDO

BUSY

CS

CS

1

ADATE318(CHIP 0)

SCLK

SDI

SDO

BUSY

CS

CS

0

NOTES1. x ≤ 4.

SCLK

CS[3:0]

SDI

SDO

BUSY

x

. . . . . . . . . . . .

Figure 113. Multiple SPI with Shared SDO Line

ADATE318 Data Sheet


USE OF THE SPI BUSY PIN After any valid SPI instruction is written to the ADATE318, the BUSY pin becomes asserted to indicate a busy status of the DAC update and calibration engines. The BUSY pin is an open drain type output capable of sinking a minimum of 5 mA from the VCC supply. Because it is an open drain type output, it can be wire-or’ed in common with many other similar open drain devices. In such cases, it is the user’s responsibility either to determine which device is indicating the busy state or, alter-natively, to wait until all devices on the shared line become not busy. It is recommended that the BUSY pin be tied to VCC with an external 1 kΩ pull-up.

It is not a requirement to wait for release of BUSY prior to a subsequent assertion of the CS pin. This is not the purpose of the BUSY pin. As long as the minimum number of SCLK cycles following the previous release of CS is met according to the tCSAM parameter, the CS pin can be asserted again for a subsequent SPI operation. With the one exception of recovery from a reset request (either by hardware assertion of the RST pin or a sofware setting of the internal SPI_RESET control bit), there is no scenario in normal operation of the ADATE318 in which the user must wait for release of BUSY prior to asserting the CS for another SPI operation. The only requirement on the assertion of CS is that the tCSAM parameter be defined as in Figure 4 and Table 13.

It is very important, however, that the SCLK continue to operate for as long as the BUSY pin state remains active. This minimum period of time is defined by the tBUSW parameter (see Figure 4, Figure 6, Figure 7, and Table 18). If the SCLK does not remain active for at least the time specified by the tBUSW parameter, oper-ations pending to the internal processor may not fully complete or, worse, they may complete in an incorrect fashion. In either case, a temporary malfunction of the ADATE318 may occur.

After the ADATE318 releases the BUSY pin, the SCLK may again be stopped to prevent unwanted digital noise from coupling into the analog levels during normal operation of the

pin electronics functions. In every case (with no exception for reset recovery), it is the purpose of the BUSY pin to notify the external test processor that it is again safe to stop the SCLK signal to the ADATE318. Running the SCLK for extra periods when BUSY is not active is never a problem except for the possibility of adding unwanted digital switching noise to the analog pin electronics circuitry as already noted.

While the length of the BUSY period (tBUSW) is variable depending on the particular preceding SPI instruction, it is nevertheless deterministic. The parameter tBUSW depends only on factors such as whether the previous instruction involved a write to one or more DAC addresses and, if so, then how many channels were involved and whether or not the calibration function was enabled. Table 18 describes the precise length of the tBUSW period in units of rising edge SCLK cycles for each possible SPI instruction scenario as well as recovery from a hard RST reset.

Because tBUSW is deterministic, it is therefore possible to predict in advance the minimum number of rising edge SCLK cycles required to complete any given SPI instruction. This makes it possible to operate the ADATE318 without a need to monitor the state of the BUSY pin. For applications in which it is neither possible nor desireable to monitor the pin, it is acceptable to use the information in Table 18 to guarantee that the minimum number of cycles is provided in lieu of monitoring BUSY following release of CS or reset. All DAC addresses have been assigned to the contiguous address block from 0x00 through 0x0F; therefore, it is possible to decode this information within the external test processor to provide a software indication that extra SCLK cycles may be required according to the scenarios listed in Table 18. All other operations not involving these addresses require only the standard number of clock cycles determined by tCSAM. As stated above, however, it is extremely important to honor the minimum number of required rising edge SCLK cycles as defined by tBUSW following the release of CS for each of the SPI instruction scenarios listed in Table 18 to ensure proper operation of the ADATE318.

Table 18. BUSY Minimum SCLK Cycle Requirements SPI Instruction Type Calibration Engine1 Maximum tBUSW (SCLK Cycles) Following the Release of the Asynchronous Reset Pin (Hardware Reset) X 64 Following Assertion of the SPI_RESET Control Bit (Software Reset) X 64 No Operation (NOP) Instruction X 3 Read Request to Any Valid ADATE318 Address and/or Channel (0x00 – 0x7F) X 3

Single/Double Channel Write Request to Any Valid ADATE318 Address ≥ 0x10 X 3

Single Channel Write Request to Any DAC (ADDR 0x01 – ADDR 0x0E) Disabled 10 Double Channel Write Request to Any DAC (ADDR 0x01 – ADDR 0x0E) Disabled 16 Single Channel Write Request to Any DAC (ADDR 0x01 – ADDR 0x0E) Enabled 20 Double Channel Write Request to Any DAC (ADDR 0x01 – ADDR 0x0E) Enabled 26

1 X = don’t care.

Data Sheet ADATE318


RESET SEQUENCE AND THE RST PIN The internal state of the ADATE318 is indeterminate following power-up. For this reason, it is necessary to perform a complete reset sequence once the power supplies have stabilized. Further, the RST pin must be held in the asserted state before and during the power-up sequence and released only after all power supplies are known to be stable.

The ADATE318 has an active low pin (RST) that asynchron-ously starts a reset sequence. A soft reset sequence can also be initiated under SPI software control by writing to the SPI_RESET bit in the SPI Control Register (SPI 0x12[0] (see Figure 13)). In the case of a soft reset, the sequence begins on the first rising edge of SCLK following the release of CS, subject to the normal setup and hold times. Certain actions take place immediately upon initiation of the reset request, whereas other actions require SCLK.

The following asynchronous actions take place as soon as a reset request is detected, whether or not SCLK is active:

Assert BUSY pin Force all control registers to the default reset state as

defined by control register definitions Clear all calibration registers to the default reset state as

defined by calibration register definitions Override all DAC output voltages and force analog levels to

VDUTGND

Disable DCLs and PPMUs; open system PMU switches Soft connect the DUT0 and DUT1 pins to VDUTGND (see

Figure 114)

The part remains in this static reset state indefinitely until the clocked portion of the sequence begins with either the first rising edge of SCLK following the release of RST (asynch-ronous reset) or the second rising edge of SCLK following the release of CS (soft reset). No matter how the reset sequence is initiated, the clocked portion of the reset sequence requires 64 SCLK cycles to run to completion, and the BUSY pin remains asserted until these clock cycles have been received. The following actions take place during the clocked portion of the reset sequence:

Complete internal SPI controller initialization Write the appropriate values to specific DAC X2 registers

(see Table 19) Enable the thermal alarm with a 100C threshold; disable

PPMU and the overvoltage detect (OVD) alarms

The 64th rising edge of SCLK releases BUSY and starts a self-timed DAC deglitch period of approximately 3 μs. DAC voltages begin to change once the deglitch circuits have timed out, and they then require an additional 10 μs to settle to their final values. Thus, a full reset sequence requires approximately 15 μs, comprising 1.28 μs (64 cycles 20 ns) for the reset state machine, 3 μs for DAC deglitch, and another 10 μs for settling.

0953

0-01

0

DRIVER

DUTGND

DUTx

COMPARATORS

50Ω

10kΩ

CLAMPS TO PPMU

LOAD

DUT PULLDOWNx

ADDR 0x19[7]

DUT PULL-DOWN SWITCH DEFAULTS TO ACLOSED STATE IMMEDIATELY FOLLOWINGAN ASSERT OF RST (FOR HARD RESET)OR AT THE FIRST RISING EDGE OF SCLKFOLLOWING THE SPI CS (FOR SOFT RESET).SEE DCL CONTROL REGISTER 0x19[7].

Figure 114. DUTx to VDUTGND Soft Connect Detail

ADATE318 Data Sheet


SPI REGISTER DEFINITIONS AND MEMORY MAP

0953

0-01

1

D1 D0D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2C1 C0 A6 A5 A4 A3 A2 A1 A0 R/W

24 2510 11 12 13 14 15 16 17 18 19 20 21 22 230

SPI WORD INDEX

1 2 3 4 5 6 7 8 9SPI CLOCK INDEX

CH[1:0]CHANNEL SELECT 00 = NOP 01 = READ/WRITE CHANNEL 0 10 = READ/WRITE CHANNEL 1

11 = READ NOP11 = WRITE CHANNEL 0 AND 1

ADDR[6:0]ADDRESS FIELD

DATA[15:0]DATA FIELD

R/WREAD/WRITE SELECT

0 = READ:

1 = WRITE:

THE CONTENTS OF REGISTER SPECIFIED BY ADDR[6:0]AND CH[1:0] ARE SHIFTED OUT ON THE SDO PINDURING THE NEXT SPI INSTRUCTION CYCLE.DATA[15:0] IS WRITTEN TO THE REGISTERSPECIFIED BY ADDR[6:0] AND CH[1:0].

Figure 115. SPI Word Definition

Table 19. SPI Register Memory Map CH[1:0]1, 2 ADDR[6:0] R/W1 DATA[15:0]1, 3 Register Description Reset Value1

XX 0x00 X XXXX No operation (NOP) XXXX CC 0x01 R/W DDDD VIH DAC level (reset value = 0.0 V) 0x4000 CC 0x02 R/W DDDD VIT/VCOM DAC level (reset value = 0.0 V) 0x4000 CC 0x03 R/W DDDD VIL DAC level (reset value = 0.0 V) 0x4000 CC 0x04 R/W DDDD VOH DAC level (reset value = +0.5 V)) 0x4CCC CC 0x05 R/W DDDD VOL DAC level (reset value = −0.5 V) 0x3333 CC 0x06 R/W DDDD VCH DAC level (reset value = +7.5 V) 0xFFFF CC 0x07 R/W DDDD VCL DAC level (reset value = −2.5 V) 0x0000 CC 0x08 R/W DDDD VIOH DAC level (reset value = 50 μA) 0x4040 CC 0x09 R/W DDDD VIOL DAC level (reset value = 50 μA) 0x4040 CC 0x0A R/W DDDD PPMU DAC level (reset value = 0.0 V) 0x4000 01 0x0B R/W DDDD VHH DAC level (reset value = 0.0 V) 0x2666 01 0x0C R/W DDDD OVDH DAC level (reset value = +7.5 V) 0xFFFF 01 0x0D R/W DDDD OVDL DAC level (reset value = −2.5 V) 0x0000 01 0x0E R/W DDDD Spare DAC level (reset value = 0.0 V) 0x4000 XX 0x0F X XXXX Reserved XXXX XX 0x10 X XXXX No operation (NOP) XXXX CC 0x11 R/W DDDD DAC control register 0x0000 01 0x12 R/W DDDD SPI control register 0x0000 XX 0x13 to 0x17 X XXXX Reserved XXXX 01 0x18 R/W DDDD VHH control register 0x0000 CC 0x19 R/W DDDD DCL control register 0x0080 CC 0x1A R/W DDDD PPMU control register 0x0000 CC 0x1B R/W DDDD PPMU MEAS control register 0x0000 CC 0x1C R/W DDDD CMP control register 0x07FE CC 0x1D R/W DDDD ALARM mask register 0x0045 CC 0x1E R DDDD ALARM state register 0x0000 CC 0x1F R/W DDDD CLC control register 0x0000 XX 0x20 X XXXX No operation (NOP) XXXX CC 0x21 R/W DDDD VIH (driver) m-coefficient 0xFFFF CC 0x22 R/W DDDD VIT (driver) m-coefficient 0xFFFF CC 0x23 R/W DDDD VIL (driver) m-coefficient 0xFFFF CC 0x24 R/W DDDD VOH (normal window comparator) m-coefficient 0xFFFF

Data Sheet ADATE318


CH[1:0]1, 2 ADDR[6:0] R/W1 DATA[15:0]1, 3 Register Description Reset Value1

CC 0x25 R/W DDDD VOL (normal window comparator) m-coefficient 0xFFFF CC 0x26 R/W DDDD VCH (reflection clamp) m-coefficient 0xFFFF CC 0x27 R/W DDDD VCL (reflection clamp) m-coefficient 0xFFFF CC 0x28 R/W DDDD VIOH (active load) m-coefficient 0xFFFF CC 0x29 R/W DDDD VIOL (active load) m-coefficient 0xFFFF CC 0x2A R/W DDDD PPMU (PPMU force-voltage) m-coefficient 0xFFFF 01 0x2B R/W DDDD VHH (HVOUT) m-coefficient 0xFFFF 01 0x2C R/W DDDD OVDH (overvoltage) m-coefficient 0xFFFF 01 0x2D R/W DDDD OVDL (overvoltage) m-coefficient 0xFFFF 01 0x2E R/W DDDD Spare DAC m-coefficient 0xFFFF XX 0x2F X XXXX Reserved XXXX XX 0x30 X XXXX No operation (NOP) XXXX CC 0x31 R/W DDDD VIH (driver) c-coefficient 0x8000 CC 0x32 R/W DDDD VIT (driver) c-coefficient 0x8000 CC 0x33 R/W DDDD VIL (driver) c-coefficient 0x8000 CC 0x34 R/W DDDD VOH (normal window comparator) c-coefficient 0x8000 CC 0x35 R/W DDDD VOL (normal window comparator) c-coefficient 0x8000 CC 0x36 R/W DDDD VCH (reflection clamp) c-coefficient 0x8000 CC 0x37 R/W DDDD VCL (reflection clamp) c-coefficient 0x8000 CC 0x38 R/W DDDD VIOH (active load) c-coefficient 0x8000 CC 0x39 R/W DDDD VIOL (active load) c-coefficient 0x8000 CC 0x3A R/W DDDD PPMU (PPMU force voltage) c-coefficient 0x8000 01 0x3B R/W DDDD VHH (HVOUT) c-coefficient 0x8000 01 0x3C R/W DDDD OVDH (overvoltage) c-coefficient 0x8000 01 0x3D R/W DDDD OVDL (overvoltage) c-coefficient 0x8000 01 0x3E R/W DDDD Spare DAC c-coefficient 0x8000 XX 0x3F X XXXX Reserved XXXX XX 0x40 X XXXX No operation (NOP) XXXX 01 0x41 R/W DDDD VIH (HVOUT) m-coefficient 0xFFFF CC 0x42 R/W DDDD VCOM (active load) m-coefficient 0xFFFF 01 0x43 R/W DDDD VIL (HVOUT) m-coefficient 0xFFFF 01 0x44 R/W DDDD VOH (differential comparator) m-coefficient 0xFFFF CC 0x45 R/W DDDD VOH (PPMU measure voltage) m-coefficient 0xFFFF CC 0x46 R/W DDDD VOH (PPMU measure current, Range A) m-coefficient 0xFFFF CC 0x47 R/W DDDD VOH (PPMU measure current Range B) m-coefficient 0xFFFF CC 0x48 R/W DDDD VOH (PPMU measure current, Range C) m-coefficient 0xFFFF CC 0x49 R/W DDDD VOH (PPMU measure current, Range D) m-coefficient 0xFFFF CC 0x4A R/W DDDD VOH (PPMU measure current, Range E) m-coefficient 0xFFFF 01 0x4B R/W DDDD VOL (differential comparator) m-coefficient 0xFFFF CC 0x4C R/W DDDD VOL (PPMU measure voltage) m-coefficient 0xFFFF CC 0x4D R/W DDDD VOL (PPMU measure current, Range A) m-coefficient 0xFFFF CC 0x4E R/W DDDD VOL (PPMU measure current, Range B) m-coefficient 0xFFFF CC 0x4F R/W DDDD VOL (PPMU measure current, Range C) m-coefficient 0xFFFF CC 0x50 R/W DDDD VOL (PPMU measure current, Range D) m-coefficient 0xFFFF CC 0x51 R/W DDDD VOL (PPMU measure current, Range E) m-coefficient 0xFFFF CC 0x52 R/W DDDD VCH (PPMU) m-coefficient 0xFFFF CC 0x53 R/W DDDD VCL (PPMU) m-coefficient 0xFFFF CC 0x54 R/W DDDD PPMU force current, Range A m-coefficient 0xFFFF CC 0x55 R/W DDDD PPMU force current, Range B m-coefficient 0xFFFF CC 0x56 R/W DDDD PPMU force current, Range C m-coefficient 0xFFFF CC 0x57 R/W DDDD PPMU force current Range D m-coefficient 0xFFFF CC 0x58 R/W DDDD PPMU force current, Range E m-coefficient 0xFFFF 01 0x59 R/W DDDD VIH (HVOUT) c-coefficient 0x8000 CC 0x5A R/W DDDD VCOM (active load) c-coefficient 0x8000 01 0x5B R/W DDDD VIL (HVOUT) c-coefficient 0x8000 01 0x5C R/W DDDD VOH (differential comparator) c-coefficient 0x8000 CC 0x5D R/W DDDD VOH (PPMU measure voltage) c-coefficient 0x8000

ADATE318 Data Sheet


CH[1:0]1, 2 ADDR[6:0] R/W1 DATA[15:0]1, 3 Register Description Reset Value1

CC 0x5E R/W DDDD VOH (PPMU measure current) c-coefficient 0x8000 XX 0x5F to 0x62 X XXXX Reserved XXXX 01 0x63 R/W DDDD VOL (differential comparator) c-coefficient 0x8000 CC 0x64 R/W DDDD VOL (PPMU measure voltage) c-coefficient 0x8000 CC 0x65 R/W DDDD VOL (PPMU measure current) c-coefficient 0x8000 XX 0x66 to 0x69 X XXXX Reserved XXXX CC 0x6A R/W DDDD VCH (PPMU) c-coefficient 0x8000 CC 0x6B R/W DDDD VCL (PPMU) c-coefficient 0x8000 CC 0x6C R/W DDDD PPMU force current c-coefficient 0x8000 XX 0x6D to 0x70 X XXXX Reserved XXXX

1 X = don’t care. 2 CC corresponds to the channel address bits and indicates that there is dedicated register space for each channel. 3 DDDD stands for data.

Data Sheet ADATE318


CONTROL REGISTER DETAILS Reserved bits in any register are undefined. In some cases, a physical (but unused) memory bit may be present, in other cases not. Write operations have no effect. Read operations result in meaningless but deterministic data.

Any SPI read operation from any reserved bit or register results in an unknown but deterministic readback value.

Any SPI write operation to a control bit or control register defined only on Channel 0 must be addressed to at least Channel 0. Any such write that is addressed only to Channel 1 is ignored. Further, any such write that is addressed to both Channel 0 and Channel 1 (as a multichannel write) proceeds as if the write were addressed only to Channel 0. The data addressed to the undefined Channel 1 control bit or control register is ignored.

0953

0-01

2

RESERVED[15:3]RESERVED

DAC_LOAD[2]DAC LOAD SOFT PIN, SELF-RESETTING, CHANNEL 0/CHANNEL 1[0] = DEFAULT STATE OF THE DAC_LOAD SOFT PIN 1 = BEGIN DAC LOAD OPERATION (PULSE, SELF-CLEAR TO ZERO)A WRITE TO THIS BIT PARALLEL UPDATES ALL DACs OF CHANNEL xWITH PREVIOUSLY BUFFERED DATA ASSUMING THAT THEDAC_LOAD_MODE CONTROL BIT OF CHANNEL x IS NOT SET TOWRITE DAC IMMEDIATE MODE. THIS BIT AUTOMATICALLY SELF-CLEARS.

D1 D0D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2

24 2510 11 12 13 14 15 16 17 18 19 20 21 22 23

DATA-WORD INDEX

SPI CLOCK INDEX

DAC_CAL_ENABLE[0]DAC CALIBRATION ENGINE ENABLE, CHANNEL 0 ONLY[0] = CALIBRATION ENGINE IS DISABLED 1 = CALIBRATION ENGINE IS ENABLEDWHEN DAC CALIBRATION IS ENABLED, EACH WRITE TO A VALID DACADDRESS RESULTS IN A SUBSEQUENT MULTIPLY AND ACCUMULATE(MAC) OPERATION TO THE DATA FOR THE RESPECTIVE DAC USINGCALIBRATION DATA CONTAINED IN THE APPROPRIATE m- AND c-COEFFICIENT REGISTERS. WHEN THE CALIBRATION ENGINE ISDISABLED, DATA WRITTEN TO A VALID DAC ADDRESS IS NOTMODIFIED BY THE ON-CHIP CALIBRATION COEFFICIENTS.

DAC_LOAD_MODE[1]DAC LOAD MODE, CHANNEL 0/CHANNEL 1[0] = WRITE DAC IMMEDIATE MODE. 1 = WRITE DAC DEFERRED MODE.IN WRITE DAC IMMEDIATE MODE, EACH RESPECTIVE DAC IS UPDATEDIMMEDIATELY SUBSEQUENT TO A VALID SPI WRITE INSTRUCTION TOTHAT DAC ADDRESS. IN WRITE DAC DEFERRED MODE, EACH VALIDSPI WRITE TO A DAC ADDRESS IS BUFFERED, AND DACs ARE ONLYUPDATED FOLLOWING ASSERTION OF THE DAC_LOAD SOFT PIN.IN THIS MODE, ALL ANALOG DAC DATA FOR EITHER OR BOTHCHANNELS CAN BE UPDATED IN PARALLEL.

Figure 116. DAC Control Register (ADDR = 0x11)

ADATE318 Data Sheet


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SPI_RESET[0]SPI SOFTWARE RESET, CHANNEL 0 ONLY[0] = DEFAULT SETTING, NO ACTION IS TAKEN UNTIL A 1 IS WRITTEN. 1 = RESET (PULSE, SELF-CLEAR TO ZERO).FOLLOWING A WRITE TO SET THIS BIT, THE ADATE318 BEGINSA FULL RESET SEQUENCE JUST AS IF THE RST PIN HAD BEENASSERTED ASYNCHRONOUSLY. FOLLOWING RESET THIS BITSELF-CLEARS TO THE DEFAULT 0 CONDITION.


24 2510 11 12 13 14 15 16 17 18 19 20 21 22 23

DATA-WORD INDEX

SPI CLOCK INDEX

SPI_SDO_HIZ[1]SPI SERIAL DATA OUTPUT PIN, HIGH-Z CONTROL, CHANNEL 0 ONLY[0] = SDO PIN IS ALWAYS ACTIVE, INDEPENDENT OF THE CS INPUT. 1 = SDO PIN IS ACTIVE ONLY WHEN CS IS ACTIVE, OTHERWISE HIGH-Z.

Figure 117. SPI Control Register (ADDR = 0x12)

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VHH_ENABLE[0]VHH (HVOUT) ENABLE, CHANNEL 0 ONLY[0] = HVOUT PIN IS DISABLED. 1 = HVOUT PIN IS ENABLED.WHEN VHH MODE IS ENABLED, THE HVOUT PIN IS SET TO THE LEVELSACCORDING TO THE VHH AND VIH/VIL DRIVER TRUTH TABLE (TABLE 25).WHEN VHH MODE IS DISABLED, THE IMPEDANCE OF THE HVOUT PINIS APPROXIMATELY 50Ω TO VDUTGND.


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DATA-WORD INDEX

SPI CLOCK INDEX

Figure 118. VHH Control Register (ADDR = 0x18) Active Truth Table

Data Sheet ADATE318


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DRIVE_VT_HIZ_x[6]DRIVER VT/HiZ MODE SELECT, CHANNEL 0/CHANNEL 1[0] = DRIVER GOES TO HIGH-Z STATE WHEN RCVx = 1. 1 = DRIVER GOES TO VIT STATE WHEN RCVx = 1.WHEN DRV_VT_HIZ IS ASSERTED, THE DRIVER ON CHANNEL x ASSUMESTHE VIT LEVEL ON ASSERTION OF THE RCVx HIGH SPEED INPUT INACCORDANCE WITH THE DRIVER TRUTH TABLE. THIS CONTROL BIT ISSUBORDINATE TO THE DCL_ENABLE AND FORCE_DRIVE CONTROL BITS.

LOAD_ENABLE_x[5]ACTIVE LOAD ENABLE, CHANNEL 0/CHANNEL 1[0] = ACTIVE LOAD IS DISABLED AND POWERED DOWN. 1 = ACTIVE LOAD IS ENABLED.WHEN LOAD_ENABLE IS ASSERTED, THE ACTIVE LOAD ON CHANNEL x IS ENABLEDAND CONNECTS TO THE DUTx PIN ON ASSERTION OF THE RCVn HIGH SPEED INPUTIN ACCORDANCE WITH THE ACTIVE LOAD TRUTH TABLE. THIS CONTROL BIT ISSUBORDINATE TO THE DCL_ENABLE AND FORCE_LOAD CONTROL BITS BUT TAKESPRECEDENCE OVER THE RCVn HIGH SPEED INPUTS.

FORCE_DRIVE_STATE_x[4:3]DRIVER STATE WHEN FORCE_DRIVE, CHANNEL 0/CHANNEL 1[00] = FORCE DRIVE VIL STATE. 01 = FORCE DRIVE VIH STATE. 10 = FORCE DRIVE HIGH-Z STATE. 11 = FORCE DRIVE VIT STATE.WHEN THE FORCE_DRIVE CONTROL BIT IS ACTIVE, THE DRIVER ON CHANNEL xASSUMES THE INDICATED STATE IN ACCORDANCE WITH THE DRIVER TRUTH TABLE.

FORCE_LOAD_x[2]FORCE ACTIVE LOAD TO ACTIVE ON STATE, CHANNEL 0/CHANNEL 1[0] = ACTIVE LOAD RESPONDS TO RCVx. 1 = FORCE ACTIVE ON STATE.WHEN FORCE_LOAD IS ASSERTED, THE ACTIVE LOAD ON CHANNEL x ASSUMES THE ACTIVE ONSTATE AND IS CONNECTED TO THE DUTx PIN IN ACCORDANCE WITH THE ACTIVE LOAD TRUTHTABLE. THIS CONTROL BIT IS SUBORDINATE TO THE DCL_ENABLE CONTROL BIT BUT TAKESPRECEDENCE OVER BOTH THE LOAD_ENABLE AND DRV_VT_HIZ CONTROL BITS, AS WELL ASTHE RCVx INPUTS. THIS BIT DOES NOT FORCE SELECTION OF VCOM CALIBRATION CONSTANTS.

FORCE_DRIVE_x[1]FORCE DRIVER TO FORCE_STATE, CHANNEL 0/CHANNEL 1[0] = DRIVER RESPONDS TO DATx AND RCVx. 1 = FORCE DRIVER STATE TO FORCE_STATE.WHEN FORCE_DRIVE IS ASSERTED, THE DRIVER ON CHANNEL x ASSUMES THE STATE INDICATEDBY FORCE_STATE IN ACCORDANCE WITH THE DRIVER TRUTH TABLE. THIS CONTROL BIT IS SUBORDINATETO THE DCL_ENABLE CONTROL BIT BUT TAKES PRECEDENCE OVER DRV_VT_HIZ, AS WELL AS THEDATx AND RCVx INPUTS. THIS BIT DOES NOT FORCE SELECTION OF VCH AND VCL CALIBRATIONCONSTANTS NOR DOES IT FORCE SELECTION OF VIT CALIBRATION CONSTANTS.

DCL_ENABLE_x[0]ENABLE DCL ON CHANNEL 0/CHANNEL 1[0] = DCL IS DISABLED (LOW LEAKAGE MODE). 1 = DCL IS ENABLED.WHEN DCL_ENABLE IS NOT ASSERTED, THE DRIVER, COMPARATOR, AND ACTIVE LOAD ONCHANNEL x ASSUME THE LOW LEAKAGE STATE IN ACCORDANCE WITH DRIVER ANDACTIVE LOAD TRUTH TABLES. THIS CONTROL BIT TAKES PRECEDENCE OVER ALL OTHER CONTROLBITS IN THE DCL CONTROL REGISTER EXCEPT FOR DUT_PULLDOWN.


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DATA-WORD INDEX

SPI CLOCK INDEX

DUT_PULLDOWN_x[7]DUTx PIN 10K SOFT PULL-DOWN, CHANNEL 0/CHANNEL 1 0 = PULL-DOWN DISCONNECTED.[1]WHEN DUT_PULLDOWN IS ASSERTED, THE DUTx PIN ON CHANNEL xHAS A 10kΩ PULL-DOWN TO DUTGND. THIS CONTROL BIT ISASYNCHRONOUSLY SET AT THE BEGINNING OF ANY RESET OPERATION,AND IT REMAINS SET UNTIL CLEARED BY THE USER. THIS CONTROLBIT DOES NOT DEPEND ON OTHER CONTROL BITS IN THIS REGISTER.

= DUTx PIN HAS 10kΩ PULL-DOWN TO DUTGND.

Figure 119. DCL Control Register (ADDR = 0x19)

ADATE318 Data Sheet


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PPMU_POWER_x[15]PPMU POWER, CHANNEL 0/CHANNEL 1[0] = PPMU POWER OFF. 1 = PPMU POWER ON.WHEN PPMU_POWER_x[15] = 1, THE NWCAND DMC HYSTERESIS IS FORCED TO AMAXIMUM, BUT THE HYSTERESISREGISTER VALUES ARE LEFT UNCHANGED.

PMU_S_ENABLE_x[11]PMU SENSE INPUT ENABLE, CHANNEL 0/CHANNEL 1[0] = PMU SENSE INPUT SWITCH OPEN. 1 = PMU SENSE INPUT SWITCH CLOSED.

PPMU_CLAMP_ENABLE_x[9]PPMU CLAMP ENABLE, CHANNEL 0/CHANNEL 1[0] = PPMU CLAMPS DISABLED. 1 = PPMU CLAMPS ENABLED.

PPMU_MEAS_VI_x[5]PPMU MEASURE V OR MEASURE I, CHANNEL 0/CHANNEL 1[0] = PPMU MEASURE V MODE. 1 = PPMU MEASURE I MODE.

PPMU_RANGE_x[3:1]PPMU RANGE, CHANNEL 0/CHANNEL 1[0XX] = PPMU RANGE E (2µA). 100 = PPMU RANGE D (10µA). 101 = PPMU RANGE C (100µA). 110 = PPMU RANGE B (1mA). 111 = PPMU RANGE A (40mA).

PPMU_FORCE_VI_x[4]PPMU FORCE V OR FORCE I, CHANNEL 0/CHANNEL 1[0] = PPMU FORCE V MODE. 1 = PPMU FORCE I MODE.

PPMU_ENABLE_x[0]PPMU ENABLE, CHANNEL 0/CHANNEL 1[0] = PPMU FULL POWER STANDBY. 1 = PPMU ACTIVE.

PPMU_SENSE_PATH_x[8]PPMU SENSE PATH, CHANNEL 0/CHANNEL 1[0] = PPMU INTERNAL SENSE PATH. 1 = PPMU EXTERNAL SENSE PATH.

PPMU_INPUT_SEL_x[7:6]PPMU INPUT SELECT, CHANNEL 0/CHANNEL 1[00] = PPMU INPUT FROM DUTGND. 01 = PPMU INPUT FROM DUTGND + 2.5V. 1X


RESERVED


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DATA-WORD INDEX

SPI CLOCK INDEX

= PPMU INPUT FROM DACPPMU LEVEL.

Figure 120. PPMU Control Register (ADDR = 0x1A)

Data Sheet ADATE318


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PPMU_MEAS_SEL_x[2:1]PPMU ANALOG MEASURE OUT PIN SELECT, CHANNEL 0/CHANNEL 1[X0] = PPMU CHANNEL x TO PPMU_MEASx OUTPUT PIN. X1 = CHANNEL 0: TEMPERATURE SENSOR OUTPUT (THERM). CHANNEL 1: TEMPERATURE SENSOR GND REFERENCE.

PPMU_MEAS_ENABLE_x[0]PPMU ANALOG MEASURE OUT PIN ENABLE, CHANNEL 0/CHANNEL 1[0] = PPMU MEASURE OUT PIN ON CHANNEL x IS DISABLED, HIGH-Z. 1 = PPMU MEASURE OUT PIN ON CHANNEL x IS ENABLED.


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DATA-WORD INDEX

SPI CLOCK INDEX

Figure 121. PPMU MEAS Control Register (ADDR = 0x1B)

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NWC_HYST_x[10:6]NORMAL WINDOW COMPARATOR HYSTERESIS VALUE, CHANNEL 0/CHANNEL 1 0x00 = DISABLE HYSTERESIS. 0x01 = ENABLE MINIMUM HYSTERESIS.[0x1F]WHEN SET TO 0x00, THE NORMAL WINDOW COMPARATOR ON CHANNEL xHAS NO HYSTERESIS ADDED TO THE INPUT STAGE. WHEN SET TO A VALUEOTHER THAN 0x00, HYSTERESIS IS ADDED AND THE AMOUNT IS CONTROLLEDBY THE VALUE IN THIS REGISTER.WHEN ADDR 0x1A PPMU _POWER_x[15] = 1, THE NWC HYSTERESIS IS FORCED TO AMAXIMUM, BUT THE HYSTERESIS REGISTER VALUE IS LEFT UNCHANGED.

DMC_HYST[5:1]DIFFERENTIAL COMPARATOR HYSTERESIS VALUE, CHANNEL 0 ONLY 0x00 = DISABLE HYSTERESIS. 0x01 = ENABLE MINIMUM HYSTERESIS.[0x1F]WHEN SET TO 0x00, THE DIFFERENTIAL COMPARATOR ON CHANNEL 0HAS NO HYSTERESIS ADDED TO THE INPUT STAGE. WHEN SET TO A VALUEOTHER THAN 0x00, HYSTERESIS IS ADDED AND THE AMOUNT IS CONTROLLEDBY THE VALUE IN THIS REGISTER.WHEN ADDR 0x1A PPMU _POWER_x[15] = 1, THE DMC HYSTERESIS IS FORCED TO AMAXIMUM, BUT THE HYSTERESIS REGISTER VALUE IS LEFT UNCHANGED.

DMC_ENABLE[0]DIFFERENTIAL MODE COMPARATOR ENABLE, CHANNEL 0 ONLY[0] = DISABLE DIFFERENTIAL MODE COMPARATOR. 1 = ENABLE DIFFERENTIAL MODE COMPARATOR.WHEN DMC_ENABLE IS ASSERTED, THE NORMAL WINDOW COMPARATORON CHANNEL 0 IS DISABLED, THE DIFFERENTIAL MODE COMPARATOR ONCHANNEL 0 IS ENABLED, AND ITS OUTPUTS GOES TO THE CMPH0 AND CMPL0HIGH SPEED OUTPUT PINS. THE OPERATION OF THE NORMAL WINDOWCOMPARATOR ON CHANNEL 1 IS NOT AFFECTED. THIS CONTROL BIT EXISTSAT ADDR 0x1C CHANNEL 0 ONLY.


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DATA-WORD INDEX

SPI CLOCK INDEX

= ENABLE MAXIMUM HYSTERESIS.

= ENABLE MAXIMUM HYSTERESIS.

Figure 122. CMP Control Register (ADDR = 0x1C)

ADATE318 Data Sheet


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THERM_ALARM_MASK[3]THERMAL ALARM MASK BIT, CHANNEL 0 ONLY [0] = THERMAL ALARM ENABLED. 1WHEN THE THERMAL ALARM IS ENABLED, A TEMPERATURE SENSOR READINGABOVE THE THRESHOLD SPECIFIED BY THERM_ALARM_THRESHASSERTS AND LATCHES THE ALARM OPEN DRAIN OUTPUT PIN.

PPMU_ALARM_MASK_x[2]PPMU CLAMP ALARM MASK, CHANNEL 0/CHANNEL 1 0 [1] = PPMU CLAMP ALARM DISABLED.WHEN THE PPMU CLAMP IS ENABLED, A CLAMP CONDITION ON CHANNEL xPPMU CLAMPS ASSERTS AND LATCHES THE ALARM OPEN DRAIN OUTPUTPIN. THE PPMU CLAMP LEVELS ARE DEFINED BY THE VCL AND VCH DACREGISTERS.

OVD_ALARM_MASK_n[0]OVERVOLTAGE DETECTOR ALARM MASK, CHANNEL 0/CHANNEL 1 0 = OVERVOLTAGE ALARM ENABLED. [1]WHEN THE OVD ALARM IS ENABLED, AN OVERVOLTAGE FAULT CONDITIONON DUTx ASSERTS AND LATCHES THE ALARM OPEN DRAIN OUTPUT PIN.THE OVERVOLTAGE THRESHOLDS ARE DEFINED BY THE OVDH ANDOVDL DAC REGISITERS.

RESERVED[1]RESERVED


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DATA-WORD INDEX

SPI CLOCK INDEX

THERM_ALARM_THRESH[6:4]THERMAL ALARM THRESHOLD, CHANNEL 0 ONLY 000 = 0°C (FOR TEST USE ONLY) 001 = 25°C 010 = 50°C 011 = 75°C[100] 101 = 125°C 110 = 150°C 111 = 175°C

= 100°C

= OVERVOLTAGE ALARM DISABLED.

= PPMU CLAMP ALARM ENABLED.

= THERMAL ALARM DISABLED.

Figure 123. Alarm Mask Register (ADDR = 0x1D)

Data Sheet ADATE318


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PPMU_ALARM_FLAG_x[2]PPMU CLAMP ALARM FLAG, CHANNEL 0/CHANNEL 1 [0] = PPMU CLAMP CONDITION NOT DETECTED. 1 = PPMU CLAMP CONDITION DETECTED.WHEN THE PPMU_ALARM_FLAG BIT IS SET, A PPMU CLAMP CONDITION WASDETECTED ON CHANNEL x ACCORDING TO THE THRESHOLDS SET IN THEVCH AND VCL CLAMP REGISTERS. THIS FLAG IS SUBORDINATE TO THEPPMU_ALARM_MASK_x CONTROL BIT, AND IT AUTOMATICALLY RESETSAFTER ANY READ FROM THE ALARM STATE REGISTER.

OVDH_ALARM_FLAG_x[1]OVER VOLTAGE ALARM FLAG, CHANNEL 0/CHANNEL 1 [0] = OVER VOLTAGE FAULT NOT DETECTED. 1 = OVER VOLTAGE FAULT DETECTED.WHEN OVDH_ALARM_FLAG IS SET, AN OVER VOLTAGE FAULT CONDITIONWAS DETECTED ON CHANNEL x DUTx PIN ACCORDING TO THE THRESHOLD SETIN THE OVDH DAC REGISTER. THIS FLAG IS SUBORDINATE TO THEOVD_ALARM_MASK_x CONTROL BIT, AND IT IS AUTOMATICALLY RESETAFTER ANY READ FROM THE ALARM STATE REGISTER.

OVDL_ALARM_FLAG_x[0]UNDER VOLTAGE ALARM FLAG, CHANNEL 0/CHANNEL 1 [0] = UNDER VOLTAGE FAULT NOT DETECTED. 1 = UNDER VOLTAGE FAULT DETECTED.WHEN OVDL_ALARM_FLAG IS SET, AN UNDER VOLTAGE FAULT CONDITIONWAS DETECTED ON CHANNEL x DUTx PIN ACCORDING TO THE THRESHOLD SETIN THE OVDL DAC REGISTER. THIS FLAG IS SUBORDINATE TO THEOVD_ALARM_MASK_x CONTROL BIT, AND IT IS AUTOMATICALLY RESETAFTER ANY READ FROM THE ALARM STATE REGISTER.


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DATA-WORD INDEX

SPI CLOCK INDEX

THERM_ALARM_FLAG[3]THERMAL ALARM FLAG, CHANNEL 0 ONLY [0] = THERMAL FAULT NOT DETECTED. 1 = THERMAL FAULT DETECTED.WHEN THE THERM_ALARM_FLAG BIT IS SET, A FAULT WAS DETECTEDON THE DIE ACCORDING TO THE THERMAL THRESHOLD SET IN THETHERM_ALARM_THRESH REGISTER. THIS FLAG IS SUBORDINATE TO THETHERM_ALARM_MASK CONTROL BIT, AND IT IS AUTOMATICALLYRESET AFTER ANY READ FROM THE ALARM STATE REGISTER.

Figure 124. Alarm State Register (ADDR = 0x1E) (Read Only)

ADATE318 Data Sheet


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DATA-WORD INDEX

SPI CLOCK INDEX

DRV_CLC_x[15:13]DRIVER CABLE LOSS COMPENSATION,CHANNEL 0/CHANNEL 1 [000] = DISABLE DRIVER CLC. 001 = ENABLE DRIVER MINIMUM CLC. 111 = ENABLE DRIVER MAXIMUM CLC.WHEN SET TO 0x00, THE DRIVER ON CHANNEL x HASZERO CABLE LOSS COMPENSATION (CLC) ADDEDTO ITS OUTPUT CHARACTERISTIC. WHEN SET TO AVALUE OTHER THAN 0x00, CABLE LOSS COMPENSATIONPRE-EMPHASIS IS ADDED AND THE PERCENTAGEIS CONTROLLED BY THE REGISTER VALUE.

NWC_CLC_x[10:8]NORMAL WINDOW COMPARATOR CABLE LOSS COMPENSATION,CHANNEL 0/CHANNEL 1 [000] = DISABLE NWC CLC. 001 = ENABLE NWC MINIMUM CLC. 111 = ENABLE NWC MAXIMUM CLC.WHEN SET TO 0x00, THE NORMAL WINDOW COMPARATOR (NWC) ON CHANNEL xHAS NO CABLE LOSS COMPENSATION (CLC) ADDED TO THE INPUT ADDED TOTHE INPUT WAVEFORM CHARACTERISTIC. WHEN SET TO A VALUE OTHER THAN0x00, PRE-EMPHASIS IS ADDED AND THE PERCENTAGE IS CONTROLLED BYTHE VALUE IN THIS REGISTER.

DMC_CLC[5:3]DIFFERENTIAL MODE COMPARATOR CABLE LOSS COMPENSATION, CHANNEL 0 ONLY [000] = DISABLE DMC CLC. 001 = ENABLE DMC MINIMUM CLC. 111 = ENABLE DMC MAXIMUM CLC.WHEN SET TO 0x00, THE DIFFERENTIAL MODE COMPARATOR (ON CHANNEL 0 ONLY)HAS NO CABLE LOSS COMPENSATION (CLC) ADDED TO THE INPUT WAVEFORMCHARACTERISTIC. WHEN SET TO A VALUE OTHER THAN 0x00, PRE-EMPHASIS IS ADDEDAND THE PERCENTAGE IS CONTROLLED BY THE VALUE IN THIS REGISTER.

Figure 125. CLC Control Register (ADDR = 0x1F)

Data Sheet ADATE318


LEVEL SETTING DACS DAC UPDATE MODES The ADATE318 provides 24- × 16-bit integrated level setting DACs organized as two channel banks of 12 DACs each. The detailed mapping of the DAC register to pin electronics function is shown in Table 19. Each DAC can be programmed by writing data to the respective SPI register address and channel.

The ADATE318 provides two methods for updating analog DAC levels: DAC immediate update mode and DAC deferred update mode. At release of the CS pin associated with any valid SPI write to a DAC address, the update of analog levels may start immediately1, or it can be deferred, depending on the state of the DAC_LOAD_MODE control bits in the DAC control register (SPI ADDR 0x11[1] (see Figure 116)). The DAC update mode can be selected independently for each channel bank.

If the DAC_LOAD_MODE control bit for a given channel bank is cleared, the DACs assigned to that channel are then in the DAC immediate update mode. Writing to any DAC of that channel causes the corresponding analog level to be updated immediately following the associated release of CS. Because all analog levels are updated on a per-channel basis, any previously pending DAC writes queued to the channel (while in deferred update mode) are also updated at this time. This situation can arise if DAC writes are queued to the channel while in deferred update mode, and the DAC_LOAD_MODE bit is subsequently changed to immediate update mode before the analog levels are updated by writing to the respective DAC_LOAD soft pin. The queued data is not lost. Note that writing to the DAC_LOAD soft pin has no effect in immediate update mode.

If the DAC_LOAD_MODE control bit for a given channel is set, the DACs assigned to that channel are in the deferred update mode. Writing to any DAC of that channel only queues the DAC data into that channel. The analog update of queued DAC levels is deferred until the respective DAC_LOAD soft pin is set (SPI ADDR 0x11[2] (see Figure 116)). The DAC deferred update mode, in conjunction with the respective DAC_LOAD soft pin, provides the means to queue all DAC level writes to a given channel bank before synchronously updating the analog levels with a single SPI command.

Certain pin electronics functions, such as VHH, OVDH, OVDL, and the spare DAC, do not fit neatly within a particular channel bank. However, they must be updated as a part of the channel bank to which they are assigned as shown in Table 19.

The ADATE318 provides a feature in which a single SPI write operation can address two channels at one time (see Figure 115). This feature makes possible a scenario in which a SPI write

1 Initiation of the analog level update sequence (and triggering of the on-chip deglitch circuit) actually begins four SCLK cycles following the associated release of the CS pin. For the purpose of this discussion, it is assumed to start coincident with the release of CS.

operation can address corresponding DACs on both channels at the same time even though the channels may be configured with different DAC update modes. In such a case, the part behaves as expected. For example, if both channels are in immediate update mode, the update of analog levels of both channel banks begins after the associated release of the CS pin. If both channels are in deferred update mode, the update of analog levels is deferred for both channels until the corres-ponding DAC_LOAD bits are set. If one channel is in deferred update mode and the other channel is in immediate update mode, the former channel defers analog updates until the corresponding DAC_LOAD bit is written, and the latter channel begins analog updates immediately after the associated release of the CS pin.

An on-chip deglitch circuit with a period of approximately 3 μs is provided to prevent DAC-to-DAC crosstalk whenever an analog update is processed. Only one deglitch circuit is provided per chip, and it must operate over all physical DACs (both channels) at the same time. The deglitch circuit can be retriggered when an analog levels update is initiated before a previous update operation has completed. In the case of a dual-channel immediate mode DAC write using a single SPI command, the deglitch circuit is triggered once after data is loaded into both DAC channels. Analog transitions at the DAC outputs do not begin until the deglitch circuit has timed out, and final settling to full precision requires an additional 7 μs beyond the end of the 3 μs deglitch interval. Total settling time following release of the associated CS is approximately 10 μs. Note that prolonged and consecutive retriggering of the deglitch circuit by one channel may cause the apparent settling time of analog levels on the other channel to be much longer than the specified 10 μs.

A typical DAC update sequence is illustrated in Figure 126 in which two immediate mode DAC update commands are written in direct succession. This example illustrates what happens when a DAC update command is written subsequent to a previous update command that has not yet finished its deglitch and settling sequence.

Recommended Sequence for OVDH DAC Level Addressing

For correct OVDH addressing, first write data to the OVDH DAC level at SPI 0x0C at CH0. If in DAC immediate mode, the OVDH data write must be followed by either a DAC_LOAD command to SPI 0x11[2] at CH1 or a subsequent write to any other CH1 DAC data address before the OVDH value will be updated. If in DAC deferred mode, the OVDH DAC level write must be followed by a DAC_LOAD command to SPI 0x11[2] at CH1 (not CH0) before the analog OVDH value will be updated.

ADATE318 Data Sheet


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2

tSPI

3µs

tDAC

NOTE 1 NOTE 1±0.5 LSB

COMPLETION OF 3µsDEGLITCH PERIOD

RETRIGGER OF 3µsDEGLITCH PERIOD

BEGINNING OF 3µsDEGLITCH PERIOD

NOTES1. DAC DEGLITCH PERIOD ALWAYS BEGINS FOUR

SCLK CYCLES BEFORE RELEASE OF BUSY.

DAC23

DAC2

DAC1

DAC0

BUSY

SDI

CS

SCLK

SEE TABLE 18

WRITE DAC0 WRITE DAC1

SEE TABLE 18

. . . . . . . .

Figure 126. SPI DAC Write and Settling Time

Addressing M and C Registers

Some DACs have pairs of m/c-coefficients that are controlled depending on other register status. Table 20 details the specific register settings and register addresses for the different pairs (X = don’t care).

Table 20. M- and C-Register Mapping

SPI Address (Channel)

DAC Name

Functional (DAC Usage) Description

m-register

c-register

VHH_ ENABLE 0x18[0]

DMC_ ENABLE 0x1C[0]

LOAD_ ENABLEx 0x19[5]

PPMU_ POWERx 0x1A[15]

PPMU_MEAS_ VIx 0x1A[5]

PPMU_FORCE_VIx 0x1A[4]

PPMU_ RANGEx (0x1A[3:1])

0x0D[0] OVDL Overvoltage detect low 0x2D[0] 0x3D[0] X X X X X X XXX

0x04[0] VOH0 NWC high level, Channel 0

0x24[0] 0x34[0] X 0 X 0 X X XXX

DMC high level 0x44[0] 0x5C[0] X 1 X 0 X X XXX

PPMU go/no-go MV high level, Channel 0

0x45[0] 0x5D[0] X X X 1 0 X XXX

PPMU go/no-go MI Range A high level, Channel 0

0x46[0] 0x5E[0] X X X 1 1 X 111

PPMU go/no-go MI Range B high level, Channel 0

0x47[0] 0x5E[0] X X X 1 1 X 110

PPMU go/no-go MI Range C high level, Channel 0

0x48[0] 0x5E[0] X X X 1 1 X 101

PPMU go/no-go MI Range D high level, Channel 0

0x49[0] 0x5E[0] X X X 1 1 X 100

PPMU go/no-go MI Range E high level, Channel 0

0x4A[0] 0x5E[0] X X X 1 1 X 0XX

Data Sheet ADATE318



DAC Name


m-register

c-register

VHH_ ENABLE 0x18[0]

DMC_ ENABLE 0x1C[0]






0x05[0] VOL0 NWC low level, Channel 0

0x25[0] 0x35[0] X 0 X 0 X X XXX

DMC low level 0x4B[0] 0x63[0] X 1 X 0 X X XXX

PPMU go/no-go MV low level, Channel 0

0x4C[0] 0x64[0] X X X 1 0 X XXX

PPMU go/no-go MI Range A low level, Channel 0

0x4D[0] 0x65[0] X X X 1 1 X 111

PPMU go/no-go MI Range B low level, Channel 0

0x4E[0] 0x65[0] X X X 1 1 X 110

PPMU go/no-go MI Range C low level, Channel 0

0x4F[0] 0x65[0] X X X 1 1 X 101

PPMU go/no-go MI Range D low level, Channel 0

0x50[0] 0x65[0] X X X 1 1 X 100

PPMU go/no-go MI Range E low level, Channel 0

0x51[0] 0x65[0] X X X 1 1 X 0XX

0x08[0] VIOH0 Load IOH level, Channel 0

0x28[0] 0x38[0] X X X X X X XXX

0x09[0] VIOL0 Load IOL level, Channel 0

0x29[0] 0x39[0] X X X X X X XXX

0x02[0] VIT0/ VCOM0

Drive term level, Channel 0

0x22[0] 0x32[0] X X 0 X X X XXX

Load commutation voltage, Channel 0

0x42[0] 0x5A[0] X X 1 X X X XXX

0x01[0] VIH0 Drive high level, Channel 0

0x21[0] 0x31[0] 0 X X X X X XXX

HVOUT drive high level, Channel 0

0x41[0] 0x59[0] 1 X X X X X XXX

0x03[0] VIL0 Drive low level, Channel 0

0x23[0] 0x33[0] 0 X X X X X XXX

HVOUT drive low level, Channel 0

0x43[0] 0x5B[0] 1 X X X X X XXX

0x06[0] VCH0 Ref clamp high level, Channel 0

0x26[0] 0x36[0] X X X 0 X X XXX

PPMU clamp high level, Channel 0

0x52[0] 0x6A[0] X X X 1 X X XXX

0x07[0] VCL0 Ref clamp low level, Channel 0

0x27[0] 0x37[0] X X X 0 X X XXX

PPMU clamp low level, Channel 0

0x53[0] 0x6B[0] X X X 1 X X XXX

0x0A[0] PPMU0 PPMU VIN FV level, Channel 0

0x2A[0] 0x3A[0] X X X X X 0 XXX

PPMU VIN FI Range A level, Channel 0

0x54[0] 0x6C[0] X X X X X 1 111

PPMU VIN FI Range B level, Channel 0

0x55[0] 0x6C[0] X X X X X 1 110

PPMU VIN FI Range C level, Channel 0

0x56[0] 0x6C[0] X X X X X 1 101

PPMU VIN FI Range D Level, Channel 0

0x57[0] 0x6C[0] X X X X X 1 100

PPMU VIN FI Range E level, Channel 0

0x58[0] 0x6C[0] X X X X X 1 0XX

0x0B[0] VHH VHH level 0x2B[0] 0x3B[0] X X X X X X XXX

0x0C[0] OVDH Overvoltage detect high

0x2C[0] 0x3C[0] X X X X X X XXX

ADATE318 Data Sheet



DAC Name


m-register

c-register

VHH_ ENABLE 0x18[0]

DMC_ ENABLE 0x1C[0]






0x04[1] VOH1 NWC high level, Channel 1

0x24[1] 0x34[1] X X X 0 X X XXX

PPMU go/no-go MV high level, Channel 1

0x45[1] 0x5D[1] X X X 1 0 X XXX

PPMU go/no-go MI Range A high level, Channel 1

0x46[1] 0x5E[1] X X X 1 1 X 111

PPMU go/no-go MI Range B high level, Channel 1

0x47[1] 0x5E[1] X X X 1 1 X 110

PPMU go/no-go MI Range C high level, Channel 1

0x48[1] 0x5E[1] X X X 1 1 X 101

PPMU go/no-go MI Range D high level, Channel 1

0x49[1] 0x5E[1] X X X 1 1 X 100

PPMU go/no-go MI Range E high level, Channel 1

0x4A[1] 0x5E[1] X X X 1 1 X 0XX

0x05[1] VOL1 NWC low level, Channel 1

0x25[1] 0x35[1] X X X 0 X X XXX

PPMU go/no-go MV low level, Channel 1

0x4C[1] 0x64[1] X X X 1 0 X XXX

PPMU go/no-go MI Range A low level, Channel 1

0x4D[1] 0x65[1] X X X 1 1 X 111

PPMU go/no-go MI Range B low level, Channel 1

0x4E[1] 0x65[1] X X X 1 1 X 110

PPMU go/no-go MI Range C low level, Channel 1

0x4F[1] 0x65[1] X X X 1 1 X 101

PPMU go/no-go MI Range D low level, Channel 1

0x50[1] 0x65[1] X X X 1 1 X 100

PPMU go/no-go MI Range E low level, Channel 1

0x51[1] 0x65[1] X X X 1 1 X 0XX

0x08[1] VIOH1 Load IOH level, Channel 1

0x28[1] 0x38[1] X X X X X X XXX

0x09[1] VIOL1 Load IOL level, Channel 1

0x29[1] 0x39[1] X X X X X X XXX

0x02[1] VIT1/ VCOM1

Drive term level, Channel 0

0x22[1] 0x32[1] X X 0 X X X XXX

Load commutation voltage, Channel 1

0x42[1] 0x5A[1] X X 1 X X X XXX

0x01[1] VIH1 Drive high level, Channel 1

0x21[1] 0x31[1] X X X X X X XXX

0x03[1] VIL1 Drive low level, Channel 1

0x23[1] 0x33[1] X X X X X X XXX

0x06[1] VCH1 Ref clamp high level, Channel 1

0x26[1] 0x36[1] X X X 0 X X XXX

PPMU clamp high level, Channel 1

0x52[1] 0x6A[1] X X X 1 X X XXX

0x07[1] VCL1 Ref clamp low level, Channel 1

0x27[1] 0x37[1] X X X 0 X X XXX

PPMU clamp low level, Channel 1

0x53[1] 0x6B[1] X X X 1 X X XXX

0x0A[1] PPMU1 PPMU VIN FV level, Channel 1

0x2A[1] 0x3A[1] X X X X X 0 XXX

PPMU VIN FI Range A level, Channel 1

0x54[1] 0x6C[1] X X X X X 1 111

PPMU VIN FI Range B level, Channel 1

0x55[1] 0x6C[1] X X X X X 1 110

PPMU VIN FI Range C level, Channel 1

0x56[1] 0x6C[1] X X X X X 1 101

PPMU VIN FI Range D level, Channel 1

0x57[1] 0x6C[1] X X X X X 1 100

PPMU VIN FI Range E level, Channel 1

0x58[1] 0x6C[1] X X X X X 1 0XX

Data Sheet ADATE318



DAC Name


m-register

c-register

VHH_ ENABLE 0x18[0]

DMC_ ENABLE 0x1C[0]






0x0E[0] Spare Spare level 0x2E[0] 0x3E[1] X X X X X X XXX

DAC TRANSFER FUNCTIONS

Table 21. Detailed DAC Code to Voltage Level Transfer Functions

Levels

Programmable DAC Range1, 0x0000 to 0xFFFF DAC-to-Level and Level-to-DAC Transfer Functions

VIHx, VILx, VITx/VCOMx, VOLx, VOHx, VCHx, VCLx, OVDHx, OVDLx

−2.5 V to +7.5 V VOUT = 2 × (VREF − VREFGND) × (DAC/216 ) − 0.5 × (VREF − VREFGND) + VDUTGND DAC = [VOUT − VDUTGND + 0.5 × (VREF − VREFGND)] × [(216)/(2 × (VREF − VREFGND))]

VHH −3.0 V to +17.0 V VOUT = 4 × (VREF − VREFGND) × (DAC/216 ) − 0.6 × (VREF − VREFGND) + VDUTGND DAC = [VOUT − VDUTGND + 0.6 × (VREF − VREFGND)] × [216/(4 × (VREF − VREFGND))]

IOHx, IOLx −12.5 mA to +37.5 mA IOUT = [2 × (VREF − VREFGND) × (DAC/216 ) − 0.5 × (VREF − VREFGND)] × (25 mA/5) DAC = [(IOUT × (5/25 mA)) + 0.5 × (VREF − VREFGND)] × [216/(2 × (VREF − VREFGND))]

PPMU_VINx (FV) −2.5 V to +7.5 V VOUT = 2 × (VREF − VREFGND) × (DAC/216 ) − 0.5 × (VREF − VREFGND) + VDUTGND DAC = [VOUT − VDUTGND + 0.5 × (VREF − VREFGND)] × [216/(2 × (VREF − VREFGND))]

PPMU_VINx (FI, Range A) −80 mA to +80 mA IOUT = [2 × (VREF − VREFGND) × (DAC/216) − 0.5 × (VREF − VREFGND) − 2.5] × (80 mA/5) DAC = [(IOUT × (5/80 mA)) + 2.5 + 0.5 × (VREF − VREFGND)] × [216/(2 × (VREF − VREFGND))]

PPMU_VINx (FI, Range B) −2 mA to +2 mA IOUT = [2 × (VREF − VREFGND) × (DAC/216 ) − 0.5 × (VREF − VREFGND) − 2.5] × (2 mA/5) DAC = [(IOUT × (5/2 mA)) + 2.5 + 0.5 × (VREF − VREFGND)] × [216/(2 × (VREF − VREFGND))]

PPMU_VINx (FI, Range C) −200 µA to +200 µA IOUT = [2 × (VREF − VREFGND) × (DAC/216 ) − 0.5 × (VREF − VREFGND) − 2.5] × (200 µA/5) DAC = [(IOUT × (5/200 µA)) + 2.5 + 0.5 × (VREF − VREFGND)] × [216/(2 × (VREF − VREFGND))]

PPMU_VINx (FI, Range D) −20 µA to +20 µA IOUT = [2 × (VREF − VREFGND) × (DAC/216) − 0.5 × (VREF − VREFGND) − 2.5] × (20 µA/5) DAC = [(IOUT × (5/20 µA)) + 2.5 + 0.5 × (VREF − VREFGND)] × [216/(2 × (VREF − VREFGND))]

PPMU_VINx (FI, Range E) −4 µA to +4 µA IOUT = [2 × (VREF − VREFGND) × (DAC/216) − 0.5 × (VREF − VREFGND) − 2.5] × (4 µA/5) DAC = [(IOUT × (5/4 µA)) + 2.5 + 0.5 × (VREF − VREFGND)] × [216/(2 × (VREF − VREFGND))]

1 Programmable ranges include the margin outside the specified performance range, allowing for offset and gain calibration.

Table 22. Load Transfer Functions Load Level Transfer Functions Notes IOLx VIOLx/( VREF − VREFGND) × 25 mA VIOLx and VIOHx DAC levels are not referenced to VDUTGND. IOHx VIOHx/( VREF − VREFGND) × 25 mA

Table 23. PPMU Transfer Functions PPMU Mode Transfer Functions1

Uncalibrated PPMU_VIN DAC Settings to Achieve Specified PPMU Range

FV VOUT = PPMU_VINx −2.0 V < PPMU_VINx < +6.5 V MV VPPMU_MEASx = VDUTx (internal sense path) N/A MV VPPMU_MEASx = VPPMU_Sx (external sense path) N/A FI IOUT = [PPMU_VINx − (VREF − VREFGND)/2]/(5 × RPPMU) 0.0 V < PPMU_VINx < 5.0 V MI VPPMU_MEASx = [VREF − VREFGND)/2] + (5 × IOUT × RPPMU) +

VDUTGND N/A

1 RPPMU = 12.5 Ω for Range A, 500 Ω for Range B, 5.0 kΩ for Range C, 50 kΩ for Range D, and 250 kΩ for Range E.

Table 24. VHH Transfer Functions VHH Mode Transfer Functions VHH HVOUT = 2 × [VHH + (VREF − VREFGND)/5] + VDUTGND VIL HVOUT = VIL0 + VDUTGND VIH HVOUT = VIH0 + VDUTGND

ADATE318 Data Sheet


GAIN AND OFFSET CORRECTION Each DAC within the ADATE318 has independent gain (m) and offset (c) correction registers that allow digital trim of gain and offset errors. DACs that are shared between functions or levels are provided with per-level or per-function gain and offset correction registers, as appropriate. These registers provide the ability to calibrate out errors in the complete signal chain, which includes error in pin electronics function as well as the DACs. All m- and c-registers are volatile and must be loaded after power-on as part of a calibration cycle if values other than the defaults are required.

The gain and offset correction function can be bypassed by clearing the DAC_CAL_ENABLE bit in the SPI DAC contol register (SPI ADDR 0x11[0]; see Figure 116). This bypass mode is available on a per-chip basis only; that is, it is not possible to bypass calibration for a subset of the DACs.

The calibration function, when enabled, adjusts the numerical data sent to each DAC according to the following equation:

( )112 2

21 −−+

×

+

= nn cXmX

where: X2 = the data-word loaded into the DAC and returned by an SPI read operation. X1 = the 16-bit data-word written to the DAC SPI input register. m = the code in the respective DAC gain register (default code = 0xFFFF = 2n − 1). c = the code in the respective DAC offset register (default code = 0x8000 = 2n−1). n = the DAC resolution (n = 16).

From this equation, it can be seen that the gain applied to the X1 value is always less than or equal to 1.0, with the effect that a DAC’s output voltage can only be made smaller. To compensate for this numerically imposed limitation, the ADATE318’s signal paths are designed to have gain guaranteed to be greater than 1.0 when the default m values (0xFFFF) are applied. This guarantees that proper gain calibration is always possible. Note also that the value of c is expressed in raw DAC LSBs; that is, it is calculated without considering the effect of the m-register.

When enabled, the calibration function applies the above operation to the X2 register(s) only after a SPI write to the respective X1 register(s). The X2 registers are not updated after writes to either the m- or c-register. In the case of a dual channel write to the DAC, two respective X2 registers are sequentially updated using the appropriate m and c values.

X2 REGISTERS Each DAC has associated with it a single X2 register. There is no provision for storing separate X2 values for DACs shared between functions or ranges. Thus, new data must be written to any shared DAC after a mode or range change is performed, even if the old and new DAC data is identical. The ADATE318 provides separate m- and c-registers for all ranges and modes so

that the new X2 value is calculated correctly following the new data write, provided the desired m and c values are stored in advance. The sequence of operations is critical in that the mode or range change must be performed prior to writing the new DAC data, and both m and c values must be present before the new DAC data is written. The m and/or c value can be written either before or after a mode or range change but must be written prior to the DAC data to have the intended effect.

SAMPLE CALCULATIONS OF M AND C Because the ADATE318’s on-chip DACs have a theoretical output range that exceeds the operating capabilities of the remainder of its signal channels, calibration points must be chosen to be within the normal operating span. Subject to this constraint, calibration is straightforward. One of the keys to understanding the calibration method is to recognize that the intrinsic DAC offset is defined by its output when the input code is 0x0000. This is quite different from the case of the analog signal paths, where a 0 V level occurs when the DAC code is programmed to near quarter-scale.

As a first example, consider the calibration of a drive high level with a theoretical output span of −2.5 V to +7.5 V, a convenient +10.0 V span in which DAC quarter-scale corresponds to precisely 0.0 V out. The ADATE318 drivers do not of course support this full span, but it is a useful choice for illustration of the calibration methodology.

1. Set the channel to drive high and program the VIL andVIT DACs for roughly −1.0 V outputs (Code 0x2700, notcritical). Program the VIH DAC to quarter-scale (0x4000)and measure Output Voltage V1; then program the DAC tothree-quarter-scale (0xC000) and measure Output VoltageV2. Note that V1 and V2 should be measured with respect toDUTGND.

2. Calculate

( )122__ VVFSRDACActual −×=

where (V2 − V1) represents half the full-scale span.3. Calculate the extrapolated DAC voltage at Code 0x0000.

−=

4__

10FSRDACActualVV

4. Calculate

( )768,32

__ 12 VVLSBDACActual −=

5. Calculate

( ) 1536,655

12

−

×

−=

VVm

6. Calculate the offset from the ideal −2.5 V.

( ) 05.2 VOffset −−=

Data Sheet ADATE318


7. Calculate

+=

LSBDACActualOffset

c__

768,32

8. Calculate volts

−

×=12

5_____VV

LSBDACActualLSBDACnCalibratioPost

The above procedure places the DAC’s theoretical 0x0000 output at −2.5 V and its theoretical 0xFFFF output at +7.49985 V (1 LSB below +7.5 V). The useful range extends from below 0x199A (−1.5 V) to above 0xE666 (+6.5 V), a span of at least 52,428 actual DAC codes.

An alternative calibration approach can be used to map all 216 DAC codes onto the part’s specified output range by mapping the zero-code to −1.5 V and the full-scale code to +6.5 V.

1. Repeat Step 1 to Step 4 above.2. Calculate

( ) 535,654

12

×−

=VV

m

3. Calculate the offset from the desired −1.5 V.( ) 05.1 VOffset −−=

4. Calculate DAC

+=

LSBDACActualOffset

c__

768,32

5. Calculate

536,658___ =LSBDACnCalibratioPost Volts

Although this second approach gives an apparent 16 bits of resolution covering the full signal range, it must be kept in mind that this is achieved purely by mathematical alteration of the DAC data. The DAC’s internal LSB step size is not changed. In this example, the number of internal DAC codes used to cover the signal span remains roughly 52,428 even though the number of user codes has increased to 65,536. A consequence of this is that apparent DNL errors are increased as more input codes are mapped onto the same number of DAC codes. While the second calibration method is included here as an example of what is possible, its use can provide a false sense of improved accuracy and it is therefore not recommended.

ADATE318 Data Sheet


POWER SUPPLY, GROUNDING, AND DECOUPLING STRATEGY The ADATE318 product is internally divided into a digital core and an analog core.

The VCC and DGND pins provide power and ground, respectively, for the digital core, which includes the SPI and all digital calibration functions. DGND is the logic ground reference for the VCC supply, and VCC should be adequately bypassed to DGND with low ESR bypass capacitors. To reduce transient digital switching noise coupling from the VCC and DGND pins to the analog core, DGND should be connected to a dedicated ground domain that is separate from the analog ground domains. If the application permits, the DGND should share digital ground domain with the system FPGA or ASIC that interfaces with the ADATE318 SPI. All CMOS inputs and outputs are referenced between VCC and DGND, and their valid levels should be guaranteed relative to these.

The analog core of the product includes all analog ATE functional blocks such as DACs, driver, comparator, load, PPMU, VHH driver, and so on. The VPLUS, VDD, and VSS supplies provide power for the analog core. The AGND and PGND are analog ground and analog power ground references, respectively. PGND is generally more noisy with analog switching transients, and it may also have large static dc currents. The AGND is generally more quiet and has relatively small static dc currents. Ideally, these ground domains should be separated, but it is not necessary. They can be connected together outside the chip to a shared analog ground plane. VDD and VSS should be adequately bypassed to the PGND ground domain. Both PGND and AGND (whether separated or shared) should be kept separate from the DGND ground plane as discussed above.

The VPLUS supply pin has the sole purpose to provide high voltage power for the VHH drive capability (HVOUT pin). If the VHH drive capability is used, the VPLUS supply must be provided as specified. If the VHH drive capability is not used, the VPLUS supply can be connected directly to the VDD supply domain to save power.

The ADATE318 also has a DUTGND input pin that can be used to sense the remote DUT ground potential. All DAC functions

(with the exception of VIOH and VIOL active load currents and VPMU when in PPMU FI mode) are adjusted relative to this DUTGND input. Further, the PPMU measure out pins (PPMU_MEASx) are referenced to DUTGND not AGND. This, therefore, requires the system ADC to reference its inputs relative to DUTGND as well. Referencing the system ADC to AGND results in errors, except in the case that DUTGND is tied to AGND. For applications that do not distinguish between DUT ground reference and system analog ground reference, the DUTGND pin can be connected to the same ground plane as AGND.

The ADATE318 should have ample supply decoupling of 0.1 μF on each supply pin located as close to the device as possible, ideally right up against the device. In addition, there should be one 10 μF tantalum capacitor shared across each power domain. The 0.1 μF capacitor should have low effective series resistance (ESR) and effective series inductance (ESL), such as the common ceramic capacitors that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching.

Digital lines running under the device should be avoided because these couple noise onto the device. The analog ground plane should be allowed to run under the device to avoid noise coupling. The power supply lines should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching digital signals should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the reference inputs. It is essential to minimize noise on all VREF lines. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough throughout the board. As is the case for all thin packages, care must be taken to avoid flexing the package and to avoid a point load on the surface of this package during the assembly process.

Data Sheet ADATE318


USER INFORMATION AND TRUTH TABLES Table 25. Driver Truth Table1

DCL Control Register Bits (0x19) High Speed Inputs

Driver

DCL Enable ADDR 0x19[0]

Force Load ADDR 0x19[2]

Force Drive ADDR 0x19[1]

Force State ADDR 0x19[4:3]

Load Enable ADDR 0x19[5]

DRV_VT_HIZ ADDR 0x19 [6] RCVx DATx

0 X X XX X X X X Low leakage 1 X 1 00 X X X X VIL 1 X 1 01 X X X X VIH 1 X 1 10 X X X X High-Z 1 X 1 11 X X X X VIT 1 X 0 XX X X 0 0 VIL 1 X 0 XX X X 0 1 VIH 1 X 0 XX X 0 1 X High-Z 1 X 0 XX X 1 1 X VIT

1 X = don’t care.

Table 26. Active Load Truth Table1 DCL Control Register Bits (0x19) High Speed Inputs

Load

DCL Enable ADDR 0x19[0]

Force Load ADDR 0x19[2]

Force Drive ADDR 0x19[1]

Force State ADDR 0x19[4:3]

Load Enable ADDR 0x19[5]

DRV_VT_HIZ ADDR 0x19 [6] RCVx DATx

0 X X XX X X X X Low leakage 1 1 X XX X X X X Active on 1 0 X XX 0 X X X Low leakage 1 0 X XX 1 X 0 X Active off 1 0 X XX 1 0 1 X Active on 1 0 X XX 1 1 1 X Active off

1 X = don’t care.

Table 27. VHH and VIH/VIL Driver Truth Table1 VHH_ENABLE ADDR 0x18[0] CH0 RCV (RCV0) CH0 DAT (DAT0) Output of VHH Driver 1 0 0 VIL (Channel 0, VIL DAC) 1 0 1 VIH (Channel 0, VIH DAC) 1 1 X VHH 0 X X Disabled (HVOUT pin set to 0.0 V, approximately 50 Ω impedance)

1 X = don’t care.

Table 28. Comparator Truth Table DMC ENABLE ADDR 0x1C[0] CMPH0 CMPL0 CMPH1 CMPL1 0 Normal window compare

mode Logic high: VOH0 < VDUT0 Logic low: VOH0 > VDUT0

Normal window compare mode Logic high: VOL0 < VDUT0 Logic low: VOL0 > VDUT0

Normal window compare mode Logic high: VOH1 < VDUT1 Logic low: VOH1 > VDUT1


1 Differential compare mode Logic high:

VOH0 < VDUT0 – VDUT1 Logic low:

VOH0 > VDUT0 – VDUT1

Differential compare mode Logic high:

VOL0 < VDUT0 − VDUT1 Logic low:

VOL0 > VDUT0 − VDUT1

Normal window compare mode Logic high: VOH1 < VDUT1 Logic low: VOH1 > VDUT1


ADATE318 Data Sheet


ALARM FUNCTIONS The ADATE318 contains per-channel overvoltage detectors (OVD), PPMU voltage/current clamps, and a per-chip thermal alarm to detect and signal fault conditions. The status of these circuits may be interrogated via the SPI by reading the alarm state register (SPI ADDR 0x1E; see Figure 124). This read-only register is cleared by a read operation. In addition, the fault conditions are combined in the fault alarm logic (see Figure 137) and drive the open drain ALARM pin to signal that a fault has occurred.

The various alarm circuits are controlled through the alarm mask register (ADDR 0x1D; see Figure 123). In the default state, the thermal alarm is enabled, and both the overvoltage alarm and the PPMU clamp alarms are masked off.

The only function of the alarm circuits is to detect and signal the presence of a fault. The only actions taken upon detection of a fault are setting of the appropriate register bit and activating the ALARM pin.

PPMU EXTERNAL CAPACITORS

Table 29. PPMU External Compensation and Feedforward Capacitors External Components Location 220 pF Between FFCAPB0 and FFCAPA0 220 pF Between FFCAPB1 and FFCAPA1 1000 pF Between AGND and SCAP0 1000 pF Between AGND and SCAP1

Table 30. Other External Components External Components Location 10 kΩ ALARM pull-up to VCC

1 kΩ BUSY pull-up to VCC

TEMPERATURE SENSOR

Table 31. Temperature Output 0 K 0.00 V 300 K 3.00 V TKELVIN 0.00 V + (TKELVIN ) × 10 mV/K

Data Sheet ADATE318


DEFAULT TEST CONDITIONS

Table 32. Name Default Test Condition VIHx DAC Levels 2.0 V VITx/VCOMx DAC Levels 1.0 V VILx DAC Levels 0.0 V VOHx DAC Levels 6.5 V VOLx DAC Levels −1.5 V VCHx DAC Levels 7.5 V VCLxDAC Levels −2.5 V VIOHxDAC Levels 0.0 mA VIOLx DAC Levels 0.0 mA PPMU_VINx DAC Levels 0.0 V VHH DAC Level 13.0 V OVDH DAC Levels 7.0 V OVDL DAC Levels −2.0 V DAC_CONTROL 0x0000: DAC calibration disabled, DAC load mode is immediate VHH_CONTROL 0x0000: HVOUT (VHH) disabled DCL_CONTROL 0x0001: DCL enabled, load disabled, high-Z for RCVx = 1, force drive = 0 (to VIL state) PPMU_CONTROL 0x0000: PPMU disabled, PPMU Range E, Force-V1/Measure-V2, input to VDUTGND, internal sense path,

clamps disabled, external PPMU_S open, PPMU_POWER_x off PPMU_MEAS_CONTROL 0x0000: PPMU_MEASx high-Z COMPARATOR_CONTROL 0x0000: normal window comparator mode, comparator hysteresis disabled ALARM_MASK 0x0045: disable alarm functions PRE_EMPHASIS_CONTROL 0x0000: disable driver CLC, differential comparator CLC, and normal window comparator CLC Calibration m-Coefficients 1.0 (0xFFFF) Calibration c-Coefficients 0.0 (0x8000) DATx, RCVx Inputs Logic low DUTx Pins Unterminated CMPHx, CMPLx Outputs Unterminated VDUTGND 0.0 V

1 Force-V indicates force voltage. 2 Measure-V indicates measure voltage.

ADATE318 Data Sheet


DETAILED FUNCTIONAL BLOCK DIAGRAMS

0953

0-02

3

DACVCHx

DACVIT/VCCMx

DACVCLx

DACVIHx

DACVILx DRV

ADDR 0x01, CHx

ADDR 0x06, CHx

ADDR 0x07, CHx

ADDR 0x02, CHx

ADDR 0x03, CHx

DATx

DUTx50Ω

TERM

1

0

1

0

0

(IDEAL CLAMP DIODES)

HIGH-Z

DRV_RCV_MODE(SEE THE DRIVER LOGIC DIAGRAM)

DRV_LOW_LEAK(SEE THE DRIVER LOGIC DIAGRAM)

DRV_RCV_SW(SEE THE DRIVER LOGIC DIAGRAM)

PMU CLAMP LEVELSSHARED WITH HIGH

SPEED DCL CLAMPS

Figure 127. Driver Block Diagram

0953

0-02

4

DCL_ENABLE

ADDR 0x19[0]

FORCE_DRV

ADDR 0x19[1]

FORCE_STATE[1]

ADDR 0x19[4]

FORCE_STATE[0]

ADDR 0x19[3]

DRV_VT_HIZ

ADDR 0x19[6]

DRV_LOW_LEAK

DRV_RCV_MODE(SEE THE DRIVER BLOCK DIAGRAM)

DRV_RCV_SW(SEE THE DRIVER BLOCK DIAGRAM)

RCVx

DRV_LOW_LEAK = DCL_ENABLE

DRV_RCV_MODE = DRIVE_VT_HIZ + FORCE_DRV × FORCE_STATE[0]

DRV_RCV_SW = FORCE_DRV × FORCE_STATE[1] + FORCE_DRV × RCVx

Figure 128. Driver Logic Diagram

Data Sheet ADATE318


VCM

VDM

DAT 1.30V

1.10VDAT

VCM = 1.20VVDM = 200mV

VCM

VDM

RCV 1.25V

0.95VRCV

DAT

DAT

RCV

RCV

VCM = 1.10VVDM = 300mV

TYPICAL INPUT WAVEFORMS

TO DRIVER,LOAD, AND VHH

0.0V ≤ VCM ≤ 3.3V200mV ≤ VDM ≤ 1.0V

100Ω

100Ω

ADATE318

0953

0-02

5

Figure 129. Driver Input Stage Diagram

DACVIOL

ADDR 0x09

ACTIVE LOAD

DACVIT/VCOM

ADDR 0x2

DACVIOH

ADDR 0x08

FROM DRIVER50Ω

DUTx

LOAD_CONNECT(SEE THE ACTIVE LOAD LOGIC DIAGRAM)

LOAD_PWR_DOWN(SEE THE ACTIVE LOAD LOGIC DIAGRAM) 09

530-

026

Figure 130. Active Load Block Diagram

DCL_ENABLE

ADDR 0x19[0]

FORCE_LOAD

ADDR 0x19[2]

LOAD_ENABLE

ADDR 0x19[5]

DRV_VT_HIZ

RCVn

LOAD_PWR_DOWN(SEE THE ACTIVE LOAD BLOCK DIAGRAM)

LOAD_CONNECT(SEE THE ACTIVE LOAD BLOCK DIAGRAM)

ADDR 0x19[6]

LOAD_CONNECT = DCL_ENABLE × (FORCE_LOAD + RCVn × DRV_VT_HIZ × LOAD_ENABLE)

LOAD_PWR_DOWN = DCL_ENABLE + FORCE_LOAD × LOAD_ENABLE 0953

0-02

7

Figure 131. Active Load Logic Diagram

ADATE318 Data Sheet


0953

0-02

8

DACVHH VHH (NOTE 1)VHH DRIVER

VL/VHDRIVER

VIL (NOTE 2)

HVOUT

50Ω50Ω

<5Ω

VIH (NOTE 2)DACVIL

DACVIH

VDUTGND

DAT0

RCV0

NOTES1. VHH = 2 × (DACVHH + (VREF – VREFGND)/5 + VDUTGND) – VDUTGND

2. VIL = DACVIL + VDUTGND; VIH = DACVIH + VDUTGND

VHH_EN

Figure 132. VHH and VIL/VIH Driver Block Diagram

0953

0-02

9

HVOUT

RCV0 L H

H L

L DON’T CARE

DAT0 L H L H L H L H DON’T CAREDON’T CARE

VHH_ENABLEADDR 0x18[0]

DACVIH

DACVHH

DACVIL0.0V

Figure 133. VHH and VIL/VIH Waveform Diagram

Data Sheet ADATE318


0953

0-03

0

DACVOH0

DACVOH0

DACVOL0

DIFFERENTIALCOMPARATOR ONCHANNEL 0 ONLY

TO DUT1

ADDR 0x04

DACVOL0

DMC_ENABLE

ADDR 0x1C[0]

ADDR 0x05

COMPH0

1

0

1

COMPL

COMPL

COMPHDUT0

Figure 134. Comparator Block Diagram

0953

0-03

1

50Ω

VTTC

0.5V ≤ VTT_EXT ≤ VTTCx

50Ω 50Ω50Ω 50Ω

≥ 250mV

VTTCVHI = VTTC – 25mV

VLO = VTTC – 275mV

50Ω

OUTPUTWAVEFORM

ADATE318

CMP

CMP

10mA

Figure 135. Comparator Output Stage Diagram

ADATE318 Data Sheet


0953

0-03

2

F-AMP

PMU_Sx

DUTx

PPMU_Sx

PPMU_MEASx(RELATIVE TO VDUTGND)

PPMU_CMPHx

PPMU_CMPLx

0123

DACVCH

VDUTGND2.5V + VDUTGND

DACVCL

ADDR 0x06, CHxPMU CLAMP LEVELSSHARED WITH HIGH

SPEED DCL CLAMPS

ADDR 0x07, CHx

PPMU_FORCE_E_VI_x

PPMU_MEAS_VI_x

ADDR 0x1A[4], CHx

PPMU_MEAS_SEL_x

ADDR 0x1B[1], CHx

ADDR 0x1A[5], CHx

PPMU_MEAS_ENABLE_x

ADDR 0x1B[0], CHx

ADDR 0x0A, CHx

PPMU_INPUT_SEL_x

ADDR 0x1A[7:6], CHx

PPMU_RANGE_x

ADDR 0x1A[3:1], CHx

VREF/2 + VDUTGND

AV = 5.0

AV = 1.0

PPMU_CLAMP_ENABLE_x

ADDR 0x1A[9], CHx

RPPMU

PPMU_SENSE_PATH_x

ADDR 0x1A[8], CHx

PPMU_ENABLE_x

ADDR 0x1A[0], CHx

PPMU_S_ENABLE_x

ADDR 0x1A[11], CHx

DACPPMU

ADDR 0x04, CHx

VOH x

1.2K

F-AMP

I-AMPCURRENT

VOLTAGE

×10

1CH0: THERM OUTCH1: THERM GND

ADDR 0x05, CHx

VOL x

RANGE

40mA

1mA

100µA

10µA

2µA

RPPMU

12.5Ω

500Ω

5kΩ

50kΩ

250kΩ

PPMU_ENABLE_x

PPMU_POWER_x

ADDR 0x1A[0], CHx

ADDR 0x1A[15], CHx

0 X PPMU IS POWERED DOWN.

1 0 PPMU IS IN FULL-POWER STANDBY MODE BUT NOT YET ENABLED TOFORCE V/FORCE I. USE THIS MODE FOR FAST INTERNAL SETTLING OFLEVELS PRIOR TO ENABLING ACTIVE MODE TO MINIMIZE PPMU GLITCHING.

PPMU GO/NO-GO COMPARATOR DAC LEVELS ARESHARED WITH THE HIGH SPEED PE COMPARATOR.WHEN PPMU IS NOT IN ACTIVE MODE, PPMUGO/NO-GO COMPARATORS ARE NOT USED ANDTHEIR OUTPUTS ARE FORCED TO STATIC LOW.

1 1 PPMU IS IN FULL-POWER ACTIVE MODE.

Figure 136. PPMU Block Diagram

Data Sheet ADATE318


DACOVDH

DACOVDL

ADDR 0x0C, CH0

ADDR 0x0D, CH0

OVD_ALARM_MASK_x

ADDR 0x1D[0], CHx

THERM_ALARM_MASK

ADDR 0x1D[3], CH0

THERM_THRESHOLD

ADDR 0x1D[6:4], CH0

PPMU_ALARM_MASK_x

ADDR 0x1D[2], CHx

TEMPERATURESENSOR(10mV/K)

NOTE: DEDICATED PPMU CLAMP INDICATORSARE PROVIDED FOR EACH CHANNEL. ONLYONE CHANNEL IS SHOWN HERE.

NOTE: DEDICATED OVERVOLTAGE WINDOW COMPARATORSARE PROVIDED FOR EACH CHANNEL. ONLY ONE CHANNELIS SHOWN HERE. THE DACOVDx, LEVELS ARE SHAREDBETWEEN CHANNELS.

FROM PPMUxCLAMP INDICATOR

VCC

VCC

D Q

Q

RESET BY READINGFROM SPI ALARMSTATE REGISTERADDR 0x1E, CHx

ALARM

DUTx

THERM(10mV/K)

0953

0-03

3

Figure 137. Fault Alarm Block Diagram

ADATE318 Data Sheet


OUTLINE DIMENSIONS

1

21

63

43 2242

8464

0.600.500.40

0.600.420.24

0.600.420.24

0.300.230.18

8.00 REF

6.856.75 SQ6.65

0.40BSC

0.20 REF

12° MAX

0.05 MAX0.01 NOM

SEATINGPLANE

0.700.600.50

TOP VIEW

PIN 1INDICATOR

1.000.850.80

0.700.650.60

BOTTOM VIEW

NOTES:1. FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONSSECTION OF THIS DATA SHEET.

2. TIEBARS MAY OR MAY NOT BE SOLDERED TO THE BOARD. 07-0

2-20

12-B

0.930.830.73

0.97(SEE NOTE 2)

0.25(SEE NOTE 2)

EXPOSED PAD(SEE NOTE 1)

10.1010.00 SQ9.90

9.859.75 SQ9.65

COPLANARITY0.08

Figure 138. 84-Lead Lead Frame Chip Scale Package [LFCSP] 10 mm × 10 mm Body and 0.85 mm Package Height

(CP-84-2) Dimensions shown in millimeters

ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADATE318BCPZ TJ = +25°C to +70°C 84-Lead Lead Frame Chip Scale Package CP-84-2

1 Z = RoHS Compliant Part.

©2011–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.

D09530-0-7/17(B)


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