Research and Practices on 3D Networks-on-Chip ArchitecturesAmir-Mohammad Rahmani1,2, Khalid Latif1,2, Pasi Liljeberg1, Juha Plosila1, Hannu Tenhunen1,2

University of Turku, Finland1. Turku Centre for Computer Science (TUCS), Finland2.{amir.rahmani, khalid.latif, pasi.liljeberg, juha.plosila, hannu.tenhunen}@utu.fi

Abstract-To continue the growth of the number oftransistors on a chip, the 3D IC practice, where multiplesilicon layers are stacked vertically, is emerging as arevolutionary technology. Partitioning a larger die intosmaller segments and then stacking them in a 3Dintegration can significantly reduce latency and energyconsumption. Such benefits emanate from the notion thatinter-wafer distances are negligible compared to intra-waferdistances which substantially reduce global wiring length in3D chips. This progress has introduced novel architecturesand new challenges for high-performance power-awaredesign exploration. In this paper, we outline theopportunities and challenges associated with three-dimensional networks-on-chip architectures, underconsideration for different design metrics. In this context,we categorize and present several alternatives for 3D NoCarchitectures and we investigate and summarize the impactof these architectures on various system characteristics.

I. INTRODUCTION

Communication plays a crucial role in the design andperformance of multi-core systems-on-chip (SoCs). Recentlyon-chip transistor density has been considerably increased andthis enables the integration of dozens of components on a singledie. One outcome of greater integration is that interconnectionnetworks have started to replace shared buses. Networks-on-chip (NoCs) [1][2] are proposed to be used in complex SoCs forcommunication between cores because they scale better thantraditional forms of on-chip interconnections, and have betterperformance and power consumption characteristics [2]. Thedesign of 2D NoCs has been examined from various aspects,such as performance, power and reliability [3][4][5][6][7][8]and some commercial products already deploy such networks[9][10]. The advent of three-dimensional (3D) stackedtechnologies provides a new horizon for on-chip interconnectdesign. 3D ICs, which contain multiple layers of active devices,have the potential for enhancing system power/performancecharacteristics [11][12][13][14][15]. 3D ICs allow forperformance enhancements even in the absence of scaling[12][16]. This is because of the reduced length of interconnects.Besides this clear benefit, package density is increasedsignificantly, power is reduced due to shorter wires, andcircuitry is more immune to noise [12]. The power/performanceimprovement arising from the architectural advantages of NoCswill be significantly enhanced if 3D ICs are adopted as the basicfabrication methodology. The amalgamation of two emergingparadigms, NoC and 3D IC, allows for the creation of newstructures that enable significant performance enhancementsover more traditional solutions. With freedom in the thirddimension, architectures that were prohibitive due to wiringconstraints in 2D ICs are now possible, and many 3Dimplementations can outperform their 2D counterparts [11].

Even though both 3D integrated circuits and NoCs areproposed as alternatives for the interconnect scaling demands,there are several challenges of combining both approaches todesign three-dimensional NoCs such as only a fewcommercially available EDA tools and lack of designmethodologies, high peak temperatures, increased powerdensities and large area footprints of vertical interconnects. Toaddress these issues new architectures and design methods are

needed. In the last few years, there have been many efforts ininterconnection network designs for 3D stacked CMPs. Thepurpose of this survey is to clarify the 3D NoC concept and tomap the scientific efforts made into the area of architectural andtopological optimizations in NoC research. We will identifygeneral trends and explain a range of issues which are importantfor designing efficient 3D NoC architectures. Moreover, thissurvey highlights the significance of difference networkcharacteristics (e.g. power dissipation, thermal issues, etc) inon-chip networks, and brings valuable insights and comparisonsof different existing architectures in the area of 3D on-chipnetwork designs.

The rest of this paper is organized as follows: Section IIcovers basics and developments pertinent to 3D integratedcircuits technologies. Section III provides details of the existingresearch and practices on 3D Networks-on-Chip designs andpresents the impact of existing architecture on different systemcharacteristics, while Section IV summarizes the survey.

II. THREE-DIMENSIONAL NETWORKS-ON-CHIP

In the last few years, there have been many efforts to designand fabricate 3D ICs for different applications. The designsinclude a NAND Flash using double stack S3 technology [17]form Samsung [18], 3D-OTP memory from Matrix [19], theDARPA 3D IC project [20] from MIT Lincoln Laboratories,and also IBM [21] and Tezzaron [22] recent projects. These 3Dintegrated circuits have emerged to overcome the limitations ofinterconnect scaling [23] by stacking active silicon layers[24][25]. Compared with traditional 2D design, 3D ICs offer anumber of advantages: such as shorter global interconnects,higher performance, lower interconnect power consumption dueto wire-length reduction, higher packing density and smallerfootprint, and support for the implementation of mixed-technology chips [29][30]. In this context, several 3D designshave appeared recently. This section gives a brief introductionon the exploration of possible technologies

Several vertical interconnect technologies have beenexplored, including wire bonding, microbump, contactless(capacitive or inductive), and through-silicon-via (TSV) verticalinterconnect [13]. Among several 3D integration technologies,TSV is the most promising one, hence the majority of 3Dintegration R&D activities concentrate on this approach [23].

Utilizing 3D design offers increased bandwidth [33] andreduced length of average interconnection wire [34], whichresults in a considerable saving in overall power consumption.It has been also demonstrated that a 3D design can be utilized toimprove reliability [35]. However, the adoption of a 3Dintegration technology faces the challenges of increasing chiptemperature due to increasing power density compared to aplanar 2D design [36]. In this context, several techniques havebeen proposed in 3D architectures such as physical designoptimization through intelligent placement [37], increasingthermal conductivity of the stack through insertion of thermalvias [36], and use of novel cooling structures [38]. In addition, arecent work reveals that in placement of the processing cores ina 3D chip, the areal power density is the more significant designconstraint [39]. Consequently, thermal concern can be managedas long as components with high power density are not stackedon top of each other. To prevent severe thermal problems,architectures that stack memory on top of processor cores, or978-1-4244-8971-8/10$26.00 c©2010 IEEE

those that rely on low-power processor cores have beendeveloped [40]. It should be noted at this point that increasedtemperatures increase wire resistances, and consequently theinterconnect delays [41].

III. 3D ARCHITECTURES

Recently, various architectures were proposed for 3D NoCswhich have different impacts on design metrics. This part isconcerned with the existing architectures for 3D NoC designand reviews their influences on different system characteristics.

i. SYMMETRIC NOC ARCHITECTUREIn order to integrate many nodes into a 3D chip, simplest

approach is to group the nodes into multiple layers and basicallystack them on top of each other as shown in Figure 1(a), whichshows 3 layers stacked together, each with 9 nodes, totaling 27nodes. We call this architecture a 3D Symmetric NoC, sinceboth intra- and inter-layer movement bear identicalcharacteristics: hop-by-hop traversal. Despite of simplicity, thisarchitecture has two major inherent drawbacks. Firstly, it doesnot exploit the beneficial attribute of a negligible inter-waferdistance (around 50 μm per layer) in 3D chips [42]. Sincetraveling in the vertical dimension is multi-hop, it takes thesame time as moving within the layer. In this architecture, inter-layer and intra-layer hops are indistinguishable, in spite of theaverage number of hops between a source and a destinationdoes decrease as a result of folding a 2D design into multiplestacked layers. In addition, buffering and arbitration delay ofeach flit at every hop, add to the overall delay for routing withinthe layer. Secondly, a larger 7×7 crossbar is obligated as a resultof two extra ports. According to [42], crossbars scale upwardvery inefficiently and it can be seen from their reported resultsthat compared with 5×5 crossbar, a 6×6 crossbar consumesabout 21% more power, and the power consumption of a 7×7crossbar is approximately 2.24 times more than the 5×5counterpart. Thus, 3D Symmetric NoC implementation is asomewhat naive extension to the baseline 2D network becauseof its excessive area and power overhead.

ii. 3D NOC-BUS HYBRID ARCHITECTUREOne of the main characteristics of a 3D IC is the short

interlayer distances [13]. In order to take advantage of thisapplicable attribute, 3D NoC-Bus Hybrid architecture wasproposed that is a hybrid between packet-switched network anda bus. Accordingly, with the potential of utilizing this benefit, asymmetric NoC architecture with multi-hop communication inthe inter-layer dimension is not efficient. In this architecture,given the very small inter-layer distance, single-hopcommunication is, in fact, feasible. As can be seen from Figure1(b), the NoC router can be hybridized with a bus link in thevertical dimension to create a 3D NoC-Bus Hybrid structure.This approach was first used in a 3D NUCA L2 Cache forCMPs [43]. This hybrid system provides both performance andarea benefits. It requires a 6×6 crossbar, since the bus adds asingle additional port to the generic 2D 5×5 crossbar andcompared to 7×7 crossbar in symmetric architecture, it is lesspower-hungry and occupies less area. The additional link formsthe interface between the NoC domain and the bus domain. Thebus link has its own dedicated queue, which is controlled by acentral arbiter. Flits from different layers wishing to moveup/down should arbitrate for access to the shared medium.Furthermore, each bus has only a small number of nodes,keeping overall capacitance on the bus small and considerablysimplifying bus arbitration.

However, despite this encouraging result, there is anopposite side of the coin which paints a rather bleak picture,because the bus approach also suffers from a followingdrawback. Since the bus is a shared medium, it does not allowconcurrent communication in the third dimension. Therefore, inhigh network loads, probability of contention and blockingcritically increases. As result of this, there is a considerabledegradation in inter-layer bandwidth despite single-hop verticalcommunication does improve performance in terms of overalllatency.

iii. CILIATED 3D MESH ARCHITECTUREAnother proposed method of constructing a 3D NoC is by

adding layers of functional IP blocks and restricting theswitches to one layer or a small number of layers. In thiscontext, Feero et al. [11], introduce new architecture calledciliated 3D Mesh. This structure is essentially a 3D Meshnetwork with multiple IP blocks per switch. For the ciliated 3DMesh, a 3 × 3 × 3 3D Mesh network with three IPs per switch,is shown in Figure 1(c). In a ciliated 3D Mesh network, eachswitch contains at most 5+k ports (one for each cardinaldirection, two for up and down (one either up or down in two-layer 3D mesh), and one to each of the k IP blocks. Inconsequence of multiple IP cores per switch and diminishedconnectivity this architecture presents lower overall bandwidthcompared to a symmetric 3D Mesh. Nonetheless, it was shownthat this type of network offers an advantage in terms of energydissipation, especially in the presence of specific trafficpatterns.

iv. TRUE 3D NOC ROUTERConcerning with drawbacks of the preceding architectures,

the implementation of a true 3D crossbar with the target ofseamless integration of the vertical links in the overall routeroperation, can be desirable. Based upon this envision, in [42] anefficient router structure was offered, the illustration of such a3D crossbar layout can be seen from Figure 1(d). It should benoted that the traditional definition of a crossbar - in the contextof a 2D physical layout - is a switch in which each input isconnected to each output through a single connection point.However, extending this definition to a physical 3D structurewould imply a switch of enormous complexity and size (giventhe increased numbers of input- and output port pairs associatedwith the various layers). In this architecture a simpler structurewas chosen which can accommodate the connection of an inputto an output port through more than one connection points.

The vertical links are embedded in the crossbar and extendto all layers. This implies the use of a 5×5 crossbar, since noadditional physical channels need to be dedicated for interlayercommunication. Interconnection between the various links in a3D crossbar would have to be provided by dedicated connectionboxes at each layer. These connecting points can facilitatelinkage between vertical and horizontal channels, allowingflexible flit traversal within the 3D crossbar. The improvedarchitecture (particularly on crossbar structure) of the True 3DNoC router called DimDe has been proposed which reveals therather enhanced energy-delay product characteristic [42].

Despite this encouraging result, there are some importantdrawbacks. Adding a large number of vertical links in a 3Dcrossbar to increase NoC connectivity leads to increased pathdiversity and means multiple possible paths between source anddestination pairs, and actually leads to a dramatic increase in thecomplexity and power consumption of the central arbiter.

Figure 1. NoC architectures. (a) Three-Dimensional mesh. (b) NoC-Bus Hybrid mesh (c) Ciliated 3D mesh (d) NoC routers with true 3D crossbars

v. TREE-BASED 3D NOCSButterfly fat tree (BFT) [44], [45] and the generic fat tree, orSPIN [46] are the two types of tree-based interconnectionnetworks that have been considered for NoC applications.According to [11], considerable enhancements can be achievedwhen these networks are instantiated in a 3D IC environment.Unlike the work with mesh-based NoCs, any new topologies fortree-based systems were not proposed. Instead, they present theachievable performance benefits by instantiating already-existing tree-based NoC topologies in a 3D environment.

It can be concluded from their reported results that when the2D BFT network is mapped onto a multi-layer 3D SoC, wirerouting becomes simpler, and the longest interswitch wirelength is reduced by at least a factor of two, in comparison withthe one-layer 2D implementation. This will lead to reducedenergy dissipation as well as smaller area overhead. They arguethat the fat tree topology will have the same advantages whenmapped onto a 3D IC as the BFT.

vi. XNOTS 3D NOCTo make the best utilization of the short delay and high

density of inter-wafer links, Xbar-connected Network-on-Tiers(XNoTs), which consist of multiple network layers tightlyconnected via crossbar switches, is proposed by Matsutani et al.[47]. XNoTs-based architectures have crossbar switches thatconnect different layers and their cores, in such a way that the2D topology on every layer can be independently customized soas to meet the cost-performance requirements, as far as networkconnectivity is at least guaranteed with the bottom layer. Thearchitecture is not power-efficient, because it requires largevertical switches.

vii. MIRA 3D NOCPark et al. [48] propose a Multi-layered on-chip Interconnect

Router Architecture (MIRA), which is based on implementing a2D mesh chip-multiprocessor in three dimensions. Unlike theexplained 3D routers, MIRA is a 3D stacked NoC routerarchitecture which is stacked into multiple layers and optimizedto reduce the overall area requirements and power consumption.The major drawback of the architecture is that it assumes theprocessor cores are designed in 3D. This makes it difficult toreuse existing highly optimized 2D processor core designs.

viii. DE-BRUIJN GRAPH-BASED 3D NOCArchitectures like typical 3D mesh, ciliated 3D mesh or tree

based 3D NoC have a common disadvantage: the large networklatency because of large network diameter of mesh topology. In[49], Chen et al. propose a novel 3D NoC architecture based onDe-Bruijn graph. The De-Bruijn topology is an efficienttopology for parallel processing purposes. The advantages ofDe-Bruijn graph network topology are small diameter, highconnectivity and high reliability [50]. The degree of NoC basedon De-Bruijn graph does not change with an increase in the sizeof network.

This architecture benefits from a simple routing algorithm.The De-Bruijn architecture provides better throughputperformance as compared to the 3D mesh NoC because ofshorter diameter. On other hand, the solution is not powerefficient as compared to the 3D mesh NoC because shorterroute cannot be achieved in most cases. The proposed topologyis shown in Figure 2(a).

ix. SERIALIZED VERTICAL CHANNEL 3D NOCIn 3D ICs, vertical TSVs take significant chip area because

of their typically spread-out distribution. Pasricha [51]proposes the serialization of vertical TSV interconnects toreduce their area footprint and avoid the routing congestion ofinterconnects. Such serialization can lead to a better thermalTSV distribution resulting in lower peak temperatures. Theextra space made available on each layer due to serializationcan be used for efficient core layout across multiple layers androuting, as well as more efficient thermal TSV insertion fortemperature management. Such area savings and other benefitscome at the cost of nominal power and performance overhead.

Author has presented the impact on performance withvarying degrees of serialization. The performance degradationis about 1.7% on average for various applications for 4:1serialization (64à 16 wires) but reaches around 16.1% for 64:1serialization (64 à 1 wire). Performance degradation dependson the frequency of vertical transfers as well. The lower degreesof serialization like 4:1 or 2:1 are more practical because ofsmaller degradations in performance and lower powerconsumption overhead but significantly reducing the footprintarea.

x. HONEYCOMB 3D NOCFor a topology design, there is always a tradeoff between

degree and diameter. The degree refers to the hardware cost.Mesh and torus are the main stream topologies because of theirhigh regularity, symmetry and scalability but with extrahardware cost (degree). Yin et al. [52] propose the honeycombinterconnect topology as an alternative for NoC based designs.Honeycomb topology reduces the network cost significantly,while maintaining the positive characteristics of typical meshand torus topologies.

For regular mesh and torus topologies in two dimensionaldomains, the honeycomb mesh and torus provide anapproximate 40% reduction in terms of network cost. Smallernetwork degree for honeycomb topology makes the routerarchitecture simpler, reliable and power efficient. The 3Dhoneycomb mesh topology with network degree ‘5’ is shown inFigure 2(b). To further reduce the network cost, vertical linkscan be removed by systematically bi-partitioning of the routersinto odd and even groups. The authors present the deadlock freerouting algorithm for 3D honeycomb topology as well.

xi. LOW-RADIX 3D NOCThe key problem faced by current 3D stacking technology is

that only vertical inter-layer links are allowed. Due to which,the direct connection between arbitrary nodes located atdifferent layers is not allowed. In case of 3D NoC architectures,the system design is highly constrained by the complexity andpower of routers and links. Thus, the low radix routers arepreferred due to lower power consumption and better heatdissipation. This makes the latency value higher due to high hopcounts in network paths.

Xu et al. [53] present an efficient network topology for 3DNoCs by using the long range links. As shown in Figure 2(c),utilization of long-range links makes the topology low diameterbut requires only low-radix routers to implement. The longrange links show significant reduction in latency even for thehigher operating frequency and pipelined wires. The increase inpower consumption is sub-linear to the increase in length. Theauthors present an optimal operating frequency of 1GHz for 3DNoCs because higher clock frequency for 3D chip brings theconcern of high heat dissipation.

xii. LAYER-MULTIPLEXED 3D NOCAs discussed above, architectures like 3D NoC-Bus hybrid

can reduce the network cost, but there are some otherperformance bottlenecks like bus bandwidth limitations.Another issue is the layer load-balancing. If one layer is

congested and other layers have very light load, the system isnot power and performance efficient.

Ramanujam et al. [54] present an efficient Layer-Multiplexed (LM) 3D architecture for vertical communicationwith the consideration of load balancing. More precisely, thelayer-multiplexed architecture replaces the one-layer-per-hoprouting in a conventional 3D mesh with simpler vertical de-multiplexing and multiplexing stages. There are two majordrawbacks for the proposed architecture. First is to traversepackets through two stage crossbar, which makes it lesspower and area efficient. Second is to use two hops perpacket for vertical communication, which makes thearchitecture less throughput efficient. On the other hand,reduced degree of router and layer load balancing compensatesthe power degradation.

xiii. BBVC-3D-NOCIn 3D NoCs, as the number of cores increases in each layer

to support increasing application complexity, the amount ofcommunication between layers is also expected to grow, andconsequently the number of interconnect TSVs will get higher.Since each TSV requires a pad for bonding to a wafer layer, thearea footprint of TSVs in each layer is no longer negligible. Asdiscussed before, serialization of vertical TSV interconnects isproposed as a way to reduces the interconnect TSV footprint.However, it degrades the performance due to serializationoverhead and low bandwidth utilization.

In [55], Rahmani et al. explore a mechanism to reduce TSVarea footprint, and thus improving 3D IC cost, routability,thermal efficiency, and power consumption. Specifically, theypropose a novel technique to replace the pair of unidirectionalvertical channels between layers by a bidirectional channel thatis dynamically self-reconfigurable to be used in either out-goingor incoming direction. To compensate the bandwidthdegradation, they exploit the low-latency nature of verticalTSVs by establishing high-speed inter-layer communicationusing mixed-clock FIFOs. Figure 2(d) shows the schematicrepresentation of their proposed Bidirectional BisynchronousVertical Channels (BBVC) -based NoC. The main idea of theproposed 3D NoC system is to exploit a bidirectional channelfor inter-layer communication operating at a higher frequencycompared to intra-layer communication (f2>f1) and beingcapable of dynamically changing the channel direction betweenrouters in neighboring layers based on the real time need ofbandwidth. The BBVC-3D-NoC can cope with the majorinherent drawbacks of the 3D symmetric NoC architecture byexploiting the beneficial attribute of a negligible inter-wafer

distance in 3D chips. In addition, BBVCs are only responsiblefor inter-layer communication. In other words, the proposedinter-layer communication scheme is independent of the intra-layer topology. The main disadvantage of the BBVC-3D-NoCis that it does not support bus-based vertical communication,thus communication on vertical dimension is not single hop.

xiv. SPECIAL PURPOSE 3D NOCSDesign of 3D SoCs satisfying the application performance

requirements with minimum power consumption, whilesatisfying the 3D technology constraints is a big challenge. Asynthesis based power-performance efficient design approachfor 3D NoCs can deal with such issues.

Seiculescu et al. [56] present a tool for NoC topologysynthesis for 3D ICs named SunFloor 3D. Path computation,assignment and placement of network elements in 3D layers arealso the tasks for the tool. The separate algorithms for core toswitch connectivity and path computation are presented with thecorresponding constraints. The comprehensive comparisonbetween 2D and 3D NoCs is also presented, which shows that3D integration can significantly reduce the latency and powerconsumption as compared to the 2D interconnects. Thetopologies produced by SunFloor tool show significant powerand latency savings as compared to the standard topologies.Similar approach has been adopted by [57].

IV. SUMMARY

Recently, Networks-on-Chip architectures have gainedpopularity to address the interconnect delay problem fordesigning on-chip multi-core systems in deep sub-microntechnology. However, almost all prior studies have focused on2D NoC designs. Since three dimensional (3D) integration hasemerged to mitigate the interconnect delay and power problem,exploring the NoC design space in 3D can provide ampleopportunities to design high performance and energy-efficientNoC architectures. In this survey, we have given an overview ofthe existing architecture for 3D NoC and highlighted theirimpact on network characteristics. We have first stated themotivation for 3D NoC and given an introduction of the basicconcepts. Furthermore, we investigate various architecturalalternatives for designing a high-performance and energy-efficient 3D NoC system. We have demonstrated that besidesreducing the footprint in a fabricated design, 3D networkstructures provide better power consumption and performancecharacteristics compared to traditional, 2D NoC architectures.We have demonstrated that most NoC architectures are capableof achieving better power/performance when instantiated in a3D IC environment compared to more traditional 2Dimplementations. The pros and cons of the analyzed structuresare concisely summarized and reported in Table 1.

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