5-Descripcion Del Hardware PTN 910 y 950_es

8/12/2019 5-Descripcion Del Hardware PTN 910 y 950_es

http://slidepdf.com/reader/full/5-descripcion-del-hardware-ptn-910-y-950es 1/46

Descripción del Hardware PTN 910 y 950

Confidential Information of Huawei. No Spreading Without Permission

P-0





P-1





P-2





P-3





P-4

Radio Acess Network

Huawei PTN provide seamless end-to-end Backhaul solutions from the convergence layer,HUB layer to Cellsitelayer. Huawei PTN series can be used to construct end-to-end Packet

Transport network.

In the Network, can be used for fiber-optic network, the highest rate of network reach 10GE,

and can be extended to 400G with built-in WDM; can be used for IP Radio Network, thehighest rate of network reach 300M; can also make use of leased lines for networking.through using statistical multiplexing in Cell site, HUB nodes, can save leased-line bandwidthand reduce rental costs.Throughout the network, all services are built through the construction of PWE3 over MPLS,

end-to-end network management.





P-5





P-6





P-7





P-8





P-9





P-10

NOTE:

When housed in slot 1 or slot 2, the EG2 can process 2 x GE signals. When housed inany other slot, the second port of the EG2 is not available.

As the ML1 and ML1A have the same functions except for the match impedance.

The second port of the CD1 can be used for only the LMSP protection.

The ADS2A supports the Annex A mode. The ADS2B supports the Annex B mode.

On one NE, only one AUXQ board can be housed.





P-11





P-12





P-13

NOTE:

The CXPA and CXPB each house two slots. Slot 1 and slot 2 house one CXPA or CXPB.As the CXPA and CXPB have the same functions except for the match impedance.

The CXPG and CXPH each house two slots. Slot 1 and slot 2 house one CXPG orCXPH. As the CXPG and CXPH have the same functions except for the match

impedance. The second port of the CD1 can be used for only the LMSP protection.

As the ML1 and ML1A have the same functions except for the match impedance.

The ADS2A supports the Annex A mode. The ADS2B supports the Annex B mode.





P-14





P-15





P-16





P-17

The EF8T mainly consists of the access and convergence module, control driver module, clockmodule, and power supply module.

Access and Convergence Module

Accesses 8 x FE electrical signals.

Buffers FE signals to avoid packet loss.

Provides flow control frames to control the number of packets.

Processes the IEEE 1588V2 packets. (PTP= Precision Time Protocol)

Control Driver Module

Detects the system status through the management bus.

Detects any fault of the system control board.

Detects whether board is loosened from the slot.

Detects the voltage and temperature.

Realizes the hot swappable function of the board.

Clock Module

Provides the working clock for each module on the board. Supports the synchronous Ethernet and the SSM (Synchronous Status Message)

protocol.

Supports the IEEE 1588V2 protocol.

Supports the 1588 ACR clock. (ACR=Adaptive clock recovery)

Power Supply Module

Accesses two -48 V DC or -60 V DC power supplies.

Supplies 3.3 V and 1.2 V power for the EF8T.





P-18

The EF8F mainly consists of the access and convergence module, control driver module, clockmodule, and power supply module.

Access and Convergence Module

Accesses 8 x FE optical signals.



Processes the IEEE 1588V2 packets.


Detects the system status through the management control bus.

Checks whether any fault occurs on the system control board.




Clock Module

Provides the working clock for each module on the EF8F. Supports the synchronous Ethernet and the SSM protocol.


Supports the 1588 ACR clock.

Power Supply Module

Accesses two - 48 V DC or - 60 V DC power supplies.

Supplies 3.3 V and 1.2 V power for the EF8F.





P-19

The EG2 mainly consists of the interface conversion module, control driving module, clockmodule, and power supply module.

Interface Conversion Module

Accesses 2 x GE services in two directions.

Supports ESFP optical interfaces and GE colored optical interfaces. Select a proper

optical interface for single-mode or multi-mode transmission over a specified distance.

Control Driving Module


Detects any fault of the system control board.




Clock module

Provides the working clock for each module on the EG2.

Supports the synchronous Ethernet and the SSM protocol. Supports the IEEE 1588V2 protocol.

Supports the 1588 ACR clock.

Power Supply Module


Supplies 3.3 V or 1.2 V power for each module on the EG2.





P-20

The AUXQ mainly consists of the service access module, auxiliary interface module, control driver module, clockmodule, and power supply module.

Service Access and Processing Module

Accesses 4 x FE electrical signals.

Provides physical-layer interfaces, supports medium access control (MAC) communication.



Processes the IEEE 1588V2 packets.

Auxiliary Interface Module

Provides one 64 kbit/s synchronous data port, which is compliant with ITU-T G.703, is used totransparently transmit other NM data.

Provides one orderwire interface.

Provides two channels of alarm concatenation and two channels of alarm output.

Provides four channels of alarm input.



Detects any fault of the CXP.

Detects the active/standby status of the CXP.



Processes the alarm signals, orderwire signals, and transparent data signals. Realizes the hot swappable function of the board.

Clock Module

Provides the working clock to the service access and processing module.

Provides the working clock to the auxiliary interface module.

Supports the synchronous Ethernet and the SSM protocol.


Power Supply Module


Supplies 1.2 V, 3.3 V, and 5 V power for each module on the board.





P-21





P-22

The CD1 consists of the SDH processing module, line processing module, data processing module, managementmodule, clock module, and power supply module.

SDH Processing Module

In the receive direction, this module accesses 1 x channelized STM-1 signals, decapsulates the VC-12timeslots from the STM-1 signals, obtains the E1 signals by demapping the VC-12 timeslots, andprocesses the overhead bytes, pointers, and alarm signals.

In the transmit direction, this module receives the E1 signals from the line processing module, maps the

signals to the VC-12 timeslots, multiplexes the VC-12 timeslots to STM-1 signals, adds the overheadbytes and pointers, processes the alarm signals, and sends out the 1 x channelized STM-1 signalsthrough the interface on the backplane.

Line Processing Module

In the receive direction, this module receives the signals from the SDH processing module, rearrangesthe frames of the E1 signals, performs processing for various services such as setup and deletion of theIMA link, creation of the ML-PPP group, extraction of protocol packets in the ML-PPP services, andsuppression of timeslots of the CES services. Then, the processed signals are sent to the data processingmodule.

In the transmit direction, this module receives the signals from the data processing module, processesvarious services, and sends the processed signals to the SDH processing module.

Data Processing Module

In the receive direction, this module obtains the corresponding PW channel information of each E1service, performs the PWE3 encapsulation and PW scheduling, and sends the processed signals to theCXPA/CXPG through the interface on the backplane.

In the transmit direction, this module receives the signals from the CXPA/CXPG, identifies different

service types, and performs the PWE3 decapsulation and service scheduling. Management Module

When used with the CXPA/CXPG, this module manages and controls each module on the CD1.

Clock Module

Processes the line clocks.

Accesses and processes the system clock from the CXPA/CXPG, and provides the working clock to eachmodule on the CD1.

Supports the SSM protocol.

Power Supply Module

Accesses two -48 V/-60 V DC power supplies.

Supplies the working power for each module on the CD1.





P-23





P-24

Conector Anea 96

Modulos: Control, procesamiento de lado línea, procesamiento de sistema (CES/IMA/ML-PPP),modulo de interfaz backplane, reloj y fuente de poder

The ML1 mainly consists of the control module, line-side processing module, system-side

processing module, backplane interface module, clock module, and power supply module.

Line-Side Processing Module

In the receive channel, this module performs impedance match, signal equalization,

electrical level conversion, clock data recovery, dejitter, and decoding to signals. Inthe transmit channel, this module performs encoding, dejitter, pulse shaping, and linedriving to signals.

System-Side Processing Module

This module frames 16 x E1 signals, runs the CES, IMA, and ML-PPP protocols, andperforms PWE3 encapsulation.

Backplane Interface Module

The service bus receives or transmits service signals.

Control Module

This module controls the reading and writing on the chip, resets the chip, and detectsfaults in the chip.When used with the CXPA/CXPG, this module controls the board.



Clock Module

This module provides various clock signals for the board to operate normally, detectsclocks, and selects the line recovery clock.

Power Supply Module

This module converts the -48 V DC/-60 V DC voltage to DC voltages required by each

module on the board. In addition, this module supplies 3.3 V power to the ML1through the backplane.



P-25





P-26





P-27

PVC: Private Virtual Circuit

The ADS2 mainly consists of the service access module, interface converting module, clockmodule, and power supply module.

Service Access Module

The ADSL transceiver unit strips the ATM AAL5 adaptation layer from the ADSL

service accessed from the interface and then outputs the service.

The ADSL transceiver unit performs ATM AAL5 adaptation and encapsulation for theservice sent by the interface converting and control module and finally outputs theADSL service.

The line driver unit amplifies the signals to be transmitted.

Interface Converting and Control Module

This module performs parallel/serial conversion for transporting the service betweenthe system control board and the local board.

The system control board controls and manages the board through the serialmanagement bus. In addition, the logic control unit detects alarms and reports them

to the CXPA/CXPG through the serial management bus. Clock Module

The clock module provides working clock signals to each module.

Power Supply Module

This module provides DC voltages required by each module on the board.





P-28

The SHD4 mainly consists of the service access module, interface converting module, clockmodule, and power supply module.


The service access module transforms the signal voltage and performs protection forthe access signals. Then, the service encapsulation and bundling module bundles four

channels of G.SHDSL signals, strips the ATM AAL5 adaptation layer, and finallyoutputs the service signals.

The interface converting and control module sends the service to the serviceencapsulation and bundling module, which then performs ATM AAL5 adaptation and

encapsulation, and finally outputs the G.SHDSL service.


This module performs parallel/serial conversion for transporting the service between

the system control board and the local board.

The system control board controls and manages the board through the serialmanagement bus. In addition, the logic control unit detects alarms and reports themto the CXPA/CXPG through the serial management bus.

Clock Module

The clock module provides working clock for each module on the SHD4.

Power Supply Module

This module provides DC voltages required by each module on the board.





P-29

The SHD4I mainly consists of the service access module, interface converting and controlmodule, IMA processing module, clock module, and power supply module.


In the receive direction, this module converts the serial packets to parallel packets,and sends the parallel packets to the interface converting and control module.

In the transmit direction, this module receives the IMA service signals from the

interface converting and control module, converts the serial IMA service signals toparallel IMA service signals, and finally sends the parallel IMA service signals to theG.SHDSL interfaces.

In addition, this module extracts the NTR clock signals from the G.SHDSL servicesignals received and sends the clock signals to the clock module.


In the receive direction, this module receives the IMA service signals from the serviceaccess module, converts the IMA service signals, and sends the service signals to theIMA processing module, which multiplexes the service signals . Then, this modulereceives the ATM cells from the IMA processing module, decapsulates the ATMframes, converts the parallel signals to serial signals, converges the signals to onechannel service signal, and finally sends the service signal to the backplane.

In the transmit direction, this module receives the service signal from the backplane,

converts the serial signal to parallel signal, encapsulates the service signal into ATMframes, and sends the ATM cells to the IMA processing module, which inverselymultiplexes the ATM signals. Then, this module receives IMA signals from the IMAprocessing module and finally sends the IMA signals to the service access module.

In addition, this module works with the CXPA/CXPG to manage and control eachmodule on the SHD4I.



IMA Processing Module

In the receive direction, this module receives the IMA service signals from theinterface converting and control module, multiplexes the service signals as ATMsignals, and finally sends the ATM signals to the interface converting and controlmodule, which converges the signals.

In the transmit direction, this module receives the service signals from the backplane

after the interface converting and control module processes the service signals. Then,this module inversely multiplexes the ATM signals and sends the IMA service signals tothe interface converting and control module.

Clock Module

Selects a clock source from the four channels of NTR clock signals and uploads theclock signals to the CXPA/CXPG.

Provides working clock signals for each module on the SHD4I board.

Power Supply Module

This module provides the following DC voltages for the modules on the SHD4Iboard:3.3 V/ 1.8 V/ 1.5 V/ 1.2 V.



P-30





P-31





P-32





P-33

NOTE:

When rotate only one ejector lever, the protection switching is not

triggered. The protection switching is triggered only when you rotate the

two ejector levers.

Other Functions: APS

Supports MPLS Tunnel APS.

Supports 1:1 PW APS with dual-ended switching.

MPLS Tunnel OAM: Supported

PW OAM: Supported

BFD: Supports BFD with a period of 3.3 ms, 10 ms, 20 ms, 50 ms, 100 ms, or 1s.





P-34





P-35

Other Functions:

Fractional E1: Supports the CES services and IMA services at 64 kbit/s level.

Interface function

Type of the loopback at the FE port: PHY-layer inloop/ MAC-layer outloop

Automatic loopback release at the port: Supported

LAG

Intra-board LAG: Supported

Inter-board LAG: Supported

APS




PW OAM: Supported

BFD

Supports BFD with a period of 3.3 ms, 10 ms, 20 ms, 50 ms, 100 ms, or 1s.

Black list and white list of MAC addresses: Supported

Clock

Synchronous Ethernet: Supported

SSM protocol: Supported

IEEE 1588V2 protocol: Supported

1588 ACR clock: Supported





P-36

NOTE:

The FE1 to FE4 interfaces, ETH/OAM interface and EXT/F1 interface support auto-adaptation to a straight-through network cable or a crossover network cable.





P-37

Other Functions:

Fractional E1: Supports the CES services and IMA services at 64 kibt/s level.

LAG

Intra-board LAG: Supported

Inter-board LAG: Supported

APS




PW OAM: Supported

BFD: Supports BFD with a period of 3.3 ms, 10 ms, 20 ms, 50 ms, 100 ms, or 1s.

Black list and white list of MAC addresses: Supported

Clock

Synchronous Ethernet: Supported

SSM protocol: Supported

IEEE 1588V2 protocol: Supported

1588 ACR clock: Supported





P-38

NOTE:

The FE1 to FE4 interfaces and ETH/OAM interface support auto-adaptation to astraight-through network cable or a crossover network cable.





P-39

Note:

• Press the CF RCV button for 5 seconds, the equipment automatically restores the configuration data

from the CF card.

• When you press the RST button and then release it, the board is reset (warm).

• When you press the LAMP button, all the board indicators on the NE, except the Ethernet service

interface indicators, should be on.





P-40





P-41





P-42





P-43





P-44



Descripción del Hardware PTN 910 y 950 P-45

Documents

5-Descripcion Del Hardware PTN 910 y 950_es