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8/13/2019 4.Interrupts
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Embedded Software Design, 2005, Pao-Ann Hsiung, National Chung Cheng University
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Contents
Microprocessor ArchitectureInterrupt Basics
Shared-Data Problem
Interrupt Latency
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Microprocessor Architecture Assembly language = human-readable
microprocessor instructions1 assembly instruction = 1 CPU instruction1 C statement = 1 or more CPU instructionsEvery family of microprocessors has adifferent assembly language
Microprocessor registers:general-purpose: R1, R2, R3, special: program counter, stack pointer,
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Assembly-Language InstructionsMOVE R3, R2
MOVE R5, (iTemperature)MOVE R5, iTemperature
ADD R7, R3NOT R4JUMP NO_ADD
NO_ADD: MOVE (xyz), R1SUBTRACT R1, R5JCOND ZERO, NO_MORE
Value of variable
iTemperature frommemory
Address of variableiTemperature in
memory
Unconditional Jump
Conditional Jump
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Assembly-Language InstructionsCALL ADD_EM_UP
MOVE (xyz), R1
ADD_EM_UP: ADD R1, R3 ADD R1, R4
ADD R1, R5RETURN
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Context AwarenessSince embedded systems are closely
relevant to the contexts, how can theseexternal events be noticed?
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I/O InterruptsThe most common approach is to use
interrupts .Interrupts cause the microprocessor in theembedded system
to suspend doing whatever it is doing, andto execute some different code instead.
Interrupts can solve the response problem,
but not without some difficult programming,and without introducing some new problemsof their own.
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Interrupt Hardware
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Interrupt BasicsMicroprocessor detects interrupt request (IRQ)
signal is assertedStops executing instructionsSaves on stack the address of nextinstructionJumps to interrupt service routine (ISR) andexecutes itReturns from ISRPops address from stack
Continues execution of next instruction
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Interrupt Service Routine (ISR)Do whatever needs to be done when the
interrupt signal occursE.g.: character received at serial port chip
read character from chipput it into memory
Miscellaneous housekeeping:reset interrupt-detecting hardware in CPUenable processing interrupts of lower priorities
Last instruction: RETURN or return from ISR
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ISR vs. Procedure CallsTo execute ISRs, there is NO CALL
instruction.The microprocessor does the callautomatically.
An array, interrupt vector , of addresses isused to point to appropriate ISRs.
ISRs must be loaded when the computer is
turned on.Interrupts can be masked.The context need to be saved.
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Interrupt Routines
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Disabling InterruptsTwo ways:
At Source : tell I/O chip to stop interrupting At Destination : inform CPU to ignore IRQs
Selective disabling can be performedWrite a value in a special register
Two types of interruptsMaskable : can be disabled, normal I/ONonmaskable : cannot be disabled, powerfailure, catastrophic event, etc.(ISR must not share data with task code!)
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Disabling InterruptsPriority-based interrupt disabling/enabling
Assign a priority to each IRQ
Program specifies lowest acceptable priority
All IRQ with lower priorities will be disabled All IRQ with higher priorities will be enabled
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Some Common QuestionsHow do CPUs know where to find ISR ?
At fixed location: e.g.: 8051 IRQ1: 0x0003In IVT (Interrupt Vector Table): addresses ofeach ISR
How does CPU know where IVT is? At fixed location: e.g.: 80186: 0x00000Depends on CPU
Can CPU be interrupted within an instruction ?Usually not
Except: inst with large data movements
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Some Common Questions (contd)2 IRQ at same time, which one to service?
According to prioritiesCan an IRQ interrupt an ISR?
Yes: default behavior on some CPUs
Interrupt nesting:80x86 : all IRQs disabled automatically, ISRmust reenable interruptsOthers : automatic, high-priority IRQ caninterrupt low-priority ISR
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Some Common Questions (contd)Interrupts signaled, while IRQs are disabled?
Interrupts are remembered by microprocessor Serviced after IRQs are enabled, in priority-order (actually only deferred)
IRQs disabled, forgot to enable?System halted
CPU start up: interrupts enabled or disabled?Disabled
ISR in C? Yes!
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ISR in C?Non-standard keyword: interrupt (depends on
CPU)void interrupt vHandleTimerIRQ (void) { }Compiler will automatically add code to saveand restore the contextCompiler will add RETURN at endC code of ISR must setup IVTC is a little slower than assembly, if speed isnot of concern, C can be used to write ISR!
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Textbook: An Embedded Software Primer,David E. Simon, Addison Wesley
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The Shared-Data Problem
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A Powerful ISR DesignCan the ISR do everything you want?
Yes, but this is very impractical.
main(){
int i;// setting up ISRs// do nothing but an empty loopwhile(1)
i=i+0;}
SampleISR()
{
newVal:= ReadADConverter()
call StartNewConversion()
}
SampleISR()
{
newVal:= ReadADConverter()
call StartNewConversion()
}
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A Practical ApproachThe ISR should do the necessary tasks
moving data from I/O devices to the memory buffer orvice versahandling emergent signalssignaling the task subroutine code or the kernel
The ISR needs to notify some other procedure to dofollow-up processing.
Task Code ISR ISR
Shared Variables
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Accessing the Shared DataHowever, this may cause the shared data problem.
ISR
Task Code
Interrupt
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The Shared Data ProblemThe unexpected interrupt
may cause two readings to be different,even though the two measured temperatureswere always the same.
How can we improve on this?Compare these temperature measurementsdirectly!
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Directly TestingThe new code
ISR
Task Code
Testing
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A Bug Harder to Be Detected The compiler translation
Interruptible
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Characteristics of Shared-Data Bug A bug that is very hard to find.
It does not happen every time the code runs.The program may run correctly most of thetime.
However, a false alarm may be set offsometimes.
How can you trace back if the embedded
system has already exploded?Remember the Therac-25 accidents?
There were many shared variables!!!
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Characteristics of Shared-Data Bug
Whenever ISR and task code share data
Be suspicious!!!
Analyze the situation to locate any such bugs!!!
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Textbook: An Embedded Software Primer,David E. Simon, Addison Wesley
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Solving the Shared-Data
Problem
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Solving Shared-Data ProblemSolution : Disable interrupts before using
shared data in task code, enable them after!C compilers have functions to disable andenable interrupts
Processors have instructions to disable andenable interrupts
Problem : Compilers not smart enough toautomatically add disable/enable instructionsaround shared code. Users must DO IT!
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Solving Shared-Data Problem:Disabling Interrupts in C
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Atomic Instructions/Sections A More Convenient Way
Use some atomic instructions supported bythe hardware.
An instruction is atomic if it cannot be
interrupted.The collection of lines can be atomic byadding an interrupt-disable instruction.
A set of instruction that must be atomic for thesystem to work properly is often called acritical section .
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Another Example A buggy program
imprecise answer
Interrupt
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Interrupts with a Timer Bug:
lSecondsSinceMidnight() interrupted!iSeconds, iMinutes, iHours changed byvUpdateTime()
Wrong answer by lSecondsSinceMidnight()
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Several Possible SolutionsDisable the interrupt
A buggy solution- Interrupts will not be appropriately enabled.
A buggy solution
- Interrupts will not be appropriately enabled.
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A Better CodeChanging the timing of return()
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The Best WayThe nested interrupts
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Another Potential SolutionDoing things in the ISR
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Is the solution correct?Depends on if the microprocessors registersare large enough to hold a long integer lSecondsSinceMidnight() in assembly
MOVE R1, (lSecondsToday)
RETURN
MOVE R1, (lSecondsToday)
MOVE R2, (lSecondsToday+1)RETURN
YES! ATOMIC
NO! NOT ATOMIC
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Solution without disabling interrupts
(needsvolatilekeyword)
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Compiler optimizations defeat the
purpose of the solutionSolution :
read twice lSecondsToday, if not changedthen no interrupt occurred between the reads
Problems :
After lReturn = lSecondsToday;, compilersaves lSecondsToday and assumes that it hasnot changed since the last read, thus using the
saved value instead of newly reading itwhile loop is optimized out of existence!
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The volatile Keyword Need to declare:
static volatile long int lSecondsToday;
Compiler will know that the variable is volatileand each reference is read from memory
If this keyword is not supported, you can stillget the similar result by turning off thecompiler optimizations .
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Textbook: An Embedded Software Primer,David E. Simon, Addison Wesley44
Interrupt Latency
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Interrupt LatencyHow fast does my system respond to each
interrupt?Longest period of interrupt disabled time
Total execution time of higher priorityinterrupts
Time for microprocessor to stop execution ,
switch context , start ISR executionExecute ISR till an initial response
CPU
docs
Simulation, Estimation
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To Reduce Interrupt LatenciesFactor 4: Initial response of ISR
Write efficient codeFactor 3: Context switch
Hardware dependent
Factor 2: Exec of higher-priority ISRsWrite short ISRs!
Factor 1: Disable interruptsTo solve shared-data problem,Shorten period
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Make your ISRs shortFactory Control System
A task to monitor a gas leak detector Call fire deptShut down affected factory part
High priorityCall fire dept = several secondsDelays all other lower priority interruptsTherefore, remove telephone call from ISR
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Disabling InterruptsSystem requirements:
Disable interrupts for 125 microseconds toread 2 shared temperature variables
Disable interrupts for 250 microseconds toget time from shared variables
Respond within 625 microseconds to special
signals, ISR takes 300 microseconds toexecute
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Worst Case Interrupt Latency
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Worst Case Interrupt LatencyDesign Change :NetworkEnhancement
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Alternatives to Disabling InterruptsTwo variable sets
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Two Variable SetsThis simple mechanism solves the shared-
data problem, because the ISR will neverwrite into the set of temperatures that the taskcode is reading.
However, the while-loop may be executedtwice before it sets off the alarm.
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A Queue ApproachThe shared-data problem is also eliminated.
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A Queue Approachmain()
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A Queue ApproachHowever, this code is very fragile.
Either of these seemingly minor changes cancause bugsIn task code (main):
Reversing the following order could cause shareddata bug
Read data firstUpdate iTail pointer second
If the following statement is non-atomic, shareddata bug could occur
iTail += 2;
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Shared Data in Therac-25 Software