4Gb: x16, x32 Mobile LPDDR2 SDRAM S4

Mobile LPDDR2 SDRAMMT42L256M16D1, MT42L128M32D1, MT42L256M32D2,MT42L128M64D2, MT42L512M32D4, MT42L192M64D3,MT42L256M64D4, MT42L384M32D3

Features Ultra low-voltage core and I/O power supplies

VDD2 = 1.141.30V VDDCA/VDDQ = 1.141.30V VDD1 = 1.701.95V

Clock frequency range 53310 MHz (data rate range: 106620 Mb/s/pin)

Four-bit prefetch DDR architecture Eight internal banks for concurrent operation Multiplexed, double data rate, command/address

inputs; commands entered on every CK edge Bidirectional/differential data strobe per byte of

data (DQS/DQS#) Programmable READ and WRITE latencies (RL/WL) Programmable burst lengths: 4, 8, or 16 Per-bank refresh for concurrent operation On-chip temperature sensor to control self refresh

rate Partial-array self refresh (PASR) Deep power-down mode (DPD) Selectable output drive strength (DS) Clock stop capability RoHS-compliant, green packaging

Table 1: Key Timing Parameters

SpeedGrade

Clock Rate(MHz)

Data Rate(Mb/s/pin) RL WL tRCD/tRP1

-18 533 1066 8 4 Typical

-25 400 800 6 3 Typical

-3 333 667 5 2 Typical

Options Marking VDD2: 1.2V L Configuration

32 Meg x 16 x 8 banks x 1 die 256M16 16 Meg x 32 x 8 banks x 1 die 128M32 16 Meg x 32 x 8 banks x 2 die 256M32 1 (16 Meg x 32 x 8 banks) + 2 (32

Meg x 16 x 8 banks)384M32

32 Meg x 16 x 8 banks x 4 die 512M32 16 Meg x 32 x 8 banks x 2 die 128M64 16 Meg x 32 x 8 banks x 3 die 192M64 16 Meg x 32 x 8 banks x 4 die 256M64

Device type LPDDR2-S4, 1 die in package D1 LPDDR2-S4, 2 die in package D2 LPDDR2-S4, 3 die in package D3 LPDDR2-S4, 4 die in package D4

FBGA green package 134-ball FBGA (10mm x

11.5mm)GU, GV

168-ball FBGA (12mm x 12mm) LF, LG 216-ball FBGA (12mm x 12mm) LH, LK, LL, LM,

LP 220-ball FBGA (14mm x 14mm) LD, MP 240-ball FBGA (14mm x 14mm) MC 253-ball FBGA (11mm x 11mm) EU, EV

Timing cycle time 1.875ns @ RL = 8 -18 2.5ns @ RL = 6 -25 3.0ns @ RL = 5 -3

Operating temperature range From 30C to +85C WT From 40C to +105C AT

Revision :A

Note: 1. For Fast tRCD/tRP, contact factory.

4Gb: x16, x32 Mobile LPDDR2 SDRAM S4Features

PDF: 09005aef84427aab4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN 1

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.

Table 2: Single Channel S4 Configuration Addressing

Architecture 256 Meg x 16 128 Meg x 32 256 Meg x 32 384 Meg x 32 512 Meg x 32

Dieconfiguration

CS0# 32 Meg x 16 x 8banks

16 Meg x 32 x 8banks




CS1# n/a n/a 16 Meg x 32 x 8banks



Row addressing 16K (A[13:0]) 16K (A[13:0]) 16K (A[13:0]) 16K (A[13:0]) 16K (A[13:0])

Columnaddressing

CS0# 2K (A[10:0]) 1K (A[9:0]) 1K (A[9:0]) 1K (A[9:0]) 2K (A[10:0])

CS1# n/a n/a 1K (A[9:0]) 2K (A[10:0]) 2K (A[10:0])

Number of die 1 1 2 3 4

Die per rank CS0# 1 1 1 1 2

CS1# 0 0 1 2 2

Ranks per channel 1 1 1 2 2 2

Note: 1. A channel is a complete LPDRAM interface, including command/address and data pins.

Table 3: Dual Channel S4 Configuration Addressing

Architecture 128 Meg x 64 192 Meg x 64 256 Meg x 64

Die configuration 16 Meg x 32 x 8 banks 16 Meg x 32 x 8 banks 16 Meg x 32 x 8 banks

Row addressing 16K (A[13:0]) 16K (A[13:0]) 16K (A[13:0])

Column addressing CS0# 1K (A[9:0]) 1K (A[9:0]) 1K (A[9:0])

CS1# n/a 1K (A[9:0]) 1K (A[9:0])

Number of die 2 3 4

Die per rank CS0# 1 1 1

CS1# 0 1 = Channel A0 = Channel B

1

Ranks per channel 1 Channel A 1 2 2

Channel B 1 1 2

Note: 1. A channel is a complete LPDRAM interface, including command/address and data pins.




Figure 1: 4Gb LPDDR2 Part Numbering

Micron Technology

Product Family42 = Mobile LPDDR2 SDRAM

Operating VoltageL = 1.2V

Configuration256M16 = 256 Meg x 16

128M32 = 128 Meg x 32

256M32 = 256 Meg x 32

384M32 = 384 Meg x 32

512M32 = 512 Meg x 32

128M64 = 128 Meg x 64

192M64 = 192 Meg x 64

256M64 = 256 Meg x 64

AddressingD1 = LPDDR2, 1 die

D2 = LPDDR2, 2 die

D3 = LPDDR2, 3 die

D4 = LPDDR2, 4 die

Design Revision:A = First generation

Operating TemperatureWT = 30C to +85C

AT = 40C to +105C

Cycle Time-18 = 1.875ns, tCK RL = 8

-25 = 2.5ns, tCK RL = 6

-3 = 3.0ns, tCK RL = 5

Package CodesGU, GV = 134-ball FBGA, 10mm x 11.5mm

LF, LG = 168-ball FBGA, 12mm x 12mm

LH, LK, LL, LM, LP = 216-ball FBGA, 12mm x 12mm

LD, MP = 220-ball FBGA, 14mm x 14mm

MC = 240-ball FBGA, 14mm x 14mm

EU, EV = 253-ball FBGA, 11mm x 11mm

MT 42 L 128M32 D1 GU -25 WT :A

FBGA Part Marking Decoder

Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from thepart number. Microns FBGA part marking decoder is available at www.micron.com/decoder.

Table 4: Package Codes and Descriptions

PackageCode Ball Count # Ranks # Channels Size (mm)

Die perPackage

Solder BallComposition

GU 134 1 1 10 x 11.5 x 0.7, 0.65 pitch SDP LF35 (w/OSP)

GV 134 2 1 10 x 11.5 x 0.85, 0.65 pitch DDP LF35 (w/OSP)

LF 168 1 1 12 x 12 x 0.75, 0.5 pitch SDP SAC305

LG 168 2 1 12 x 12 x 0.8, 0.5 pitch DDP SAC305

LH 216 1 1 (Chan B only) 12 x 12 x 0.65, 0.4 pitch SDP SAC305

LL 216 1 2 12 x 12 x 0.8, 0.4 pitch DDP SAC305

LM 216 2 2 12 x 12 x 1.0, 0.4 pitch QDP SAC305

LK 216 2 1 (Chan B only) 12 x 12 x 0.8, 0.4 pitch DDP SAC305

LP 216 2 1 (Chan B only) 12 x 12 x 0.82, 0.4 pitch 3DP SAC305

MP 220 1 2 14 x 14 x 0.8, 0.5 pitch DDP SAC305

LD 220 2 2 14 x 14 x 1.0, 0.5 pitch QDP SAC305

MC 240 1 2 14 x 14 x 0.8, 0.5 pitch DDP SAC305

EU 253 1 2 11 x 11 x 0.9, 0.5 pitch DDP LF35 (w/OSP)

EV 253 2 2 11 x 11 x 1.2, 0.5 pitch QDP LF35 (w/OSP)

Notes: 1. SDP = single-die package, DDP = dual-die package, 3DP = triple-die package, QDP = quad-die package2. Solder ball material: LF35 with Cu OSP ball pads (98.25% Sn, 1.2% Ag, 0.5% Cu, 0.05% Ni),




SAC305 (96.5% Sn, 3% Ag, 0.5% Cu).




ContentsGeneral Description ....................................................................................................................................... 12

General Notes ............................................................................................................................................ 12IDD Specifications ........................................................................................................................................... 13Package Block Diagrams ................................................................................................................................. 18Package Dimensions ....................................................................................................................................... 24Ball Assignments and Descriptions ................................................................................................................. 37Functional Description ................................................................................................................................... 46Power-Up ....................................................................................................................................................... 47

Initialization After RESET (Without Voltage Ramp) ...................................................................................... 49Power-Off ....................................................................................................................................................... 49

Uncontrolled Power-Off .............................................................................................................................. 50Mode Register Definition ................................................................................................................................ 50

Mode Register Assignments and Definitions ................................................................................................ 50ACTIVATE Command ..................................................................................................................................... 61

8-Bank Device Operation ............................................................................................................................ 61Read and Write Access Modes ......................................................................................................................... 62Burst READ Command ................................................................................................................................... 62

READs Interrupted by a READ ..................................................................................................................... 69Burst WRITE Command .................................................................................................................................. 69

WRITEs Interrupted by a WRITE ................................................................................................................. 72BURST TERMINATE Command ...................................................................................................................... 72Write Data Mask ............................................................................................................................................. 74PRECHARGE Command ................................................................................................................................. 75

READ Burst Followed by PRECHARGE ......................................................................................................... 76WRITE Burst Followed by PRECHARGE ....................................................................................................... 77Auto Precharge ........................................................................................................................................... 78READ Burst with Auto Precharge ................................................................................................................. 78WRITE Burst with Auto Precharge ............................................................................................................... 79

REFRESH Command ...................................................................................................................................... 81REFRESH Requirements ............................................................................................................................. 87

SELF REFRESH Operation ............................................................................................................................... 89Partial-Array Self Refresh Bank Masking .................................................................................................... 90Partial-Array Self Refresh Segment Masking .............................................................................................. 91

MODE REGISTER READ ................................................................................................................................. 92Temperature Sensor ................................................................................................................................... 94DQ Calibration ........................................................................................................................................... 96

MODE REGISTER WRITE Command ............................................................................................................... 98MRW RESET Command .............................................................................................................................. 98MRW ZQ Calibration Commands ................................................................................................................ 99ZQ External Resistor Value, Tolerance, and Capacitive Loading .................................................................... 101

Power-Down ................................................................................................................................................. 101Deep Power-Down ........................................................................................................................................ 108Input Clock Frequency Changes and Stop Events ............................................................................................ 109

Input Clock Frequency Changes and Clock Stop with CKE LOW .................................................................. 109Input Clock Frequency Changes and Clock Stop with CKE HIGH ................................................................. 110

NO OPERATION Command ........................................................................................................................... 110Simplified Bus Interface State Diagram ....................................................................................................... 110

Truth Tables .................................................................................................................................................. 112Electrical Specifications ................................................................................................................................. 120

Absolute Maximum Ratings ....................................................................................................................... 120




Input/Output Capacitance ......................................................................................................................... 120Electrical Specifications IDD Specifications and Conditions ........................................................................... 121AC and DC Operating Conditions ................................................................................................................... 124AC and DC Logic Input Measurement Levels for Single-Ended Signals ............................................................. 127

VREF Tolerances ......................................................................................................................................... 128Input Signal .............................................................................................................................................. 128

AC and DC Logic Input Measurement Levels for Differential Signals ................................................................ 131Single-Ended Requirements for Differential Signals .................................................................................... 132Differential Input Crosspoint Voltage ......................................................................................................... 134Input Slew Rate ......................................................................................................................................... 134

Output Characteristics and Operating Conditions ........................................................................................... 135Single-Ended Output Slew Rate .................................................................................................................. 136Differential Output Slew Rate ..................................................................................................................... 137HSUL_12 Driver Output Timing Reference Load ......................................................................................... 140

Output Driver Impedance .............................................................................................................................. 140Output Driver Impedance Characteristics with ZQ Calibration .................................................................... 141Output Driver Temperature and Voltage Sensitivity ..................................................................................... 142Output Impedance Characteristics Without ZQ Calibration ......................................................................... 142

Clock Specification ........................................................................................................................................ 146tCK(abs), tCH(abs), and tCL(abs) ................................................................................................................ 147

Clock Period Jitter .......................................................................................................................................... 147Clock Period Jitter Effects on Core Timing Parameters ................................................................................. 147Cycle Time Derating for Core Timing Parameters ........................................................................................ 148Clock Cycle Derating for Core Timing Parameters ....................................................................................... 148Clock Jitter Effects on Command/Address Timing Parameters ..................................................................... 148Clock Jitter Effects on READ Timing Parameters .......................................................................................... 148Clock Jitter Effects on WRITE Timing Parameters ........................................................................................ 149

Refresh Requirements .................................................................................................................................... 150AC Timing ..................................................................................................................................................... 151CA and CS# Setup, Hold, and Derating ........................................................................................................... 157Data Setup, Hold, and Slew Rate Derating ....................................................................................................... 164Revision History ............................................................................................................................................ 171

Rev. O 08/13 ............................................................................................................................................ 171Rev. N 05/13 ............................................................................................................................................ 171Rev. M 10/12 ........................................................................................................................................... 171Rev. L 08/12 ............................................................................................................................................ 171Rev. K 07/12 ............................................................................................................................................ 171Rev. J 07/12 ............................................................................................................................................. 171Rev. I 05/12 ............................................................................................................................................. 171Rev. H 04/12 ............................................................................................................................................ 171Rev. G 04/12 ............................................................................................................................................ 172Rev. F 03/12 ............................................................................................................................................ 172Rev. E 02/12 ............................................................................................................................................ 172Rev. D 12/11 ............................................................................................................................................ 172Rev. C 12/11 ............................................................................................................................................ 172Rev. B 05/11 ............................................................................................................................................ 172Rev. A 02/11 ............................................................................................................................................ 172




List of FiguresFigure 1: 4Gb LPDDR2 Part Numbering ............................................................................................................ 3Figure 2: VDD1Typical Self Refresh Current vs. Temperature ............................................................................. 17Figure 3: VDD2 Typical Self Refresh Current vs. Temperature ............................................................................ 17Figure 4: Single Rank, Single Channel Package Block Diagram ......................................................................... 18Figure 5: Dual Rank, Single Channel Package Block Diagram ........................................................................... 18Figure 6: Dual Rank, Single Channel (3 Die) Package Block Diagram ................................................................ 19Figure 7: Single Rank, Dual Channel Package Block Diagram ........................................................................... 20Figure 8: Dual Rank, Dual Channel Package Block Diagram ............................................................................ 21Figure 9: Dual Rank, Dual Channel (3 Die) Package Block Diagram .................................................................. 22Figure 10: Dual Rank, Single Channel (4 Die) Package Block Diagram .............................................................. 23Figure 11: 134-Ball FBGA 10mm x 11.5mm Single-Die (Package Code GU) ..................................................... 24Figure 12: 134-Ball FBGA 10mm x 11.5mm Dual-Die (Package Code GV) ....................................................... 25Figure 13: 168-Ball FBGA 12mm x 12mm Single-Die (Package Code LF) ........................................................ 26Figure 14: 168-Ball FBGA 12mm x 12mm Dual-Die (Package Code LG) .......................................................... 27Figure 15: 216-Ball FBGA 12mm x 12mm (Package Codes LK, LL) .................................................................. 28Figure 16: 216-Ball FBGA 12mm x 12mm (Package Code LM) ........................................................................ 29Figure 17: 216-Ball FBGA 12mm x 12mm (Package Code LH) ........................................................................ 30Figure 18: 216-Ball FBGA 12mm x 12mm (Package Code LP) ......................................................................... 31Figure 19: 220-Ball FBGA 14mm x 14mm Dual-Die (Package Code MP) ......................................................... 32Figure 20: 220-Ball FBGA 14mm x 14mm Quad-Die (Package Code LD) ......................................................... 33Figure 21: 240-Ball FBGA 14mm x 14mm Dual-Die (Package Code MC) ......................................................... 34Figure 22: 253-Ball FBGA 11mm x 11mm Dual-Die (Package Code EU) ......................................................... 35Figure 23: 253-Ball FBGA 11mm x 11mm Quad-Die (Package Code EV) ......................................................... 36Figure 24: 134-Ball FBGA (x16) ....................................................................................................................... 37Figure 25: 134-Ball FBGA (x32) ....................................................................................................................... 38Figure 26: 168-Ball FBGA 12mm x 12mm ..................................................................................................... 39Figure 27: 216-Ball 2-Channel FBGA 12mm x 12mm ..................................................................................... 40Figure 28: 216-Ball 1-Channel (B) FBGA 12mm x 12mm ................................................................................ 41Figure 29: 220-Ball 2-Channel FBGA 14mm x 14mm ..................................................................................... 42Figure 30: 240-Ball 2-Channel FBGA 14mm x 14mm ..................................................................................... 43Figure 31: 253-Ball 2-Channel FBGA 11mm x 11mm ..................................................................................... 44Figure 32: Functional Block Diagram ............................................................................................................. 46Figure 33: Voltage Ramp and Initialization Sequence ...................................................................................... 49Figure 34: ACTIVATE Command .................................................................................................................... 61Figure 35: tFAW Timing (8-Bank Devices) ....................................................................................................... 62Figure 36: READ Output Timing tDQSCK (MAX) ........................................................................................... 63Figure 37: READ Output Timing tDQSCK (MIN) ........................................................................................... 63Figure 38: Burst READ RL = 5, BL = 4, tDQSCK > tCK ..................................................................................... 64Figure 39: Burst READ RL = 3, BL = 8, tDQSCK < tCK ..................................................................................... 64Figure 40: tDQSCKDL Timing ........................................................................................................................ 65Figure 41: tDQSCKDM Timing ....................................................................................................................... 66Figure 42: tDQSCKDS Timing ......................................................................................................................... 67Figure 43: Burst READ Followed by Burst WRITE RL = 3, WL = 1, BL = 4 ......................................................... 68Figure 44: Seamless Burst READ RL = 3, BL = 4, tCCD = 2 .............................................................................. 68Figure 45: READ Burst Interrupt Example RL = 3, BL = 8, tCCD = 2 ................................................................. 69Figure 46: Data Input (WRITE) Timing ........................................................................................................... 70Figure 47: Burst WRITE WL = 1, BL = 4 ......................................................................................................... 70Figure 48: Burst WRITE Followed by Burst READ RL = 3, WL = 1, BL = 4 ......................................................... 71Figure 49: Seamless Burst WRITE WL = 1, BL = 4, tCCD = 2 ............................................................................ 71Figure 50: WRITE Burst Interrupt Timing WL = 1, BL = 8, tCCD = 2 ................................................................ 72




Figure 51: Burst WRITE Truncated by BST WL = 1, BL = 16 ............................................................................ 73Figure 52: Burst READ Truncated by BST RL = 3, BL = 16 ............................................................................... 74Figure 53: Data Mask Timing ......................................................................................................................... 74Figure 54: Write Data Mask Second Data Bit Masked .................................................................................... 75Figure 55: READ Burst Followed by PRECHARGE RL = 3, BL = 8, RU(tRTP(MIN)/tCK) = 2 ................................ 76Figure 56: READ Burst Followed by PRECHARGE RL = 3, BL = 4, RU(tRTP(MIN)/tCK) = 3 ................................ 77Figure 57: WRITE Burst Followed by PRECHARGE WL = 1, BL = 4 .................................................................. 78Figure 58: READ Burst with Auto Precharge RL = 3, BL = 4, RU(tRTP(MIN)/tCK) = 2 ........................................ 79Figure 59: WRITE Burst with Auto Precharge WL = 1, BL = 4 .......................................................................... 80Figure 60: Regular Distributed Refresh Pattern ............................................................................................... 84Figure 61: Supported Transition from Repetitive REFRESH Burst .................................................................... 85Figure 62: Nonsupported Transition from Repetitive REFRESH Burst .............................................................. 86Figure 63: Recommended Self Refresh Entry and Exit ..................................................................................... 87Figure 64: tSRF Definition .............................................................................................................................. 88Figure 65: All-Bank REFRESH Operation ........................................................................................................ 88Figure 66: Per-Bank REFRESH Operation ....................................................................................................... 89Figure 67: SELF REFRESH Operation .............................................................................................................. 90Figure 68: MRR Timing RL = 3, tMRR = 2 ...................................................................................................... 92Figure 69: READ to MRR Timing RL = 3, tMRR = 2 ......................................................................................... 93Figure 70: Burst WRITE Followed by MRR RL = 3, WL = 1, BL = 4 ................................................................... 94Figure 71: Temperature Sensor Timing ........................................................................................................... 96Figure 72: MR32 and MR40 DQ Calibration Timing RL = 3, tMRR = 2 ............................................................. 97Figure 73: MODE REGISTER WRITE Timing RL = 3, tMRW = 5 ....................................................................... 98Figure 74: ZQ Timings .................................................................................................................................. 100Figure 75: Power-Down Entry and Exit Timing ............................................................................................... 102Figure 76: CKE Intensive Environment .......................................................................................................... 102Figure 77: REFRESH-to-REFRESH Timing in CKE Intensive Environments ..................................................... 102Figure 78: READ to Power-Down Entry .......................................................................................................... 103Figure 79: READ with Auto Precharge to Power-Down Entry ........................................................................... 104Figure 80: WRITE to Power-Down Entry ........................................................................................................ 105Figure 81: WRITE with Auto Precharge to Power-Down Entry ......................................................................... 106Figure 82: REFRESH Command to Power-Down Entry ................................................................................... 107Figure 83: ACTIVATE Command to Power-Down Entry .................................................................................. 107Figure 84: PRECHARGE Command to Power-Down Entry .............................................................................. 107Figure 85: MRR Command to Power-Down Entry .......................................................................................... 108Figure 86: MRW Command to Power-Down Entry ......................................................................................... 108Figure 87: Deep Power-Down Entry and Exit Timing ...................................................................................... 109Figure 88: Simplified Bus Interface State Diagram .......................................................................................... 111Figure 89: VREF DC Tolerance and VREF AC Noise Limits ................................................................................. 128Figure 90: LPDDR2-466 to LPDDR2-1066 Input Signal ................................................................................... 129Figure 91: LPDDR2-200 to LPDDR2-400 Input Signal ..................................................................................... 130Figure 92: Differential AC Swing Time and tDVAC .......................................................................................... 131Figure 93: Single-Ended Requirements for Differential Signals ....................................................................... 133Figure 94: VIX Definition ............................................................................................................................... 134Figure 95: Differential Input Slew Rate Definition for CK, CK#, DQS, and DQS# ............................................... 135Figure 96: Single-Ended Output Slew Rate Definition ..................................................................................... 136Figure 97: Differential Output Slew Rate Definition ........................................................................................ 138Figure 98: Overshoot and Undershoot Definition ........................................................................................... 139Figure 99: HSUL_12 Driver Output Reference Load for Timing and Slew Rate ................................................. 140Figure 100: Output Driver ............................................................................................................................. 141Figure 101: Output Impedance = 240 Ohms, I-V Curves After ZQRESET .......................................................... 144Figure 102: Output Impedance = 240 Ohms, I-V Curves After Calibration ........................................................ 145




Figure 103: Command Input Setup and Hold Timing ..................................................................................... 157Figure 104: Typical Slew Rate and tVAC tIS for CA and CS# Relative to Clock .................................................. 160Figure 105: Typical Slew Rate tIH for CA and CS# Relative to Clock ............................................................... 161Figure 106: Tangent Line tIS for CA and CS# Relative to Clock ...................................................................... 162Figure 107: Tangent Line tIH for CA and CS# Relative to Clock ..................................................................... 163Figure 108: Typical Slew Rate and tVAC tDS for DQ Relative to Strobe ........................................................... 167Figure 109: Typical Slew Rate tDH for DQ Relative to Strobe ......................................................................... 168Figure 110: Tangent Line tDS for DQ with Respect to Strobe ......................................................................... 169Figure 111: Tangent Line tDH for DQ with Respect to Strobe ........................................................................ 170




List of TablesTable 1: Key Timing Parameters ....................................................................................................................... 1Table 2: Single Channel S4 Configuration Addressing ........................................................................................ 2Table 3: Dual Channel S4 Configuration Addressing .......................................................................................... 2Table 4: Package Codes and Descriptions ......................................................................................................... 3Table 5: 256 Meg x 16 IDD Specifications ......................................................................................................... 13Table 6: 128 Meg x 32 IDD Specifications ......................................................................................................... 14Table 7: IDD6 Partial-Array Self Refresh Current ............................................................................................... 16Table 8: Ball/Pad Descriptions ....................................................................................................................... 45Table 9: Initialization Timing Parameters ....................................................................................................... 49Table 10: Power-Off Timing ............................................................................................................................ 50Table 11: Mode Register Assignments ............................................................................................................. 51Table 12: MR0 Device Information (MA[7:0] = 00h) ......................................................................................... 52Table 13: MR0 Op-Code Bit Definitions .......................................................................................................... 52Table 14: MR1 Device Feature 1 (MA[7:0] = 01h) .............................................................................................. 52Table 15: MR1 Op-Code Bit Definitions .......................................................................................................... 53Table 16: Burst Sequence by Burst Length (BL), Burst Type (BT), and Wrap Control (WC) ................................. 53Table 17: No-Wrap Restrictions ...................................................................................................................... 54Table 18: MR2 Device Feature 2 (MA[7:0] = 02h) .............................................................................................. 54Table 19: MR2 Op-Code Bit Definitions .......................................................................................................... 55Table 20: MR3 I/O Configuration 1 (MA[7:0] = 03h) ......................................................................................... 55Table 21: MR3 Op-Code Bit Definitions .......................................................................................................... 55Table 22: MR4 Device Temperature (MA[7:0] = 04h) ........................................................................................ 55Table 23: MR4 Op-Code Bit Definitions .......................................................................................................... 56Table 24: MR5 Basic Configuration 1 (MA[7:0] = 05h) ...................................................................................... 56Table 25: MR5 Op-Code Bit Definitions .......................................................................................................... 56Table 26: MR6 Basic Configuration 2 (MA[7:0] = 06h) ...................................................................................... 57Table 27: MR6 Op-Code Bit Definitions .......................................................................................................... 57Table 28: MR7 Basic Configuration 3 (MA[7:0] = 07h) ...................................................................................... 57Table 29: MR7 Op-Code Bit Definitions .......................................................................................................... 57Table 30: MR8 Basic Configuration 4 (MA[7:0] = 08h) ...................................................................................... 57Table 31: MR8 Op-Code Bit Definitions .......................................................................................................... 57Table 32: MR9 Test Mode (MA[7:0] = 09h) ....................................................................................................... 58Table 33: MR10 Calibration (MA[7:0] = 0Ah) ................................................................................................... 58Table 34: MR10 Op-Code Bit Definitions ........................................................................................................ 58Table 35: MR[11:15] Reserved (MA[7:0] = 0Bh0Fh) ......................................................................................... 59Table 36: MR16 PASR Bank Mask (MA[7:0] = 010h) .......................................................................................... 59Table 37: MR16 Op-Code Bit Definitions ........................................................................................................ 59Table 38: MR17 PASR Segment Mask (MA[7:0] = 011h) .................................................................................... 59Table 39: MR17 PASR Segment Mask Definitions ............................................................................................ 59Table 40: MR17 PASR Row Address Ranges in Masked Segments ...................................................................... 59Table 41: Reserved Mode Registers ................................................................................................................. 60Table 42: MR63 RESET (MA[7:0] = 3Fh) MRW Only ....................................................................................... 60Table 43: Bank Selection for PRECHARGE by Address Bits ............................................................................... 76Table 44: PRECHARGE and Auto Precharge Clarification ................................................................................. 80Table 45: REFRESH Command Scheduling Separation Requirements .............................................................. 82Table 46: Bank and Segment Masking Example ............................................................................................... 91Table 47: Temperature Sensor Definitions and Operating Conditions .............................................................. 95Table 48: Data Calibration Pattern Description ............................................................................................... 97Table 49: Truth Table for MRR and MRW ........................................................................................................ 98Table 50: Command Truth Table ................................................................................................................... 112




Table 51: CKE Truth Table ............................................................................................................................. 113Table 52: Current State Bank n to Command to Bank n Truth Table ................................................................ 114Table 53: Current State Bank n to Command to Bank m Truth Table ............................................................... 116Table 54: DM Truth Table .............................................................................................................................. 119Table 55: Absolute Maximum DC Ratings ...................................................................................................... 120Table 56: Input/Output Capacitance ............................................................................................................. 120Table 57: Switching for CA Input Signals ........................................................................................................ 121Table 58: Switching for IDD4R ......................................................................................................................... 122Table 59: Switching for IDD4W ........................................................................................................................ 122Table 60: IDD Specification Parameters and Operating Conditions .................................................................. 123Table 61: Recommended DC Operating Conditions ....................................................................................... 125Table 62: Input Leakage Current ................................................................................................................... 126Table 63: Operating Temperature Range ........................................................................................................ 126Table 64: Single-Ended AC and DC Input Levels for CA and CS# Inputs ........................................................... 127Table 65: Single-Ended AC and DC Input Levels for CKE ................................................................................ 127Table 66: Single-Ended AC and DC Input Levels for DQ and DM ..................................................................... 127Table 67: Differential AC and DC Input Levels ................................................................................................ 131Table 68: CK/CK# and DQS/DQS# Time Requirements Before Ringback (tDVAC) ............................................ 132Table 69: Single-Ended Levels for CK, CK#, DQS, DQS# .................................................................................. 133Table 70: Crosspoint Voltage for Differential Input Signals (CK, CK#, DQS, DQS#) ........................................... 134Table 71: Differential Input Slew Rate Definition ............................................................................................ 135Table 72: Single-Ended AC and DC Output Levels .......................................................................................... 135Table 73: Differential AC and DC Output Levels ............................................................................................. 136Table 74: Single-Ended Output Slew Rate Definition ...................................................................................... 136Table 75: Single-Ended Output Slew Rate ...................................................................................................... 136Table 76: Differential Output Slew Rate Definition ......................................................................................... 137Table 77: Differential Output Slew Rate ......................................................................................................... 138Table 78: AC Overshoot/Undershoot Specification ......................................................................................... 138Table 79: Output Driver DC Electrical Characteristics with ZQ Calibration ...................................................... 141Table 80: Output Driver Sensitivity Definition ................................................................................................ 142Table 81: Output Driver Temperature and Voltage Sensitivity ......................................................................... 142Table 82: Output Driver DC Electrical Characteristics Without ZQ Calibration ................................................ 142Table 83: I-V Curves ..................................................................................................................................... 143Table 84: Definitions and Calculations .......................................................................................................... 146Table 85: tCK(abs), tCH(abs), and tCL(abs) Definitions ................................................................................... 147Table 86: Refresh Requirement Parameters (Per Density) ............................................................................... 150Table 87: AC Timing ..................................................................................................................................... 151Table 88: CA and CS# Setup and Hold Base Values (>400 MHz, 1 V/ns Slew Rate) ............................................ 158Table 89: CA and CS# Setup and Hold Base Values ( VIH(AC) and < VIL(AC) ....................................................... 159Table 93: Data Setup and Hold Base Values (>400 MHz, 1 V/ns Slew Rate) ....................................................... 164Table 94: Data Setup and Hold Base Values ( VIH(AC) or < VIL(AC) ......................................................... 166




General DescriptionThe 4Gb Mobile Low-Power DDR2 SDRAM (LPDDR2) is a high-speed CMOS, dynamicrandom-access memory containing 4,294,967,296-bits. The LPDDR2-S4 device is inter-nally configured as an eight-bank DRAM. Each of the x16s 536,870,912-bit banks is or-ganized as 16,384 rows by 2048 columns by 16 bits. Each of the x32s 536,870,912-bitbanks is organized as 16,384 rows by 1024 columns by 32 bits.

General Notes

Throughout the data sheet, figures and text refer to DQs as DQ. DQ should be inter-preted as any or all DQ collectively, unless specifically stated otherwise.

DQS and CK should be interpreted as DQS, DQS# and CK, CK# respectively, unlessspecifically stated otherwise. BA includes all BA pins used for a given density.

In timing diagrams, CMD is used as an indicator only. Actual signals occur on CA[9:0].

VREF indicates VREFCA and VREFDQ.

Complete functionality may be described throughout the entire document. Any page ordiagram may have been simplified to convey a topic and may not be inclusive of all re-quirements.

Any specific requirement takes precedence over a general statement.

Any functionality not specifically stated herein is considered undefined, illegal, is notsupported, and will result in unknown operation.

4Gb: x16, x32 Mobile LPDDR2 SDRAM S4General Description



IDD Specifications

Table 5: 256 Meg x 16 IDD Specifications

VDD2, VDDQ, VDDCA = 1.141.30V; VDD1 = 1.701.95V

Parameter Supply

Speed Grade

Unit-18 -25 -3

IDD01 VDD1 15 15 15 mA

IDD02 VDD2 70 70 70

IDD0,in VDDCA + VDDQ 7 6 6

IDD2P1 VDD1 600 600 600 AIDD2P2 VDD2 800 800 800

IDD2P,in VDDCA + VDDQ 50 50 50

IDD2PS1 VDD1 600 600 600 AIDD2PS2 VDD2 800 800 800

IDD2PS,in VDDCA + VDDQ 50 50 50

IDD2N1 VDD1 2 2 2 mA

IDD2N2 VDD2 30 30 30

IDD2N,in VDDCA + VDDQ 7 6 6

IDD2NS1 VDD1 1.7 1.7 1.7 mA

IDD2NS2 VDD2 27 27 27

IDD2NS,in VDDCA + VDDQ 6 6 6

IDD3P1 VDD1 1200 1200 1200 A

IDD3P2 VDD2 8 8 8 mA

IDD3P,in VDDCA + VDDQ 150 150 150 A

IDD3PS1 VDD1 1200 1200 1200 A

IDD3PS2 VDD2 8 8 8 mA

IDD3PS,in VDDCA + VDDQ 150 150 150 A

IDD3N1 VDD1 2.5 2.5 2.5 mA

IDD3N2 VDD2 30 30 30


IDD3NS1 VDD1 2 2 2 mA

IDD3NS2 VDD2 27 27 27


IDD4R1 VDD1 3 3 3 mA

IDD4R2 VDD2 220 194 178

IDD4R,in VDDCA 6 6 6

IDD4W1 VDD1 10 10 10 mA

IDD4W2 VDD2 190 185 170

IDD4W,in VDDCA + VDDQ 25 25 25

4Gb: x16, x32 Mobile LPDDR2 SDRAM S4IDD Specifications



Table 5: 256 Meg x 16 IDD Specifications (Continued)


Parameter Supply

Speed Grade

Unit-18 -25 -3

IDD51 VDD1 40 40 40 mA

IDD52 VDD2 150 150 150


IDD5PB1 VDD1 5 5 5 mA

IDD5PB2 VDD2 50 50 50

IDD5PB,in VDDCA + VDDQ 8 8 8

IDD5PBET1 VDD1 10.5 10.5 10.5 mA

IDD5PBET2 VDD2 80 80 80

IDD5PB,ETin VDDCA + VDDQ 8 8 8

IDD5AB1 VDD1 5 5 5 mA

IDD5AB2 VDD2 50 50 50

IDD5AB,in VDDCA + VDDQ 8 8 8

IDD5ABET1 VDD1 10.5 10.5 10.5 mA

IDD5ABET2 VDD2 80 80 80

IDD5AB,ETin VDDCA + VDDQ 8 8 8

IDD61 VDD1 1000 1000 1000 A

IDD62 VDD2 3200 3200 3200


IDD6ET1 VDD1 3100 3100 3100 A

IDD6ET2 VDD2 13.7 13.7 13.7 mA

IDD6,ETin VDDCA + VDDQ 90 90 90 A

IDD81 VDD1 25 25 25 A

IDD82 VDD2 100 100 100


Table 6: 128 Meg x 32 IDD Specifications


Parameter Supply

Speed Grade

Unit-18 -25 -3

IDD01 VDD1 15 15 15

mAIDD02 VDD2 70 70 70


IDD2P1 VDD1 600 600 600

AIDD2P2 VDD2 800 800 800IDD2P,in VDDCA + VDDQ 50 50 50






Parameter Supply

Speed Grade

Unit-18 -25 -3

IDD2PS1 VDD1 600 600 600

AIDD2PS2 VDD2 800 800 800IDD2PS,in VDDCA + VDDQ 50 50 50

IDD2N1 VDD1 2 2 2 mA

IDD2N2 VDD2 30 30 30mA


IDD2NS1 VDD1 1.7 1.7 1.7

mAIDD2NS2 VDD2 27 27 27


IDD3P1 VDD1 1200 1200 1200 AIDD3P2 VDD2 8 8 8 mA

IDD3P,in VDDCA + VDDQ 150 150 150 AIDD3PS1 VDD1 1200 1200 1200 AIDD3PS2 VDD2 8 8 8 mA

IDD3PS,in VDDCA + VDDQ 150 150 150 AIDD3N1 VDD1 2.5 2.5 2.5 mA

IDD3N2 VDD2 30 30 30mA


IDD3NS1 VDD1 2 2 2

mAIDD3NS2 VDD2 27 27 27


IDD4R1 VDD1 3 3 3

mAIDD4R2 VDD2 220 194 178

IDD4R,in VDDCA 6 6 6

IDD4W1 VDD1 10 10 10

mAIDD4W2 VDD2 190 185 170

IDD4W,in VDDCA + VDDQ 25 25 25

IDD51 VDD1 40 40 40

mAIDD52 VDD2 150 150 150


IDD5PB1 VDD1 5 5 5

mAIDD5PB2 VDD2 50 50 50

IDD5PB,in VDDCA + VDDQ 8 8 8

IDD5PBET1 VDD1 10.5 10.5 10.5

mAIDD5PBET2 VDD2 80 80 80

IDD5PB,ETin VDDCA + VDDQ 8 8 8






Parameter Supply

Speed Grade

Unit-18 -25 -3

IDDAB1 VDD1 5 5 5

mAIDD5AB2 VDD2 50 50 50

IDD5AB,in VDDCA + VDDQ 8 8 8

IDDABET1 VDD1 10.5 10.5 10.5

mAIDD5ABET2 VDD2 80 80 80

IDD5AB,ETin VDDCA + VDDQ 8 8 8

IDD61 VDD1 1000 1000 1000

AIDD62 VDD2 3200 3200 3200IDD6,in VDDCA + VDDQ 50 50 50

IDD6ET1 VDD1 3100 3100 3100 AIDD6ET2 VDD2 13.7 13.7 13.7 mA

IDD6,ETin VDDCA + VDDQ 90 90 90 A

IDD81 VDD1 25 25 25

AIDD82 VDD2 100 100 100IDD8,in VDDCA + VDDQ 100 100 100

Table 7: IDD6 Partial-Array Self Refresh Current

VDD2, VDDQ, VDDCA = 1.141.30V; VDD1 = 1.701.95VPASR Supply Value (30C to +85C) Value (+85C to +105C) Unit

Full array VDD1 1000 3100 AVDD2 3.2 13.7 mA

VDDi 50 90 A

1/2 array VDD1 950 2200

VDD2 2700 7300

VDDi 50 90

1/4 array VDD1 900 1600

VDD2 2400 4300

VDDi 50 90

1/8 array VDD1 850 1300

VDD2 2000 2800

VDDi 50 90

Note: 1. LPDDR2-S4 SDRAM devices support both bank masking and segment masking. IDD6 PASRcurrents are measured using bank masking only.




Figure 2: VDD1Typical Self Refresh Current vs. Temperature

0

200

400

600

800

1000

1200

1400

1600

1800

2000

-40 -20 0 25 35 45 65 80 85 95 110

IDD6 1/8 VDD1 (a)

IDD6 1/4 VDD1 (a)

IDD6 1/2 VDD1 (a)

IDD6 Full VDD1 (a)

Figure 3: VDD2 Typical Self Refresh Current vs. Temperature

0

1000

2000

3000

4000

5000

6000

7000

8000

9000

10000

-40 -20 0 25 35 45 65 80 85 95 110

IDD6 1/8 VDD2 (a)

IDD6 1/4 VDD2 (a)

IDD6 1/2 VDD2 (a)

IDD6 Full VDD2 (a)




Package Block Diagrams

Figure 4: Single Rank, Single Channel Package Block Diagram

LPDDR2

Die 0

CS0#

CKE0

CK

CK#

DM

CA[9:0]

DQ, DQS

ZQ

RZQ

VDD1 VDD2 VDDQ VDDCA VSS

VREFDQVREFCA

Figure 5: Dual Rank, Single Channel Package Block Diagram

LPDDR2

Die 0

LPDDR2

Die 1

CS1#

CKE1

CS0#

CKE0

CK

CK#

DM

CA[9:0]

DQ[31:0], DQS

ZQ0

RZQ


VREFDQVREFCA

Note: 1. For the 168-ball JEDEC PoP ballout employing only a single ZQ connection, the RZQ re-sistor is connected to ZQ.

4Gb: x16, x32 Mobile LPDDR2 SDRAM S4Package Block Diagrams



Figure 6: Dual Rank, Single Channel (3 Die) Package Block Diagram

DQ[31:0], DQS[3:0]/DQS[3:0]#

CKE1

CS1#

LPDDR2

Die 1

LPDDR2

Die 2

LPDDR2

Die 0

x32

VDD1 VDD2 VDDQVDDCA VSS

CS0#

CKE0

CK

CK#

DM

CA[9:0]

RZQ1

ZQ1

ZQ0RZQ0

VREFDQVREFCA

x16 x16DQ[15:0] DQ[31:16]




Figure 7: Single Rank, Dual Channel Package Block Diagram

DQ[31:0], DQS

CKE0

CS0#

LPDDR2

Die 1

LPDDR2

Die 0

CS0#

CKE0

CK#

CK

DM

CA[9:0]

CA[9:0]

DM

CK

CK#

DQ[31:0], DQS

ZQ0

RZQ

ZQ0

RZQ

VDD1 VDDQ VDDCA VSS

VREFDQ(b)VREFCA(b)

Channel B

Channel A

VREFDQ(a)VREFCA(a)

VDD2




Figure 8: Dual Rank, Dual Channel Package Block Diagram

DQ[31:0], DQS

CKE0

CS0#

LPDDR2

Die 2

LPDDR2

Die 3

LPDDR2

Die 0

LPDDR2

Die 1

CS1#

CKE1

CS0#

CKE0

CK

CK#

DM

CA[9:0]

CA[9:0]

DM

CK

CK#

DQ[31:0], DQS

ZQ0

RZQ

ZQ0

RZQ


VREFDQ(b)VREFCA(b)

VREFDQ(a)VREFCA(a)

Channel B

Channel A

CKE1

CS1#




Figure 9: Dual Rank, Dual Channel (3 Die) Package Block Diagram

DQ[31:0], DQS

CKE0

CS0#

LPDDR2

Die 2

LPDDR2

Die 0

LPDDR2

Die 1

CS1#

CKE1

CS0#

CKE0

CK

CK#

DM

CA[9:0]

CA[9:0]

DM

CK

CK#

DQ[31:0], DQS

ZQ0

RZQ0

ZQ0

RZQ0


VREFDQ(a)VREFCA(a)

VREFDQ(b)VREFCA(b)

Channel B

Channel A




Figure 10: Dual Rank, Single Channel (4 Die) Package Block Diagram

DQ[15:0], DQS0/DQS0#, DQS1/DQS1#

CKE1

CS1#

LPDDR2

Die 2

LPDDR2

Die 3

LPDDR2

Die 0

LPDDR2

Die 1


CS0#

CKE0

CK

CK#

DM

CA[9:0]DQ[31:16], DQS2/DQS2#, DQS3/DQS3#

RZQ1

ZQ1

ZQ0

RZQ0

VREFDQVREFCA




Package Dimensions

Figure 11: 134-Ball FBGA 10mm x 11.5mm Single-Die (Package Code GU)

Seating plane

0.08 A

Ball A1 ID(covered by SR)

11.5 0.1

10 0.1

10.4 CTR

5.85 CTR

Ball A1 ID

0.6 0.1

0.22 MIN

ABCDEFGHJKLMNPRTU

12345678910

134X 0.36Dimensions applyto solder balls post-reflow on 0.30 SMDOSP ball pads.

0.65 TYP0.65 TYP

A

Note: 1. All dimensions are in millimeters.

4Gb: x16, x32 Mobile LPDDR2 SDRAM S4Package Dimensions



Figure 12: 134-Ball FBGA 10mm x 11.5mm Dual-Die (Package Code GV)

Seating plane

0.08 A


11.5 0.1

10 0.1

10.4 CTR

5.85 CTR

Ball A1 ID

0.75 0.1

0.22 MIN

ABCDEFGHJKLMNPRTU

12345678910

134X 0.36Dimensions applyto solder balls post-reflow on 0.30SMD OSP ball pads.

0.65 TYP0.65 TYP

A





Figure 13: 168-Ball FBGA 12mm x 12mm Single-Die (Package Code LF)

Seating plane

0.08 A

Ball A1 ID

0.237 MIN

0.65 0.1

11 CTR

12 0.1

0.5 TYP

11 CTR

12 0.1

0.5 TYP

ABCDEFGHJKLMNPRTUVWYAAABAC

23 21 19 17 15 13 11 9 7 5 3 122 20 18 16 14 12 10 8 6 4 2

Ball A1 ID

168X 0.355Dimensions applyto solder balls post-reflow on 0.28 SMDball pads.

A





Figure 14: 168-Ball FBGA 12mm x 12mm Dual-Die (Package Code LG)

Seating plane

0.08 A

Ball A1 ID

0.24 MIN

0.7 0.1

11 CTR

12 0.1

0.5 TYP

11 CTR

12 0.1

0.5 TYP

Ball A1 ID

168X 0.355Dimensionsapply to solderballs post-reflowon 0.28 SMDball pads.

ABCDEFGHJKLMNPRTUVWYAAABAC

23 21 19 17 15 13 11 9 7 5 3 122 20 18 16 14 12 10 8 6 4 2

A





Figure 15: 216-Ball FBGA 12mm x 12mm (Package Codes LK, LL)

ABCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAHAJ

Seating plane

0.08 A

Ball A1 ID

0.13 MIN

0.7 0.1

11.2 CTR

12 0.1

0.4 TYP

11.2 CTR

12 0.1

0.4 TYP



1246810121416182022242628

357911131517192123252729

A





Figure 16: 216-Ball FBGA 12mm x 12mm (Package Code LM)


Seating plane

0.08 A

Ball A1 ID

0.13 MIN

0.9 0.1

11.2 CTR

12 0.1

0.4 TYP

11.2 CTR

12 0.1

0.4 TYP



1246810121416182022242628

357911131517192123252729

A





Figure 17: 216-Ball FBGA 12mm x 12mm (Package Code LH)

Seating plane

0.08 A

Ball A1 index

0.13 MIN

0.55 0.1

11.2 CTR

12 0.1

0.4 TYP

11.2 CTR

12 0.1

0.4 TYP

1

Ball A1 index



246810121416182022242628357911131517192123252729

A





Figure 18: 216-Ball FBGA 12mm x 12mm (Package Code LP)


Seating plane

0.08 AA

Ball A1 ID

0.132 MIN

0.72 0.1

11.2 CTR

12 0.1

0.4 TYP

11.2 CTR

12 0.1

0.4 TYP

Ball A1 ID

216X 0.261Dimensionsapply to solderballs post-reflowon 0.24 SMDball pads. 1246810121416182022242628 357911131517192123252729





Figure 19: 220-Ball FBGA 14mm x 14mm Dual-Die (Package Code MP)

Seating plane

0.08 A

Ball A1 ID

0.215 MIN

0.7 0.1

13.0 CTR

14 0.1

0.5 TYP

13.0 CTR

14 0.1

0.5 TYP



ABCDEFGHJKLMNPRTUVWYAAABACADAEAFAG

13 11 9 7 5 3 114 12 10 8 6 4 2

1516

1718

1920

2122

2324

2526

27

A





Figure 20: 220-Ball FBGA 14mm x 14mm Quad-Die (Package Code LD)

Seating plane

0.08 A

Ball A1 ID

0.215 MIN

0.9 0.1

13.0 CTR

14 0.1

0.5 TYP

13.0 CTR

14 0.1

0.5 TYP




13 11 9 7 5 3 114 12 10 8 6 4 2

1516

1718

1920

2122

2324

2526

27

A





Figure 21: 240-Ball FBGA 14mm x 14mm Dual-Die (Package Code MC)

Pin A1 index

Seatingplane

0.08 A

A

0.7 0.1

Pin A1 index(covered by SR)

0.5 TYP

0.5 TYP

13.0 CTR

Dimensions applyto solder ballspost-reflow on0.27 SMD OSPball pads.

240X 0.34

14 0.1

0.215 MIN

13.0CTR

14 0.1

27 25 23 21 19 17 15 13 11 9 7 5 3 1 26 24 22 20 18 16 14 12 10 8 6 4 2






Figure 22: 253-Ball FBGA 11mm x 11mm Dual-Die (Package Code EU)

Seating plane

0.08 A


11 0.1

11 0.1

8 CTR

8 CTR

Ball A1 ID

0.8 0.1

0.18 MIN

1

253X 0.309Dimensions applyto solder balls post-reflow on 0.27SMD OSP ball pads.

0.5 TYP 0.5 TYP

ABCDEFGHJKLMNPRTU

23

45

67

89

1011

1213

1415

1617

A





Figure 23: 253-Ball FBGA 11mm x 11mm Quad-Die (Package Code EV)

Seating plane

0.08 A


11 0.1

11 0.1

8 CTR

8 CTR

Ball A1 ID

1.1 0.1

0.18 MIN

253X 0.31Dimensionsapply to solderballs post-reflowon 0.27 SMD OSPball pads.

0.5 TYP 0.5 TYP

A

1

ABCDEFGHJKLMNPRTU

23

45

67

89

1011

1213

1415

1617





Ball Assignments and Descriptions

Figure 24: 134-Ball FBGA (x16)

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

Top View (ball down)

1

DNU

DNU

VDD1

VSS

VSSCA

VDDCA

VDD2

VDDCA

VSSCA

CKE0

CS0#

CA4

VSSCA

VSS

VDD1

DNU

DNU

1

2

DNU

NC

VSS

VDD2

CA9

CA6

CA5

VSS

NC

CKE1

CS1#

CA3

VDDCA

VDD2

VSS

NC

DNU

2

4

4

3

NC

ZQ1

ZQ0

CA8

CA7

VREFCA

CK#

CK

RFU

RFU

CA2

CA1

CA0

NC

NC

3

5

VDD2

VSS

VDDQ

RFU

VSSQ

DQS1#

DM1

VSSQ

DM0

DQS0#

VSSQ

RFU

VDDQ

VSS

VDD2

5

6

VDD1

VSSQ

RFU

RFU

DQ11

DQS1

VDDQ

VDDQ

VDDQ

DQS0

DQ4

RFU

RFU

VSSQ

VDD1

6

7

RFU

VDDQ

RFU

RFU

DQ13

DQ10

VDD2

DQ5

DQ2

RFU

RFU

VDDQ

RFU

7

8

RFU

RFU

RFU

DQ15

DQ14

DQ9

VSS

DQ6

DQ1

DQ0

RFU

RFU

RFU

8

9

DNU

RFU

VSSQ

RFU

VDDQ

DQ12

DQ8

VREFDQ

DQ7

DQ3

VDDQ

RFU

VSSQ

RFU

DNU

9

10

DNU

DNU

VDDQ

VSSQ

VSSQ

VDDQ

VSSQ

VSSQ

VDDQ

VSSQ

VSSQ

VDDQ

DNU

DNU

10

4Gb: x16, x32 Mobile LPDDR2 SDRAM S4Ball Assignments and Descriptions



Figure 25: 134-Ball FBGA (x32)

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U


1

DNU

DNU

VDD1

VSS

VSSCA

VDDCA

VDD2

VDDCA

VSSCA

CKE0

CS0#

CA4

VSSCA

VSS

VDD1

DNU

DNU

1

2

DNU

NC

VSS

VDD2

CA9

CA6

CA5

VSS

NC

CKE1

CS1#

CA3

VDDCA

VDD2

VSS

NC

DNU

2

4

4

3

NC

ZQ1

ZQ0

CA8

CA7

VREFCA

CK#

CK

RFU

RFU

CA2

CA1

CA0

NC

NC

3

5

VDD2

VSS

VDDQ

DQ28

VSSQ

DQS1#

DM1

VSSQ

DM0

DQS0#

VSSQ

DQ19

VDDQ

VSS

VDD2

5

6

VDD1

VSSQ

DQ30

DQ24

DQ11

DQS1

VDDQ

VDDQ

VDDQ

DQS0

DQ4

DQ23

DQ17

VSSQ

VDD1

6

7

DQ31

VDDQ

DQ27

DM3

DQ13

DQ10

VDD2

DQ5

DQ2

DM2

DQ20

VDDQ

DQ16

7

8

DQ29

DQ25

DQS3

DQ15

DQ14

DQ9

VSS

DQ6

DQ1

DQ0

DQS2

DQ22

DQ18

8

9

DNU

DQ26

VSSQ

DQS3#

VDDQ

DQ12

DQ8

VREFDQ

DQ7

DQ3

VDDQ

DQS2#

VSSQ

DQ21

DNU

9

10

DNU

DNU

VDDQ

VSSQ

VSSQ

VDDQ

VSSQ

VSSQ

VDDQ

VSSQ

VSSQ

VDDQ

DNU

DNU

10




Figure 26: 168-Ball FBGA 12mm x 12mm

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC


1

DNU

DNU

VSS

NC

NC

(NC) 2

NC

NC

(NC) 2

NC

NC

NC

NC

ZQ

VSS

CA9

CA7

VSSCA

CA5

CK#

VSS

DNU

DNU

1

2

DNU

DNU

VDD2

NC

NC

NC

NC

NC

NC

NC

NC

VSS

VDD1

VREFCA

VDD2

CA8

VDDCA

CA6

VDDCA

CK

VDD2

DNU

DNU

2

4

NC

NC

CS1#

CKE1

4

3

NC

VDD1

CS0#

CKE0

3

5

NC

NC

VDD1

VSS

5

6

(NC) 2

NC

CA1

CA0

6

7

NC

NC

VSSCA

CA2

7

8

NC

NC

CA3

VDDCA

8

9

(NC) 2

NC

CA4

VSS 1

9

11

VDD1

VDD2

VSS

NC

11

13

DQ30

VDDQ

VDDQ

DQ17

13

14

DQ29

DQ28

DQ18

DQ19

14

15

VSSQ

DQ27

DQ20

VSSQ

15

16

DQ26

VDDQ

VDDQ

DQ21

16

22

DNU

DNU

DQ15

VDDQ

DQ12

DQ11

VDDQ

DQ8

DQS1

VDDQ

VDD2

VREFDQ

VDD1

DQS#0

VDDQ

DQ6

DQ5

VDDQ

DQ2

DQ1

VDDQ

DNU

DNU

22

23

DNU

DNU

VSSQ

DQ14

DQ13

VSSQ

DQ10

DQ9

VSSQ

DQS#1

DM1

VSS

DM0

VSSQ

DQS0

DQ7

VSSQ

DQ4

DQ3

VSSQ

DQ0

DNU

DNU

23

10

NC

VSS

VDD2

(NC) 2

10

12

VSSQ

DQ31

DQ16

VSSQ

12

18

VSSQ

DQS3

DQS2

VSSQ

18

19

DQS#3

VDDQ

VDDQ

DQS#2

19

20

VDD1

DM3

DM2

VDD1

20

21

VSS

VDD2

VDD2

VSS

21

17

DQ25

DQ24

DQ22

DQ23

17

Supply GroundLPDDR2

Notes: 1. Ball AC9 may be VSS or left unconnected.2. Balls labeled NC = no connect; however, they can be connected together internally.




Figure 27: 216-Ball 2-Channel FBGA 12mm x 12mm

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DQS#2

DM2

DQ1

DQ2

VSS

VDD1

VDD2

VDDQ

DQ4

DQ6

VDDQ

DQS0

DM0

VDDQ

DQS# 1

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DQ10

VSSQ

DNU

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2

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NC

DQ16

VDDQ

DQ19

DQ20

VDDQ

DQ23

VDDQ

DQS2

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VSSQ

VDD1

VSS

VREFDQ

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DQ3

VSSQ

DQ5

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DQS#0

VSSQ

DM1

DQS1

VSSQ

VDDQ

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VSS

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DQ30

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VSSQ

DQ14

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DQS#3

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VSSQ

CK#

CK

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DQ12

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ZQ

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VSSCA

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CS1#

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VDDQ

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VDDCA

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DQ2

CA1

CA0

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NC

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DQ1

VSSQ

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DQS2

VSSQ

VDDQ

DQ20

DQ19

VDDQ

DQ16

VDD2

VSS

VDDCA

VREFCA

VSSCA

CA4

CS0#

VSSCA

CK

VDDCA

CA7

CA8

VSSCA

VDD2

VDD1

VSS

28

GroundSupplyChannel BChannel A




Figure 28: 216-Ball 1-Channel (B) FBGA 12mm x 12mm

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VDD1

VDD2

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DQ6

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DQS0

DM0

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DQS# 1

DQ8

DQ9

DQ10

VSSQ

DNU

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2

VSS

NC

DQ16

VDDQ

DQ19

DQ20

VDDQ

DQ23

VDDQ

DQS2

DQ0

VSSQ

VDD1

VSS

VREFDQ

VDD2

DQ3

VSSQ

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DQ7

DQS#0

VSSQ

DM1

DQS1

VSSQ

VDDQ

DQ11

VDD1

VSS

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4

NC

NC

DQ13

VDDQ

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VDD2

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VDD2

DQ12

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NC

VSSQ

DQ14

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7

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Text of 4Gb: x16, x32 Mobile LPDDR2 SDRAM S4