DDR4 SDRAMMT40A1G4MT40A512M8MT40A256M16

Features VDD = VDDQ = 1.2V 60mV VPP = 2.5V, 125mV/+250mV On-die, internal, adjustable VREFDQ generation 1.2V pseudo open-drain I/O TC of 0C to 95C

64ms, 8192-cycle refresh at 0C to 85C 32ms at 85C to 95C

16 internal banks (x4, x8): 4 groups of 4 banks each 8 internal banks (x16): 2 groups of 4 banks each 8n-bit prefetch architecture Programmable data strobe preambles Data strobe preamble training Command/Address latency (CAL) Multipurpose register READ and WRITE capability Write and read leveling Self refresh mode Low-power auto self refresh (LPASR) Temperature controlled refresh (TCR) Fine granularity refresh Self refresh abort Maximum power saving Output driver calibration Nominal, park, and dynamic on-die termination

(ODT) Data bus inversion (DBI) for data bus Command/Address (CA) parity

Databus write cyclic redundancy check (CRC) Per-DRAM addressability Connectivity test (x16) Post package repair (PPR) and soft post package re-

pair (sPPR) modes JEDEC JESD-79-4 compliant

Options1 Marking Configuration

1 Gig x 4 1G4 512 Meg x 8 512M8 256 Meg x 16 256M162

FBGA package (Pb-free) 78-ball (9mm x 11.5mm) x4, x8 HX 96-ball (9mm x 14mm) x16 HA

Timing cycle time 0.833ns @ CL = 16 (DDR4-2400) -083E3

0.833ns @ CL = 17 (DDR4-2400) -083 0.937ns @ CL = 14 (DDR4-2133) -093F3

0.937ns @ CL = 15 (DDR4-2133) -093E 1.071ns @ CL = 13 (DDR4-1866) -107E

Operating temperature Commercial (0 TC 95C) None Revision :A

Notes: 1. Not all options listed can be combined todefine an offered product. Use the partcatalog search on http://www.micron.comfor available offerings.

2. Not available on Rev. A.3. Restricted and limited availability.

Table 1: Key Timing Parameters

Speed Grade Data Rate (MT/s) Target tRCD-tRP-CL tRCD (ns) tRP (ns) CL (ns)

-083E1, 2, 3, 4 2400 16-16-16 13.32 13.32 13.32

-093F1, 2, 3 2133 14-14-14 13.13 13.13 13.13

-093E1, 2 2133 15-15-15 14.06 14.06 14.06

-107E1 1866 13-13-13 13.92 13.92 13.92

Notes: 1. Backward compatible to 1600, CL = 11 (-125E).2. Backward compatible to 1866, CL = 13 (-107E).3. Backward compatible to 2133, CL = 15 (-2133).

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4. Backward compatible to 2133, CL = 14 (-2133).

Table 2: Addressing

Parameter 1024 Meg x 4 512 Meg x 8 256 Meg x 16

Number of bank groups 4 4 2

Bank group address BG[1:0] BG[1:0] BG0

Bank count per group 4 4 4

Bank address in bank group BA[1:0] BA[1:0] BA[1:0]

Row addressing 64K (A[15:0]) 32K (A[14:0]) 32K (A[14:0])

Column addressing 1K (A[9:0]) 1K (A[9:0]) 1K (A[9:0])

Page size1 512B / 1KB2 1KB 2KB

Notes: 1. Page size is per bank, calculated as follows:Page size = 2COLBITS ORG/8, where COLBIT = the number of column address bits and ORG = the number ofDQ bits.

2. Die revision dependant.

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ContentsGeneral Notes and Description ....................................................................................................................... 16

Description ................................................................................................................................................ 16General Notes ............................................................................................................................................ 16Definitions of the Device-Pin Signal Level ................................................................................................... 17Definitions of the Bus Signal Level ............................................................................................................... 17

Ball Assignments ............................................................................................................................................ 18Ball Descriptions ............................................................................................................................................ 20Package Dimensions ....................................................................................................................................... 23State Diagram ................................................................................................................................................ 25Functional Description ................................................................................................................................... 27RESET and Initialization Procedure ................................................................................................................. 28

Power-Up and Initialization Sequence ......................................................................................................... 28RESET Initialization with Stable Power Sequence ......................................................................................... 31Uncontrolled Power-Down Sequence .......................................................................................................... 32

Programming Mode Registers ......................................................................................................................... 32Mode Register 0 .............................................................................................................................................. 35

Burst Length, Type, and Order ..................................................................................................................... 36CAS Latency ............................................................................................................................................... 37Test Mode .................................................................................................................................................. 38Write Recovery(WR)/READ-to-PRECHARGE ............................................................................................... 38DLL RESET ................................................................................................................................................. 38

Mode Register 1 .............................................................................................................................................. 39DLL Enable/DLL Disable ............................................................................................................................ 40Output Driver Impedance Control ............................................................................................................... 41ODT RTT(NOM) Values .................................................................................................................................. 41Additive Latency ......................................................................................................................................... 41Write Leveling ............................................................................................................................................ 41Output Disable ........................................................................................................................................... 42Termination Data Strobe ............................................................................................................................. 42

Mode Register 2 .............................................................................................................................................. 43CAS WRITE Latency .................................................................................................................................... 45Low-Power Auto Self Refresh ....................................................................................................................... 45Dynamic ODT ............................................................................................................................................ 45Write Cyclic Redundancy Check Data Bus .................................................................................................... 45Target Row Refresh Mode ............................................................................................................................ 45

Mode Register 3 .............................................................................................................................................. 46Multipurpose Register ................................................................................................................................ 47WRITE Command Latency When CRC/DM is Enabled ................................................................................. 48Fine Granularity Refresh Mode .................................................................................................................... 48Temperature Sensor Status ......................................................................................................................... 48Per-DRAM Addressability ........................................................................................................................... 48Gear-Down Mode ....................................................................................................................................... 48

Mode Register 4 .............................................................................................................................................. 49Post Package Repair Mode .......................................................................................................................... 50Soft Post Package Repair Mode .................................................................................................................... 50WRITE Preamble ........................................................................................................................................ 51READ Preamble .......................................................................................................................................... 51READ Preamble Training ............................................................................................................................ 51Temperature-Controlled Refresh ................................................................................................................. 51Command Address Latency ........................................................................................................................ 51

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Internal VREF Monitor ................................................................................................................................. 51Maximum Power Savings Mode ................................................................................................................... 51

Mode Register 5 .............................................................................................................................................. 53Data Bus Inversion ..................................................................................................................................... 54Data Mask .................................................................................................................................................. 55CA Parity Persistent Error Mode .................................................................................................................. 55ODT Input Buffer for Power-Down .............................................................................................................. 55CA Parity Error Status ................................................................................................................................. 55CRC Error Status ......................................................................................................................................... 55CA Parity Latency Mode .............................................................................................................................. 55

Mode Register 6 .............................................................................................................................................. 56tCCD_L Programming ................................................................................................................................. 57VREFDQ Calibration Enable .......................................................................................................................... 57VREFDQ Calibration Range ........................................................................................................................... 57VREFDQ Calibration Value ............................................................................................................................ 57

Truth Tables ................................................................................................................................................... 58NOP Command .............................................................................................................................................. 61DESELECT Command .................................................................................................................................... 61DLL-Off Mode ................................................................................................................................................ 61DLL-On/Off Switching Procedures .................................................................................................................. 63

DLL Switch Sequence from DLL-On to DLL-Off ........................................................................................... 63DLL-Off to DLL-On Procedure .................................................................................................................... 65

Input Clock Frequency Change ....................................................................................................................... 66Write Leveling ................................................................................................................................................ 67

DRAM Setting for Write Leveling and DRAM TERMINATION Function in that Mode ..................................... 68Procedure Description ................................................................................................................................ 69Write-Leveling Mode Exit ............................................................................................................................ 70

Command Address Latency ............................................................................................................................ 72Low-Power Auto Self Refresh Mode ................................................................................................................. 77

Manual Self Refresh Mode .......................................................................................................................... 77Multipurpose Register .................................................................................................................................... 79

MPR Reads ................................................................................................................................................. 80MPR Readout Format ................................................................................................................................. 82MPR Readout Serial Format ........................................................................................................................ 82MPR Readout Parallel Format ..................................................................................................................... 83MPR Readout Staggered Format .................................................................................................................. 84MPR READ Waveforms ............................................................................................................................... 85MPR Writes ................................................................................................................................................ 87MPR WRITE Waveforms .............................................................................................................................. 88MPR REFRESH Waveforms ......................................................................................................................... 89

Gear-Down Mode ........................................................................................................................................... 92Maximum Power-Saving Mode ........................................................................................................................ 95

Maximum Power-Saving Mode Entry ........................................................................................................... 95Maximum Power-Saving Mode Entry in PDA ............................................................................................... 96CKE Transition During Maximum Power-Saving Mode ................................................................................. 96Maximum Power-Saving Mode Exit ............................................................................................................. 96

Command/Address Parity ............................................................................................................................... 98Per-DRAM Addressability .............................................................................................................................. 106VREFDQ Calibration ........................................................................................................................................ 109

VREFDQ Range and Levels ........................................................................................................................... 110VREFDQ Step Size ........................................................................................................................................ 110VREFDQ Increment and Decrement Timing .................................................................................................. 111

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VREFDQ Target Settings ............................................................................................................................... 115Connectivity Test Mode ................................................................................................................................. 117

Pin Mapping ............................................................................................................................................. 117Minimum Terms Definition for Logic Equations ......................................................................................... 118Logic Equations for a x4 Device, When Supported ....................................................................................... 118Logic Equations for a x8 Device, When Supported ....................................................................................... 119Logic Equations for a x16 Device ................................................................................................................ 119CT Input Timing Requirements .................................................................................................................. 119

Post Package Repair and Soft Post Package Repair ........................................................................................... 121Post Package Repair ................................................................................................................................... 121PPR Row Repair ......................................................................................................................................... 121

PPR Row Repair - Entry .......................................................................................................................... 121PR Row Repair WRA Initiated (REF Commands Allowed) ...................................................................... 122PPR Row Repair WR Initiated (REF Commands NOT Allowed) ............................................................... 123

sPPR Row Repair ....................................................................................................................................... 125PPR/sPPR Support Identifier ...................................................................................................................... 126

Target Row Refresh Mode ............................................................................................................................... 127ACTIVATE Command .................................................................................................................................... 128PRECHARGE Command ................................................................................................................................ 129REFRESH Command ..................................................................................................................................... 129Temperature-Controlled Refresh Mode .......................................................................................................... 131

TCR Mode Normal Temperature Range .................................................................................................... 131TCR Mode Extended Temperature Range ................................................................................................. 131

Fine Granularity Refresh Mode ....................................................................................................................... 133Mode Register and Command Truth Table .................................................................................................. 133tREFI and tRFC Parameters ........................................................................................................................ 133Changing Refresh Rate ............................................................................................................................... 136Usage with TCR Mode ................................................................................................................................ 136Self Refresh Entry and Exit ......................................................................................................................... 136

SELF REFRESH Operation .............................................................................................................................. 138Self Refresh Abort ...................................................................................................................................... 140Self Refresh Exit with NOP Command ......................................................................................................... 141

Power-Down Mode ........................................................................................................................................ 143Power-Down Clarifications Case 1 ........................................................................................................... 148Power-Down Entry, Exit Timing with CAL ................................................................................................... 149

ODT Input Buffer Disable Mode for Power-Down ............................................................................................ 152CRC Write Data Feature ................................................................................................................................. 154

CRC Write Data ......................................................................................................................................... 154WRITE CRC DATA Operation ...................................................................................................................... 154DBI_n and CRC Both Enabled .................................................................................................................... 155DM_n and CRC Both Enabled .................................................................................................................... 155DM_n and DBI_n Conflict During Writes with CRC Enabled ........................................................................ 155CRC Simultaneous Operation Restrictions .................................................................................................. 155CRC Polynomial ........................................................................................................................................ 155CRC Combinatorial Logic Equations .......................................................................................................... 155Burst Ordering for BL8 ............................................................................................................................... 156CRC Data Bit Mapping ............................................................................................................................... 157CRC Enabled With BC4 .............................................................................................................................. 158CRC with BC4 Data Bit Mapping ................................................................................................................ 158CRC Equations for x8 Device in BC4 Mode with A2 = 0 and A2 = 1 ................................................................ 161CRC Error Handling ................................................................................................................................... 162CRC Write Data Flow Diagram ................................................................................................................... 164

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Data Bus Inversion ........................................................................................................................................ 165DBI During a WRITE Operation .................................................................................................................. 165DBI During a READ Operation ................................................................................................................... 166

Data Mask ..................................................................................................................................................... 167Programmable Preamble Modes and DQS Postambles .................................................................................... 168

WRITE Preamble Mode .............................................................................................................................. 168READ Preamble Mode ............................................................................................................................... 171READ Preamble Training ........................................................................................................................... 171WRITE Postamble ...................................................................................................................................... 172READ Postamble ....................................................................................................................................... 172

Bank Access Operation .................................................................................................................................. 174READ Operation ............................................................................................................................................ 178

Read Timing Definitions ............................................................................................................................ 178Read Timing Clock-to-Data Strobe Relationship ....................................................................................... 179Read Timing Data Strobe-to-Data Relationship ........................................................................................ 180tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) Calculations ............................................................................ 181tRPRE Calculation ..................................................................................................................................... 183tRPST Calculation ...................................................................................................................................... 184READ Burst Operation ............................................................................................................................... 185READ Operation Followed by Another READ Operation .............................................................................. 187READ Operation Followed by WRITE Operation .......................................................................................... 192READ Operation Followed by PRECHARGE Operation ................................................................................ 198READ Operation with Read Data Bus Inversion (DBI) .................................................................................. 201READ Operation with Command/Address Parity (CA Parity) ........................................................................ 202READ Followed by WRITE with CRC Enabled .............................................................................................. 203READ Operation with Command/Address Latency (CAL) Enabled ............................................................... 204

WRITE Operation .......................................................................................................................................... 206Write Timing Definitions ........................................................................................................................... 206Write Timing Clock-to-Data Strobe Relationship ...................................................................................... 207Write Timing Data Strobe-to-Data Relationship ........................................................................................ 209WRITE Burst Operation ............................................................................................................................. 212WRITE Operation Followed by Another WRITE Operation ........................................................................... 214WRITE Operation Followed by READ Operation .......................................................................................... 220WRITE Operation Followed by PRECHARGE Operation ............................................................................... 224WRITE Operation with WRITE DBI Enabled ................................................................................................ 227WRITE Operation with CA Parity Enabled ................................................................................................... 229WRITE Operation with Write CRC Enabled ................................................................................................. 230

Write Timing Violations ................................................................................................................................. 235Motivation ................................................................................................................................................ 235Data Setup and Hold Violations ................................................................................................................. 235Strobe-to-Strobe and Strobe-to-Clock Violations ........................................................................................ 235

ZQ CALIBRATION Commands ....................................................................................................................... 236On-Die Termination ...................................................................................................................................... 238ODT Mode Register and ODT State Table ........................................................................................................ 238

ODT Read Disable State Table .................................................................................................................... 239Synchronous ODT Mode ................................................................................................................................ 240

ODT Latency and Posted ODT .................................................................................................................... 240Timing Parameters .................................................................................................................................... 240ODT During Reads .................................................................................................................................... 242

Dynamic ODT ............................................................................................................................................... 243Functional Description .............................................................................................................................. 243

Asynchronous ODT Mode .............................................................................................................................. 246

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Electrical Specifications ................................................................................................................................. 247Absolute Ratings ........................................................................................................................................ 247DRAM Component Operating Temperature Range ...................................................................................... 247

Electrical Characteristics AC and DC Operating Conditions .......................................................................... 248Supply Operating Conditions ..................................................................................................................... 248Leakages ................................................................................................................................................... 248VREFCA Supply ............................................................................................................................................ 249VREFDQ Supply and Calibration Ranges ....................................................................................................... 249VREFDQ Ranges ........................................................................................................................................... 250

Electrical Characteristics AC and DC Single-Ended Input Measurement Levels .............................................. 251RESET_n Input Levels ................................................................................................................................ 251Command/Address Input Levels ................................................................................................................ 252Data Receiver Input Requirements ............................................................................................................. 254Connectivity Test (CT) Mode Input Levels .................................................................................................. 257

Electrical Characteristics AC and DC Differential Input Measurement Levels ................................................. 261Differential Inputs ..................................................................................................................................... 261Single-Ended Requirements for CK Differential Signals ............................................................................... 262Slew Rate Definitions for CK Differential Input Signals ................................................................................ 263CK Differential Input Cross Point Voltage .................................................................................................... 264DQS Differential Input Signal Definition and Swing Requirements .............................................................. 265DQS Differential Input Cross Point Voltage ................................................................................................. 267Slew Rate Definitions for DQS Differential Input Signals .............................................................................. 267

Electrical Characteristics Overshoot and Undershoot Specifications ............................................................. 269Address, Command, and Control Overshoot and Undershoot Specifications ................................................ 269Clock Overshoot and Undershoot Specifications ......................................................................................... 270Data, Strobe, and Mask Overshoot and Undershoot Specifications .............................................................. 271

Electrical Characteristics AC and DC Output Measurement Levels ................................................................ 271Single-Ended Outputs ............................................................................................................................... 271Differential Outputs .................................................................................................................................. 273Reference Load for AC Timing and Output Slew Rate ................................................................................... 274Connectivity Test Mode Output Levels ........................................................................................................ 275

Electrical Characteristics AC and DC Output Driver Characteristics ............................................................... 277Output Driver Electrical Characteristics ..................................................................................................... 277Output Driver Temperature and Voltage Sensitivity ..................................................................................... 280Alert Driver ............................................................................................................................................... 280

Electrical Characteristics On-Die Termination Characteristics ...................................................................... 281ODT Levels and I-V Characteristics ............................................................................................................ 281ODT Temperature and Voltage Sensitivity ................................................................................................... 282ODT Timing Definitions ............................................................................................................................ 283

DRAM Package Electrical Specifications ......................................................................................................... 286Thermal Characteristics ................................................................................................................................. 290Current Specifications Measurement Conditions .......................................................................................... 291

IDD, IPP, and IDDQ Measurement Conditions ................................................................................................ 291IDD Definitions .......................................................................................................................................... 292

Current Specifications Patterns and Test Conditions ..................................................................................... 296Current Test Definitions and Patterns ......................................................................................................... 296IDD Specifications ...................................................................................................................................... 305

Current Specifications Limits ....................................................................................................................... 306Speed Bin Tables ........................................................................................................................................... 308Refresh Parameters By Device Density ............................................................................................................ 313Electrical Characteristics and AC Timing Parameters ...................................................................................... 314Options Tables .............................................................................................................................................. 325

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List of FiguresFigure 1: 78-Ball x4, x8 Ball Assignments ........................................................................................................ 18Figure 2: 96-Ball x16 Ball Assignments ............................................................................................................ 19Figure 3: 78-Ball FBGA x4, x8 ....................................................................................................................... 23Figure 4: 96-Ball FBGA x16 .......................................................................................................................... 24Figure 5: Simplified State Diagram ................................................................................................................. 25Figure 6: RESET and Initialization Sequence at Power-On Ramping ................................................................. 30Figure 7: RESET Procedure at Power Stable Condition ..................................................................................... 31Figure 8: tMRD Timing .................................................................................................................................. 33Figure 9: tMOD Timing .................................................................................................................................. 33Figure 10: DLL-Off Mode Read Timing Operation ........................................................................................... 62Figure 11: DLL Switch Sequence from DLL-On to DLL-Off .............................................................................. 64Figure 12: DLL Switch Sequence from DLL-Off to DLL-On .............................................................................. 65Figure 13: Write-Leveling Concept, Example 1 ................................................................................................ 67Figure 14: Write-Leveling Concept, Example 2 ................................................................................................ 68Figure 15: Write-Leveling Sequence (DQS Capturing CK LOW at T1 and CK HIGH at T2) .................................. 70Figure 16: Write-Leveling Exit ........................................................................................................................ 71Figure 17: CAL Timing Definition ................................................................................................................... 72Figure 18: CAL Timing Example (Consecutive CS_n = LOW) ............................................................................ 72Figure 19: CAL Enable Timing tMOD_CAL ................................................................................................... 73Figure 20: tMOD_CAL, MRS to Valid Command Timing with CAL Enabled ....................................................... 73Figure 21: CAL Enabling MRS to Next MRS Command, tMRD_CAL .................................................................. 74Figure 22: tMRD_CAL, Mode Register Cycle Time With CAL Enabled ............................................................... 74Figure 23: Consecutive READ BL8, CAL3, 1tCK Preamble, Different Bank Group ............................................... 75Figure 24: Consecutive READ BL8, CAL4, 1tCK Preamble, Different Bank Group ............................................... 75Figure 25: Auto Self Refresh Ranges ................................................................................................................ 78Figure 26: MPR Block Diagram ....................................................................................................................... 79Figure 27: MPR READ Timing ........................................................................................................................ 85Figure 28: MPR Back-to-Back READ Timing ................................................................................................... 86Figure 29: MPR READ-to-WRITE Timing ........................................................................................................ 87Figure 30: MPR WRITE and WRITE-to-READ Timing ...................................................................................... 88Figure 31: MPR Back-to-Back WRITE Timing .................................................................................................. 89Figure 32: REFRESH Timing ........................................................................................................................... 89Figure 33: READ-to-REFRESH Timing ............................................................................................................ 90Figure 34: WRITE-to-REFRESH Timing .......................................................................................................... 90Figure 35: Clock Mode Change from 1/2 Rate to 1/4 Rate (Initialization) .......................................................... 93Figure 36: Clock Mode Change After Exiting Self Refresh ................................................................................. 93Figure 37: Comparison Between Gear-Down Disable and Gear-Down Enable .................................................. 94Figure 38: Maximum Power-Saving Mode Entry .............................................................................................. 95Figure 39: Maximum Power-Saving Mode Entry with PDA ............................................................................... 96Figure 40: Maintaining Maximum Power-Saving Mode with CKE Transition .................................................... 96Figure 41: Maximum Power-Saving Mode Exit ................................................................................................ 97Figure 42: Command/Address Parity Operation .............................................................................................. 98Figure 43: Command/Address Parity During Normal Operation ..................................................................... 100Figure 44: Persistent CA Parity Error Checking Operation ............................................................................... 101Figure 45: CA Parity Error Checking SRE Attempt ........................................................................................ 101Figure 46: CA Parity Error Checking SRX Attempt ........................................................................................ 102Figure 47: CA Parity Error Checking PDE/PDX ............................................................................................ 102Figure 48: Parity Entry Timing Example tMRD_PAR ..................................................................................... 103Figure 49: Parity Entry Timing Example tMOD_PAR ..................................................................................... 103Figure 50: Parity Exit Timing Example tMRD_PAR ....................................................................................... 103

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Figure 51: Parity Exit Timing Example tMOD_PAR ....................................................................................... 104Figure 52: CA Parity Flow Diagram ................................................................................................................ 105Figure 53: PDA Operation Enabled, BL8 ........................................................................................................ 107Figure 54: PDA Operation Enabled, BC4 ........................................................................................................ 107Figure 55: MRS PDA Exit ............................................................................................................................... 108Figure 56: VREFDQ Voltage Range ................................................................................................................... 109Figure 57: Example of VREF Set Tolerance and Step Size .................................................................................. 111Figure 58: VREFDQ Timing Diagram for VREF,time Parameter .............................................................................. 112Figure 59: VREFDQ Training Mode Entry and Exit Timing Diagram ................................................................... 113Figure 60: VREF Step: Single Step Size Increment Case .................................................................................... 114Figure 61: VREF Step: Single Step Size Decrement Case ................................................................................... 114Figure 62: VREF Full Step: From VREF,min to VREF,maxCase .................................................................................. 115Figure 63: VREF Full Step: From VREF,max to VREF,minCase .................................................................................. 115Figure 64: VREFDQ Equivalent Circuit ............................................................................................................. 116Figure 65: Connectivity Test Mode Entry ....................................................................................................... 120Figure 66: PPR WRA Entry .......................................................................................................................... 123Figure 67: PPR WRA Repair and Exit ........................................................................................................... 123Figure 68: PPR WR Entry ............................................................................................................................ 124Figure 69: PPR WR Repair and Exit .............................................................................................................. 124Figure 70: sPPR Entry, Repair, and Exit ........................................................................................................ 126Figure 71: tRRD Timing ................................................................................................................................ 128Figure 72: tFAW Timing ................................................................................................................................. 128Figure 73: REFRESH Command Timing ......................................................................................................... 130Figure 74: Postponing REFRESH Commands (Example) ................................................................................. 130Figure 75: Pulling In REFRESH Commands (Example) ................................................................................... 130Figure 76: TCR Mode Example1 ..................................................................................................................... 132Figure 77: 4Gb with Fine Granularity Refresh Mode Example ......................................................................... 135Figure 78: OTF REFRESH Command Timing ................................................................................................. 136Figure 79: Self Refresh Entry/Exit Timing ...................................................................................................... 139Figure 80: Self Refresh Entry/Exit Timing with CAL Mode ............................................................................... 140Figure 81: Self Refresh Abort ......................................................................................................................... 141Figure 82: Self Refresh Exit with NOP Command ............................................................................................ 142Figure 83: Active Power-Down Entry and Exit ................................................................................................ 144Figure 84: Power-Down Entry After Read and Read with Auto Precharge ......................................................... 145Figure 85: Power-Down Entry After Write and Write with Auto Precharge ........................................................ 145Figure 86: Power-Down Entry After Write ...................................................................................................... 146Figure 87: Precharge Power-Down Entry and Exit .......................................................................................... 146Figure 88: REFRESH Command to Power-Down Entry ................................................................................... 147Figure 89: Active Command to Power-Down Entry ......................................................................................... 147Figure 90: PRECHARGE/PRECHARGE ALL Command to Power-Down Entry .................................................. 148Figure 91: MRS Command to Power-Down Entry ........................................................................................... 148Figure 92: Power-Down Entry/Exit Clarifications Case 1 .............................................................................. 149Figure 93: Active Power-Down Entry and Exit Timing with CAL ...................................................................... 150Figure 94: REFRESH Command to Power-Down Entry with CAL ..................................................................... 151Figure 95: ODT Power-Down Entry with ODT Buffer Disable Mode ................................................................ 152Figure 96: ODT Power-Down Exit with ODT Buffer Disable Mode ................................................................... 153Figure 97: CRC Write Data Operation ............................................................................................................ 154Figure 98: CRC Error Reporting ..................................................................................................................... 163Figure 99: CA Parity Flow Diagram ................................................................................................................ 164Figure 100: 1tCK vs. 2tCK WRITE Preamble Mode ........................................................................................... 168Figure 101: 1tCK vs. 2tCK WRITE Preamble Mode, tCCD = 4 ............................................................................ 169Figure 102: 1tCK vs. 2tCK WRITE Preamble Mode, tCCD = 5 ............................................................................ 170

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Figure 103: 1tCK vs. 2 tCK WRITE Preamble Mode, tCCD = 6 ........................................................................... 170Figure 104: 1tCK vs. 2tCK READ Preamble Mode ............................................................................................ 171Figure 105: READ Preamble Training ............................................................................................................. 172Figure 106: WRITE Postamble ....................................................................................................................... 172Figure 107: READ Postamble ........................................................................................................................ 173Figure 108: Bank Group x4/x8 Block Diagram ................................................................................................ 174Figure 109: READ Burst tCCD_S and tCCD_L Examples .................................................................................. 175Figure 110: Write Burst tCCD_S and tCCD_L Examples ................................................................................... 175Figure 111: tRRD Timing ............................................................................................................................... 176Figure 112: tWTR_S Timing (WRITE-to-READ, Different Bank Group, CRC and DM Disabled) ......................... 176Figure 113: tWTR_L Timing (WRITE-to-READ, Same Bank Group, CRC and DM Disabled) .............................. 177Figure 114: Read Timing Definition ............................................................................................................... 179Figure 115: Clock-to-Data Strobe Relationship .............................................................................................. 180Figure 116: Data Strobe-to-Data Relationship ................................................................................................ 181Figure 117: tLZ and tHZ Method for Calculating Transitions and Endpoints .................................................... 182Figure 118: tRPRE Method for Calculating Transitions and Endpoints ............................................................. 183Figure 119: tRPST Method for Calculating Transitions and Endpoints ............................................................. 184Figure 120: READ Burst Operation, RL = 11 (AL = 0, CL = 11, BL8) ................................................................... 185Figure 121: READ Burst Operation, RL = 21 (AL = 10, CL = 11, BL8) ................................................................. 186Figure 122: Consecutive READ (BL8) with 1tCK Preamble in Different Bank Group .......................................... 187Figure 123: Consecutive READ (BL8) with 2tCK Preamble in Different Bank Group .......................................... 187Figure 124: Nonconsecutive READ (BL8) with 1tCK Preamble in Same or Different Bank Group ....................... 188Figure 125: Nonconsecutive READ (BL8) with 2tCK Preamble in Same or Different Bank Group ....................... 188Figure 126: READ (BC4) to READ (BC4) with 1tCK Preamble in Different Bank Group ...................................... 189Figure 127: READ (BC4) to READ (BC4) with 2tCK Preamble in Different Bank Group ...................................... 189Figure 128: READ (BL8) to READ (BC4) OTF with 1tCK Preamble in Different Bank Group ............................... 190Figure 129: READ (BL8) to READ (BC4) OTF with 2tCK Preamble in Different Bank Group ............................... 190Figure 130: READ (BC4) to READ (BL8) OTF with 1tCK Preamble in Different Bank Group ............................... 191Figure 131: READ (BC4) to READ (BL8) OTF with 2tCK Preamble in Different Bank Group ............................... 191Figure 132: READ (BL8) to WRITE (BL8) with 1tCK Preamble in Same or Different Bank Group ........................ 192Figure 133: READ (BL8) to WRITE (BL8) with 2tCK Preamble in Same or Different Bank Group ........................ 192Figure 134: READ (BC4) OTF to WRITE (BC4) OTF with 1tCK Preamble in Same or Different Bank Group ......... 193Figure 135: READ (BC4) OTF to WRITE (BC4) OTF with 2tCK Preamble in Same or Different Bank Group ......... 194Figure 136: READ (BC4) Fixed to WRITE (BC4) Fixed with 1tCK Preamble in Same or Different Bank Group ..... 194Figure 137: READ (BC4) Fixed to WRITE (BC4) Fixed with 2tCK Preamble in Same or Different Bank Group ..... 195Figure 138: READ (BC4) to WRITE (BL8) OTF with 1tCK Preamble in Same or Different Bank Group ................ 196Figure 139: READ (BC4) to WRITE (BL8) OTF with 2tCK Preamble in Same or Different Bank Group ................ 196Figure 140: READ (BL8) to WRITE (BC4) OTF with 1tCK Preamble in Same or Different Bank Group ................ 197Figure 141: READ (BL8) to WRITE (BC4) OTF with 2tCK Preamble in Same or Different Bank Group ................ 197Figure 142: READ to PRECHARGE with 1tCK Preamble .................................................................................. 198Figure 143: READ to PRECHARGE with 2tCK Preamble .................................................................................. 199Figure 144: READ to PRECHARGE with Additive Latency and 1tCK Preamble .................................................. 199Figure 145: READ with Auto Precharge and 1tCK Preamble ............................................................................ 200Figure 146: READ with Auto Precharge, Additive Latency, and 1tCK Preamble ................................................. 200Figure 147: Consecutive READ (BL8) with 1tCK Preamble and DBI in Different Bank Group ............................ 201Figure 148: Consecutive READ (BL8) with 1tCK Preamble and CA Parity in Different Bank Group .................... 202Figure 149: READ (BL8) to WRITE (BL8) with 1tCK Preamble and CA Parity in Same or Different Bank Group ... 202Figure 150: READ (BL8) to WRITE (BL8 or BC4: OTF) with 1tCK Preamble and Write CRC in Same or Different

Bank Group ............................................................................................................................................... 203Figure 151: READ (BC4: Fixed) to WRITE (BC4: Fixed) with 1tCK Preamble and Write CRC in Same or Different

Bank Group ............................................................................................................................................... 204Figure 152: Consecutive READ (BL8) with CAL (3tCK) and 1tCK Preamble in Different Bank Group .................. 204

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Figure 153: Consecutive READ (BL8) with CAL (4tCK) and 1tCK Preamble in Different Bank Group .................. 205Figure 154: Write Timing Definition .............................................................................................................. 206Figure 155: Clock-to-Data Strobe Relationship .............................................................................................. 208Figure 156: Rx Compliance Mask .................................................................................................................. 209Figure 157: VCENT_DQ VREFDQ Voltage Variation .............................................................................................. 209Figure 158: Rx Mask DQ-to-DQS Timings ...................................................................................................... 210Figure 159: Rx Mask DQ-to-DQS DRAM-Based Timings ................................................................................. 211Figure 160: Example of Data Input Requirements Without Training ................................................................ 212Figure 161: WRITE Burst Operation, WL = 9 (AL = 0, CWL = 9, BL8) ................................................................. 213Figure 162: WRITE Burst Operation, WL = 19 (AL = 10, CWL = 9, BL8) ............................................................. 214Figure 163: Consecutive WRITE (BL8) with 1tCK Preamble in Different Bank Group ........................................ 214Figure 164: Consecutive WRITE (BL8) with 2tCK Preamble in Different Bank Group ........................................ 215Figure 165: Nonconsecutive WRITE (BL8) with 1tCK Preamble in Same or Different Bank Group ..................... 216Figure 166: Nonconsecutive WRITE (BL8) with 2tCK Preamble in Same or Different Bank Group ..................... 216Figure 167: WRITE (BC4) OTF to WRITE (BC4) OTF with 1 tCK Preamble in Different Bank Group .................... 217Figure 168: WRITE (BC4) OTF to WRITE (BC4) OTF with 2 tCK Preamble in Different Bank Group .................... 218Figure 169: WRITE (BC4) Fixed to WRITE (BC4) Fixed with 1 tCK Preamble in Different Bank Group ................. 218Figure 170: WRITE (BL8) to WRITE (BC4) OTF with 1 tCK Preamble in Different Bank Group ............................ 219Figure 171: WRITE (BC4) OTF to WRITE (BL8) with 1 tCK Preamble in Different Bank Group ............................ 220Figure 172: WRITE (BL8) to READ (BL8) with 1tCK Preamble in Different Bank Group ..................................... 220Figure 173: WRITE (BL8) to READ (BL8) with 1tCK Preamble in Same Bank Group .......................................... 221Figure 174: WRITE (BC4) OTF to READ (BC4) OTF with 1tCK Preamble in Different Bank Group ...................... 222Figure 175: WRITE (BC4) OTF to READ (BC4) OTF with 1tCK Preamble in Same Bank Group ........................... 222Figure 176: WRITE (BC4) Fixed to READ (BC4) Fixed with 1 tCK Preamble in Different Bank Group ................. 223Figure 177: WRITE (BC4) Fixed to READ (BC4) Fixed with 1tCK Preamble in Same Bank Group ....................... 223Figure 178: WRITE (BL8/BC4-OTF) to PRECHARGE with 1tCK Preamble ........................................................ 224Figure 179: WRITE (BC4-Fixed) to PRECHARGE with 1tCK Preamble .............................................................. 225Figure 180: WRITE (BL8/BC4-OTF) to Auto PRECHARGE with 1tCK Preamble ................................................ 225Figure 181: WRITE (BC4-Fixed) to Auto PRECHARGE with 1tCK Preamble ...................................................... 226Figure 182: WRITE (BL8/BC4-OTF) with 1tCK Preamble and DBI ................................................................... 227Figure 183: WRITE (BC4-Fixed) with 1tCK Preamble and DBI ......................................................................... 228Figure 184: Consecutive Write (BL8) with 1tCK Preamble and CA Parity in Different Bank Group ..................... 229Figure 185: Consecutive WRITE (BL8/BC4-OTF) with 1tCK Preamble and Write CRC in Same or Different Bank

Group ....................................................................................................................................................... 230Figure 186: Consecutive WRITE (BC4-Fixed) with 1tCK Preamble and Write CRC in Same or Different Bank

Group ....................................................................................................................................................... 231Figure 187: Nonconsecutive WRITE (BL8/BC4-OTF) with 1tCK Preamble and Write CRC in Same or Different

Bank Group ............................................................................................................................................... 232Figure 188: Nonconsecutive WRITE (BL8/BC4-OTF) with 2tCK Preamble and Write CRC in Same or Different

Bank Group ............................................................................................................................................... 233Figure 189: WRITE (BL8/BC4-OTF/Fixed) with 1tCK Preamble and Write CRC in Same or Different Bank Group ... 234Figure 190: ZQ Calibration Timing ................................................................................................................ 237Figure 191: Functional Representation of ODT .............................................................................................. 238Figure 192: Synchronous ODT Timing with BL8 ............................................................................................. 241Figure 193: Synchronous ODT with BC4 ........................................................................................................ 241Figure 194: ODT During Reads ...................................................................................................................... 242Figure 195: Dynamic ODT (1t CK Preamble; CL = 14, CWL = 11, BL = 8, AL = 0, CRC Disabled) .......................... 244Figure 196: Dynamic ODT Overlapped with RTT(NOM) (CL = 14, CWL = 11, BL = 8, AL = 0, CRC Disabled) .......... 245Figure 197: Asynchronous ODT Timings with DLL Off ................................................................................... 246Figure 198: VREFDQ Voltage Range .................................................................................................................. 249Figure 199: RESET_n Input Slew Rate Definition ............................................................................................ 252Figure 200: Single-Ended Input Slew Rate Definition ..................................................................................... 253

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Figure 201: DQ Slew Rate Definitions ............................................................................................................ 254Figure 202: Rx Mask Relative to tDS/tDH ....................................................................................................... 256Figure 203: Rx Mask Without Write Training .................................................................................................. 257Figure 204: TEN Input Slew Rate Definition ................................................................................................... 258Figure 205: CT Type-A Input Slew Rate Definition .......................................................................................... 258Figure 206: CT Type-B Input Slew Rate Definition .......................................................................................... 259Figure 207: CT Type-C Input Slew Rate Definition .......................................................................................... 260Figure 208: CT Type-D Input Slew Rate Definition ......................................................................................... 260Figure 209: Differential AC Swing and Time Exceeding AC-Level tDVAC ....................................................... 261Figure 210: Single-Ended Requirements for CK .............................................................................................. 263Figure 211: Differential Input Slew Rate Definition for CK_t, CK_c .................................................................. 264Figure 212: VIX(CK) Definition ........................................................................................................................ 264Figure 213: Differential Input Signal Definition for DQS_t, DQS_c .................................................................. 265Figure 214: DQS_t, DQS_c Input Peak Voltage Calculation ............................................................................. 266Figure 215: VIXDQS Definition ........................................................................................................................ 267Figure 216: Differential Input Slew Rate and Input Level Definition for DQS_t, DQS_c ..................................... 268Figure 217: ADDR, CMD, CNTL Overshoot and Undershoot Definition ........................................................... 269Figure 218: CK Overshoot and Undershoot Definition .................................................................................... 270Figure 219: Data, Strobe, and Mask Overshoot and Undershoot Definition ..................................................... 271Figure 220: Single-ended Output Slew Rate Definition ................................................................................... 272Figure 221: Differential Output Slew Rate Definition ...................................................................................... 274Figure 222: Reference Load For AC Timing and Output Slew Rate ................................................................... 275Figure 223: Connectivity Test Mode Reference Test Load ................................................................................ 275Figure 224: Connectivity Test Mode Output Slew Rate Definition .................................................................... 276Figure 225: Output Driver: Definition of Voltages and Currents ...................................................................... 277Figure 226: Alert Driver ................................................................................................................................ 280Figure 227: ODT Definition of Voltages and Currents ..................................................................................... 281Figure 228: ODT Timing Reference Load ....................................................................................................... 283Figure 229: tADC Definition with Direct ODT Control .................................................................................... 284Figure 230: tADC Definition with Dynamic ODT Control ................................................................................ 285Figure 231: tAOFAS and tAONAS Definitions .................................................................................................. 285Figure 232: Thermal Measurement Point ....................................................................................................... 290Figure 233: Measurement Setup and Test Load for IDDx, IDDPx, and IDDQx ........................................................ 292Figure 234: Correlation: Simulated Channel I/O Power to Actual Channel I/O Power ....................................... 292

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List of TablesTable 1: Key Timing Parameters ....................................................................................................................... 1Table 2: Addressing ......................................................................................................................................... 2Table 3: Ball Descriptions .............................................................................................................................. 20Table 4: State Diagram Command Definitions ................................................................................................ 26Table 5: Address Pin Mapping ........................................................................................................................ 35Table 6: MR0 Register Definition .................................................................................................................... 35Table 7: Burst Type and Burst Order ............................................................................................................... 37Table 8: Address Pin Mapping ........................................................................................................................ 39Table 9: MR1 Register Definition .................................................................................................................... 39Table 10: Additive Latency (AL) Settings ......................................................................................................... 41Table 11: TDQS Function Matrix .................................................................................................................... 42Table 12: Address Pin Mapping ...................................................................................................................... 43Table 13: MR2 Register Definition .................................................................................................................. 43Table 14: Address Pin Mapping ...................................................................................................................... 46Table 15: MR3 Register Definition .................................................................................................................. 46Table 16: Address Pin Mapping ...................................................................................................................... 49Table 17: MR4 Register Definition .................................................................................................................. 49Table 18: Address Pin Mapping ...................................................................................................................... 53Table 19: MR5 Register Definition .................................................................................................................. 53Table 20: Address Pin Mapping ...................................................................................................................... 56Table 21: MR6 Register Definition .................................................................................................................. 56Table 22: Truth Table Command .................................................................................................................. 58Table 23: Truth Table CKE ........................................................................................................................... 60Table 24: MR Settings for Leveling Procedures ................................................................................................ 68Table 25: DRAM TERMINATION Function in Leveling Mode ........................................................................... 68Table 26: Auto Self Refresh Mode ................................................................................................................... 77Table 27: MR3 Setting for the MPR Access Mode ............................................................................................. 79Table 28: DRAM Address to MPR UI Translation ............................................................................................. 79Table 29: MPR Page and MPRx Definitions ..................................................................................................... 80Table 30: MPR Readout Serial Format ............................................................................................................. 82Table 31: MPR Readout Parallel Format ....................................................................................................... 83Table 32: MPR Readout Staggered Format, x4 ................................................................................................. 84Table 33: MPR Readout Staggered Format, x4 Consecutive READs ................................................................ 84Table 34: MPR Readout Staggered Format, x8 and x16 ..................................................................................... 85Table 35: Mode Register Setting for CA Parity ................................................................................................. 100Table 36: VREFDQ Range and Levels ................................................................................................................ 110Table 37: VREFDQ Settings (VDDQ = 1.2V) ......................................................................................................... 116Table 38: Connectivity Mode Pin Description and Switching Levels ................................................................ 118Table 39: PPR MR0 Guard Key Settings .......................................................................................................... 122Table 40: DDR4 PPR Timing Parameters ........................................................................................................ 125Table 41: DDR4 sPPR Timing Parameters ...................................................................................................... 126Table 42: DDR4 Repair Mode Support Identifier ............................................................................................ 126Table 43: MAC Encoding of MPR Page 3 MPR3 ............................................................................................... 127Table 44: Normal tREFI Refresh (TCR Disabled) ............................................................................................. 131Table 45: Normal tREFI Refresh (TCR Enabled) .............................................................................................. 132Table 46: MRS Definition .............................................................................................................................. 133Table 47: REFRESH Command Truth Table .................................................................................................... 133Table 48: tREFI and tRFC Parameters ............................................................................................................. 134Table 49: Power-Down Entry Definitions ....................................................................................................... 143Table 50: CRC Error Detection Coverage ........................................................................................................ 155

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Table 51: CRC Data Mapping for x4 Devices, BL8 ........................................................................................... 157Table 52: CRC Data Mapping for x8 Devices, BL8 ........................................................................................... 157Table 53: CRC Data Mapping for x16 Devices, BL8 ......................................................................................... 158Table 54: CRC Data Mapping for x4 Devices, BC4 ........................................................................................... 158Table 55: CRC Data Mapping for x8 Devices, BC4 ........................................................................................... 159Table 56: CRC Data Mapping for x16 Devices, BC4 ......................................................................................... 160Table 57: DBI vs. DM vs. TDQS Function Matrix ............................................................................................. 165Table 58: DBI Write, DQ Frame Format (x8) ................................................................................................... 165Table 59: DBI Write, DQ Frame Format (x16) ................................................................................................. 165Table 60: DBI Read, DQ Frame Format (x8) .................................................................................................... 166Table 61: DBI Read, DQ Frame Format (x16) .................................................................................................. 166Table 62: DM vs. TDQS vs. DBI Function Matrix ............................................................................................. 167Table 63: Data Mask, DQ Frame Format (x8) .................................................................................................. 167Table 64: Data Mask, DQ Frame Format (x16) ................................................................................................ 167Table 65: CWL Selection ............................................................................................................................... 169Table 66: DDR4 Bank Group Timings ............................................................................................................ 174Table 67: Termination State Table ................................................................................................................. 239Table 68: Read Termination Disable Window ................................................................................................. 239Table 69: ODT Latency at DDR4-1600/-1866/-2133/-2400/-2666/-3200 .......................................................... 240Table 70: Dynamic ODT Latencies and Timing (1tCK Preamble Mode and CRC Disabled) ................................ 243Table 71: Dynamic ODT Latencies and Timing with Preamble Mode and CRC Mode Matrix ............................ 244Table 72: Absolute Maximum Ratings ............................................................................................................ 247Table 73: Temperature Range ........................................................................................................................ 247Table 74: Recommended Supply Operating Conditions .................................................................................. 248Table 75: VDD Slew Rate ................................................................................................................................ 248Table 76: Leakages ....................................................................................................................................... 248Table 77: VREFDQ Spe