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DESIGN FLOW OF NIOS II PROCESSOPR USING QSYS

In this session explains about design flow of Nios II processor and Quartus II

software to implementation for digital picture viewer in a cyclone III FPGA. For this

we need system specifications for both software as well as hardware.

Software and Hardware Requirement!

N! development board

Quartus II software v"".#$ including the following items%

o Quartus II FPGA synthesis and compilation tool

o Qsys system integration tool

o &ega 'ore IP library

o Nios II ()$ featuring the Nios II )oftware *uild +ools ,)*+- for

clipse

Dei"n f#ow Q$!

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/." Figure for design flow

In this flow$ you specify the system definition using Qsys. After you define

the Qsys system$ Qsys generates the following two 0inds of output.

o +he 1(2 files that the Quartus II software compiles to generate the

configuration file for the FPGA. +his Quartus II compilation process is the

hardware flow.

o A system description that the software development tools use to generate a

system library specific to the Qsys system. +his system library$ also called

a board support pac0age$ supports the Nios II processor in running the

software. +he Nios II )*+ for clipse provides an environment in which

you can develop software applications for your system. +his Nios II )*+

development process is the software flow.

+he output of the hardware flow is an FPGA image that configures the target

device. +he output of the software flow is an executable file that the Nios II

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processor can run.

In t%i tutoria# $ou &erform t%e fo##owin"

te&!

". *uild Qsys system

o 3pen the Quartus II

pro4ect.

o )tart Qsys.

o )elect and configure system components$ including IP &ega 'ore

functions.

o &a0e connections.

o Assign cloc0s and set base addresses.

o )et interrupt and arbitration priorities.

5. Generate the system to create the following items%

1(2 for the entire Qsys system.

A system description files that software development tools use to build

the hardware drivers and other relevant system information for the

software application.

6. 'omplete the Quartus II pro4ect%

Add the Qsys system to the top level of the Quartus II

pro4ect.

Add pin assignments.

'ompile the pro4ect to generate an )7A& 3b4ect File

,'of-.

8se the Quartus II Programmer to download the 'of to the

FPGA.

. (evelop the software application%

)tart the Nios II )*+ for clipse.

Add source files.

'onfigure build properties.

*uild the application to generate the xecutable and

2in0ing Format File ,'e#f-.

9. 8se the Flash Programmer to convert the image files to flash memory image files

,'f#a%- and download the flash image data to 'FI flash memory.

:. 8se the Nios II )*+ for clipse to download and run the 'e#f for the

software application.

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(#o)* dia"ram of Di"ita# &i)ture +iewer!

/.5 bloc0 diagram of Qsys

Hardware )om&onent and t%eir &erforman)e!

'omponent 'omponent Instance 'ompo

Nios II 'pu 7uns the software that controls the system.

Generic +ri;)tate Flash

'ontrols the timing for driving read and writes

transactions on the external 'FI flash memory. +he

+ri;)tate 'onduit

*rid e flash=bridge 'onnects the flash memor controller to the external

((7

)(7A& ddr=sdram )tores execute code and data in the framebuffers.

)ystem I( )ysid

Allows the Nios II=)*+ to verify that the software

isbuilt for the correct hardware version.

Avalon;&&

'loc0 slow=cloc0=crossing=br

'onnects the processor in the high;fre>uency

domain to the slower;fre>uencyperipherals.

PI3 ,Parallel I?3- lcd=i5c=scl

interface includes$ a cloc0 signal$ and an enable signal.

7efer toImpleme n ting a n LCD Contro lle r.

PI3 ,Parallel I?3- lcd=i5c=en

PI3 ,Parallel I?3- lcd=i5c=sdat

PI3 ,Parallel I?3- pio=id=eeprom=scl +wo;wire P73& I( interface components. +he I5'

serial P73& I( chip stores information about thePI3 ,Parallel I?3- pio=id=eeprom=dat

)PI ,6 @ire touch=panel=spi +ouch screen interface components. 7efer to

Implem e nting an LCDContr o lle r.PI3 ,Parallel I?3- touch=panel=pen=ir>

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Avalon;)+

+imin timer=adapter=#

ideo pipeline components. 7efer to

Impleme n ting an LCDContr o lle r.

3n;'hip Fifo

Avalon;)+

+iming timer=adapter="Pixel 'onverter

*G7# ;B *G7 pixel=converter

Avalon;)+ (ata

Format Ada ter data=format=adapter

ideo )ync video=sync=generato

/." table for components and their functioning

S&e)if$ t%e E,terna# C#o)* and C#o)* Conne)tion!

In this section$ you connect each component to the correct cloc0.

+he cloc0 source for the full digital picture viewer is the 9#;&1C oscillator

on the N! board. +he 9#;&1C oscillator is also the reference cloc0 fre>uency

for the ((7 )(7A& controller$ which runs at "## &1C. +he "##;&1C cloc0 from

the ((7 )(7A& is used by most components in the system$ including the

processor$ the flash controller$ and the video subsystem. 3nly the slow;fre>uency

components in the peripheral subsystem run at 9# &1C$ using the oscillator cloc0.

48.3show the Qsys 'loc0 )ettings tab with available cloc0s for the system.

S&e)if$ t%e Reet Conne)tion!

+his design has a single reset coming into the Qsys system$ namely$ the

cl0=reset port of o)-)#*. 'onnect the components in the system to this main resetby clic0ing on the connection dot between the cl0=reset port of o)-)#* and the

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following component ports%

+he resetport of flash=bridge

+he reset=9#port of peripheral=subsystem

+he reset="##port of peripheral=subsystem

+he resetport of sysid

+he reset=nport of cpu

+he soft=reset=nport of ddr=sdram

+he global=reset=nport of ddr=sdr

he resetport of flash

+he reset=nport of video=subsystem

Reai"n t%e Com&onent (ae .ddree to E#iminate/emor$ Conf#i)t!

+o reassign component base addresses to eliminate undesired overlap

between the address spaces of different components$ perform the following steps%

". 3n the )ystem menu$ clic0 .i"n (ae .ddree. Qsys assigns

appropriate base addresses for the components.

5. 7eassign the following base addresses to the Avalon &emory;&apped

,Avalon;&&- slave ports of the following components

For the4tag=debug=moduleport of cpu$ type #x"######.

For the uasport of flash$ type #x########.

For the s"port of ddr=sdram$ type #x5######.

For the sgdma=csrport of video=subsystem$ type #x9######.

For the slow=cloc0=crosing=bridgeport ofperipheral=subsystem$ type

#x######. For the control=slaveport of sysid$ type #x"###/###.

Set t%e Interru&t Prioritie!

+o render images on the 2'( screen smoothly$ the "dma component of

the video subsystem must continuously service the frame buffer without stalling.

@hen the "dma component completes a transaction$ it must be updated

immediately by the Nios II processor. +herefore$ "dma must have the highest

interrupt priority$ followed by the timer$0ta"-uart$ and touch;screen components.

+he lowest interrupt value indicates the highest interrupt priority. Assign interrupt

priorities to the system components by performing the following steps for each

interrupt;re>uest ,I7Q- port listed in +able /.5%

". 'lic0 the )ystem 'ontents tab.

5. 3n the left edge of the )ystem 'ontents tab$ clic0 the filter icon. +he

Filters dialog box appears.

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6. In the Filter list$ select All Interfaces.

. 'lose the Filters dialog box.

9. For each port specified in +able /.5$ perform the following steps%

In the I7Q column$ double;clic0 the connection dot.

+ype the interrupt priority value from +able /.5.

/.5 +able for interrupt priority.

Set t%e .r1itration Prioritie!

+o ensure that the video pipeline operates smoothly$ you must assign the

highest arbitration priority to "dma accesses to ddr-dram. In addition$ because

the heap memory is located in ((7 )(7A&$ you must increase the arbitration

priority of the Nios II processor for ddr=sdramto support more bac0;to;bac0 data

transactions.

+o assign arbitration priorities among the components in your system$

perform the following steps%

". 7ight;clic0 anywhere on the S$tem Content tab$ and clic0 S%ow

.r1itration S%are. +he connection panel displays the arbitration priority of each

master for each slave to which it is connected. *y default$ Qsys assigns arbitration

priority " for each connected master;slave pair.

6. For each master;slave connection in +able /.6$ double;clic0 the box that

represents the connection and type the new value from the table.

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/.6 +able for Arbitration Priority Assignments.