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Silicon LDMOS
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2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
1
Silicon RF transistors II:LDMOS
Lars VestlingUppsala University, Sweden
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
2
Outline• Introduction• Manufacturing • LDMOS Models• State-of-the-art LDMOS techniques• Future LDMOS concepts• Summary• References
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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What is a DMOS?
LDMOSLateral double-diffused MOS
VDMOSVertical double-diffused MOS
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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History
• 1969 – the first LDMOS was presented• 1972 – the LDMOS as a microwave device was presented • Switching devices
Power suppliesMotor controlsetc.....
• From mid-90‘s – Base station applicationsNMT, GSM, 3G, (900 MHz-3 GHz)Philips, Freescale (Motorola), Infineon (Ericsson)
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Base stations – RF power transistors
Base stations
Power amplifiers (PA)
RF-devices
Source: Ericsson
RF power devices has other demands than CMOS
Output powerEfficiencyLinearity
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Why LDMOS in base station applications?
Compared to Bipolar Junction Transistors (BJT)• Better linearity• Grounded substrate
source connected to substrate => no bondwire required => substrate inductance decreasedpackaging, BeO can be avioded
• Reliabilitynegtive temperature coefficient
• Higher gain
The VDMOS has some of the BJT drawbacks as well
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Typical transistor data
• Power 5-10 W up to 150 W per transistor
• Frequencies900 MHz to 2.7 GHz today
• Supply voltageVDD=26-28 V which implies a BV>60 V
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Market
• Base station applications, market share of 90% for LDMOSDevces working at 28 V, up to 2.7 GHz, gain of 15dB and efficiency of 25%.
• RF-LDMOS marketdominated by Freescale (former Motorola) with ~80% of marketothers are: Philips, Infineon, STMicroectronics
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Cross-section of a modern LDMOS device
source: Freescale
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Important transistor parameters
• ID,sat – saturated current• BV – breakdown voltage• RON vs BV – on-
resistance vs breakdown voltage
• fT, fMAX – cut-offfrequencies
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Outline• Introduction• Manufacturing• LDMOS Models• State-of-the-art LDMOS techniques• Future LDMOS concepts• Summary
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Manufacturing• Specific issues compared to CMOS• Substrate
Resistivity and epi-thickness sets BV10 Ωcm, 10 μm => BV=60-100V
• P+sinkerArea comsumingTemperature budget
• GatePolycide, gate resistanceOxide thickness, VT, BVOXGate length, Cgd, gate length not equal to channel length
• Double diffused• Channel engineering• Drain engineering• Drift region, RESURF technology
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Double-diffused
LDMOS for Power ICsSuitable for circuit integrationDevice design for avalancheruggedness
LDMOS for RFDeep p+sinker to provide substratecontactDevice design for superior RF performance
p-well and n+source are double-diffused to create the channel
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Channel engineering
• By modifying the doping in and near the channel, different behaviour can be obtained
channel length determinesspeedchannel doping level sets threshold voltage and controls punch-throughp-well curvature controlsjunction breakdown
VT Lch
NA
BV
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Drain engineering
• Used to reduce peak electric fieldTailoring doping profiles through implantation and annealing
• Minimizes IDQ drift• Do not affect BV and RON
Drain engineeringapplied in this region
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Drift region, RESURF
• RESURFREduced SURface Field
• Lateral and verticaldiodes interact to provide 2D-depletion
• Not LDMOS specificWorks for all lateral HV devices
• Charge balance• Lower RON
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Layout
• Device dividedin gate fingers to reduce gateresistance
• Exampleeach finger is 100 μmtotal width is 20 mm
Drain
Gate
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Outline• Introduction• Manufacturing• LDMOS Models• State-of-the-art LDMOS techniques• Future LDMOS concepts• Summary
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Models
• Ordinary MOS-models (SPICE) are not sufficient.• SPICE sub-circuits may solve the problem.
EnhancementMOS for channelregionJFET for drain-under-gate regionJFET or R(V,I) for extended drain
• Difficult to extractmodel parameters!
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Models - problems
• The channel/drain-endpotential, VX
Decides the channeltransistor
• How model the drift region
JFETResistor, R(I,Vgs,Vds)Analytical expressions
• All LDMOS devices are different => difficult to have a generic LDMOS model
VX
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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MOS model 20 (Philips)
• SPICE model• Combination of MOS model 9 and
MOS model 31MOS model 9 – enhancement typeMOSFET model for the channel region.MOS model 31 - junction-isolated accumulation/depletion-type MOSFETmodel. Used for the drain extension of high-voltage MOS devices.
• Model includes:charge dynamics of the drain extensionregion.not the quasi-saturation (currentcompression) effect.
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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The Chalmers model
• Generic large-signalmodel
• Analytical expression for the drain current, Ids
• Parasitics appendedC=const. or C=C(V)
L33
221 )()()(
)1()tanh())tanh(1(
pkgspkgspkgs
dsdspkds
VVPVVPVVP
VVII
−+−+−=Ψ
+⋅⋅Ψ+⋅= λα
drai
ncu
rrent
PoutPAE
drain voltage input power
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Thermal modeling
• Power devices generate heat• The heat is distributed unevenly depending on the layout• Problem characterizing the thermal properties
Pulsed measurement removes heatingPulsed S-parameter measurements with thermal chuck
• Big challenge!!!
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Outline• Introduction• Manufacturing• LDMOS Models• State-of-the-art LDMOS techniques• Future LDMOS concepts• Summary
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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What is done to improve the performance?
• Miller capacitance• Shielding• Metal sinker
Better temperature budgetLess area consuming
• MetalizationGold, AlCu
• Plastic encapsulationLower cost but worse thermal properties than ceramics
• ScalingtOX, LG, thinner substrates (<100 microns)
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Miller effect - gate-drain capacitance• Feedback capacitance
affects gainVgs must be maximizedfor max gainVgs determined by Miller capacitance
• Must minimize Cgd to minimize gain reductiondue to Miller effect
)4/()(
2
2
SS
optgsmA RV
RVgG ≈
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Shielding
1GS
2GS
1GS 2GS
IM3 vs PAE
CGD vs VDS
Example (Motorola)
Re-designing the metalshield
⇒lower CGD
⇒lower IM3
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Freescale (Motorola) MRF5S19060Typical characteristics
Power gain, GA = 14 dBDrain efficiency, ηD = 23 %IM3 = –37 dBc@ VDD=28V, IDQ=750 mA, 1960 MHz, Pout=12WBV=65 V
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Outline• Introduction• Manufacturing• LDMOS Models• State-of-the-art LDMOS techniques• Future LDMOS concepts• Summary
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Future concepts
• The supply voltage will increase to 50 V. [ITRS]• BV must increase from 60 to more than 100 V• New device concepts for higher supply voltages are needed.• Avaliable devices (28 V) can not be directly scaled to 50 V.
• Solution?:
Novel LDMOS device concept with a dual-layer extended drain region, which shields the active gate region from high voltage.
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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UU LDMOS project
• ObjectiveImplement a new type of LDMOS in a standard CMOS processBreakdown voltages above 100 V and at the same time fT and fMAX at around 10 GHzDemonstrate RF-performance for frequencies relevant to telecommunication, 1-3 GHz.
ChallengeHow to combine high voltage with a short channel?
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Standard LDMOS concept, CMOS compatible
p+
n- drift region
n+n+p-base
n+ poly
p-substrate
Source Gate Drain
kanal
• Lateral diffusion of p-base -> short channel 0.3 μm• Long poly-gate -> low gate resistance• Long drift region -> high breakdown voltage
channel
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Double depletion LDMOS
• Buried p-top => more effective drift region depletion =>higher drift region doping => lower resistance for preserved BV => higher current
p+
n- drift region
n+n+p-base
n+ poly
p-substrate
Source Gate Drain
kanal
p-top
• Lateral diffusion of p-base => short channel
• Long poly-gate => low RG
• Long drift region => high BV
channel
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Dual conduction layer LDMOS
p+
n- drift region
n+n+p-base
n+ poly
p-substrate
Source Gate Drain
kanal
n-topp-top
channel
• Buried p-top => more effective drift region depletion => higher drift region doping => lower resistancefor preserved BV => higher current
• N-top at surface => higher currentfor preserved BV
• Lateral diffusion of p-base => short channel
• Long poly-gate => low RG
• Long drift region => high BV
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Enhanced dual conduction layer LDMOS
p+
n- drift region
n+n+p-base
n+ poly
p-substrate
Source Gate Drain
kanal
n-topp-top
channel
• Buried p-top => more effective drift region depletion => higher drift region doping => lower resistancefor preserved BV => higher current
• Blanket N-top at surface => evenhigher current for preserved BV
• Lateral diffusion of p-base => short channel
• Long poly-gate => low RG
• Long drift region => high BV
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Dual depletion effect
LDMOS without p-top layerBadly distributed field over the drift region
LDMOS with p-top layerUniformly distributed field over the drift region
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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UU LDMOS – performance
• World record results were achieved.2 W/mm @ 70 V and 1 GHz1 W/mm @ 28 V and 1 GHzHigh linear gain 23dB1 W/mm @ 50 V, 3.2 GHz0.6 W/mm @ 28 V, 3.2 GHzComparablewith SiCMESFET
f=1.9 GHzVds=48 VVgs=1.1 V POUT
PAE
Input power (dBm)
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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UU LDMOS
• This device concept offersRF performance in a wide voltage rangeVery high breakdown voltages (fMAX=4 GHz @ BV=400 V)
2 6
2 7
2 8
2 9
3 0
3 1
3 2
3 3
0 .4
0 .5
0 .6
0 .7
0 .80 .91
1 0 2 0 3 0 4 0 5 0 6 0
Pou
t -3d
B c
ompr
essi
on (
dBm
)
Pout -3dB
compression (W
/mm
)
D ra in vo lta g e (V )
p a tte rn e d n -to pf= 3 .2 G H z
1
10
10 100 1000
LDMOS fT and fMAX vs BV
ftfmax
Cut
-off
frequ
ency
[GH
z]
BV [V]
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Linearity
• The linearity performance of LDMOS is very critical for the overall PA performance
• Output power normally backed-off in order to meet linearity requirements – power efficiency also drops drastically
• The linearity may be improved with some methods, e.g. combining transistors with different VT – more ideal transfer characteristic
• Major improvement can probably be achieved if the device structure itself is changed (doping profiles, dimensions etc.)
• The key is to understand the silicon
Modified device
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Better linearity with modified channel
• Simulation has shown that by changing the doping profile in the channel the transfer characteristic is improved
5678
1
2
3
4
5678
VIP3
2.22.01.81.61.41.21.00.8Gate Voltage (V)
vip3 uniform channel vip3 graded channel
A uniform channel doping provides more ideal transfer curve and has a higher VIP3 than the usual graded doping profile.This modification can be achieved with modified process stepsVIP3 is a linearity measure
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Further improvements
• Other transistor parasiticsmay also make the deviceless ideal – less linear
• Parasitics also influenceother parameters, such as output power and efficiency
• One important parasitic is the coupling to the siliconsubstrate
• This will affect the transistor output resistance in off-state
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Why off-state ROUT important?
• PA operates along a loadline.
• In on-state ROUT (Rds) is mainly determined by the channel output conductance
• The ROUT in off-statedetermines the losses.
• Affects the power efficieny of PA
VD
IDLoad line
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Cds Gd
CjsubCjs
Csub Gsub
DrainSource
Substrate
Vx
• Simulation have shown that both substrate resistivity and thickness strongly affects the off-state ROUT
• 10X improvement in off-stateoutput resistance when usinghigh resistivty bulk-Si
HR silicon substrate improves ROUT - Efficiency
(1 kΩcm)101
103
105
107
109
107 108 109 1010 1011
RO
UT
(Ωm
m)
Frequency (Hz)
Optimized 1 kΩcm substratep- epi/p+ substrate
Increasing drain voltage
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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LDMOS on SOI?
• The use of SOI may further reduce the coupling to the substrate – HR SOI may therefore be interesting
• Traditionally (CMOS) SOI also reduces other parasitics, which may lead to better overall device performance
Bulk LDMOS SOI LDMOS
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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LDMOS on SOI?
• It has been shown that very effective RESURF can be achieved on SOI substrates – good RON vs. BV
• Self-heating may be a problem• LDMOS on high resistivity SOI has shown impressive RF-
performance (40% PAE @ 7.2 GHz)• However, inversion and accumulation charge underneath
the BOX severely degrades the RF-performance, and must therefore be dealt with.
accumulationinversion
depletion
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Low-voltage LDMOS
• The LDMOS transistor may also be scaled down in voltage.• A CMOS compatible LDMOS concept enables integrated
PA solutions, e.g. mobile handsets
2
3
4
5
6
7
8
9
10
0
10
20
30
40
50
60
70
80
0 1 2 3 4
On-
Res
ista
nce
[žm
m]
Breakdow
n Voltage [V
]Gate Length [µm]
RON
BV
2
4
6
8
10
12
5
5.5
6
6.5
7
7.5
0 1 2 3 4
Freq
uenc
y [G
Hz]
Transconductance[m
S]
Gate Length [µm]
gm
fMAX
fT
RON, BV vs LG fT, fMAX, gm vs LG
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Low-voltage LDMOS - RF performance
Impressive performance with 400 V design rules!
0
5
10
15
20
25
30
0
10
20
30
40
50
60
-10 -5 0 5 10 15 20
Out
put P
ower
[dB
m]
Pow
er Added E
fficiency |%]
Input Power [dBm]
Pout
PAE
VG=3 VVD=6 Vf=1 GHz
2 mm LDMOS for on-wafer characterisation
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Outline• Introduction• Manufacturing• LDMOS Models• State-of-the-art LDMOS techniques• Future LDMOS concepts• Summary
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Summary LDMOS
• Main advantagesMajority carrier device -> carrier speed is larger than for BJTBackside source contact - reduced source inductance, no toxic BeO in the package, improved coolingHigh gainBetter thermal uniformity compared to BJTExcellent back-off linearity
• LDMOS (28V) benchmarking results showed > 5 dBc better IM3 and 2% worse efficiency @ fixed WCDMA back off power (Pavg) compared to GaAs (12V).
Adjustable BV -> Adjustable application voltageMature technologyEase of CMOS integrationReasonable ease of scaling up device size
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Summary LDMOS
• Main disadvantagesFrequency response limited by gate charging and transit time required through N- drift region -> < 3 GHz operationExcess efficiency degradation with increasing frequency operation -> Cds
Hot electron injection or IDQ drift issue
• FutureLDMOS device concept for higher voltages (required by ITRS) has successfully been demonstrated.LDMOS definitely has a bright future for RF power applications.
If you can do it in Silicon. Do it!
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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Acknowledgements
• Klas-Håkan Eklund, COMHEAT Microwave AB• Jörgen Olsson, Uppsala University
The work reported here was performed in the context of the network TARGET– “Top Amplifier Research Groups in a European Team” and supported by the Information Society Technologies Programme of the EU under contract IST-1-507893-NOE, www.target-org.net
2006-02-23 Lars Vestling - Uppsala University
Silicon RF transistors II: LDMOS
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References• J. Ankarcrona, “High Frequency Analysis of Silicon RF MOS Transistors, “ Ph.D. Theses, Uppsala University,
Uppsala, Sweden, 2005.• J. A. Appels and H. M J. Vaes, “High Voltage Thin Layer Devices (RESURF Devices), “ IEDM Tech. Dig., pp.
238-241, 1979.• H. Brech et al., “Record Efficiency and Gain at 2.1GHz of High Power RF Transistors for Cellular and 3G Base
Stations,” IEDM Tech. Dig., pp. 359-362, 2003.• W. Burger et al., “RF-LDMOS: A Device Technology for High Power RF Infrastructure Applications,” IEEE CSIC
Dig., pp. 189-192, 2004.• The International Technology Roadmap for Semiconductors, 2005, http://public.itrs.net/.• A. W. Ludikhuize et al., “Extended (180V) Voltagein 0.6um Thin-Layer-SOI A-BCD3 Technology on 1um BOX
for Display, Automotive & Consumer Applications, “ Proc. ISPSD, pp. 77-80, 2002.• Bob Metzger, “LDMOS turns up the power,” Compound Semiconductor Magazine, June 2002.• J. Olsson et al., “1 W/mm RF Power Density at 3.2 GHz for a Dual-Layer RESURF LDMOS Transistor,” IEEE
Electron Dev. Let., vol. 23, no. 4, pp. 206-208, 2002.• J. Scholvin, J. G. Fiorenza, and J. A. del Alamo, “The impact of substrate surface potential on the performance of
RF power LDMOSFETs on high-resistivity SOI,” IEDM Tech. Dig., pp. 363-366, 2003.• A. Söderbärg et al., “Integration of a Novel High-Voltage Giga-Hertz DMOS Transistor into a Standard CMOS
Process,” IEDM Tech. Dig., pp. 975-978, 1995.• L. Vestling, J. Olsson, and K.-H. Eklund, “Drift Region Optimization of Lateral RESURF Devices,” Solid-State
Electronics, vol. 46, no. 8, pp. 1177-1184, 2002.